atsamd51g/system_control/
cfsr.rs

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1#[doc = "Register `CFSR` reader"]
2pub type R = crate::R<CfsrSpec>;
3#[doc = "Register `CFSR` writer"]
4pub type W = crate::W<CfsrSpec>;
5#[doc = "Field `IACCVIOL` reader - Instruction access violation"]
6pub type IaccviolR = crate::BitReader;
7#[doc = "Field `IACCVIOL` writer - Instruction access violation"]
8pub type IaccviolW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `DACCVIOL` reader - Data access violation"]
10pub type DaccviolR = crate::BitReader;
11#[doc = "Field `DACCVIOL` writer - Data access violation"]
12pub type DaccviolW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `MUNSTKERR` reader - MemManage Fault on unstacking for exception return"]
14pub type MunstkerrR = crate::BitReader;
15#[doc = "Field `MUNSTKERR` writer - MemManage Fault on unstacking for exception return"]
16pub type MunstkerrW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `MSTKERR` reader - MemManage Fault on stacking for exception entry"]
18pub type MstkerrR = crate::BitReader;
19#[doc = "Field `MSTKERR` writer - MemManage Fault on stacking for exception entry"]
20pub type MstkerrW<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `MLSPERR` reader - MemManager Fault occured during FP lazy state preservation"]
22pub type MlsperrR = crate::BitReader;
23#[doc = "Field `MLSPERR` writer - MemManager Fault occured during FP lazy state preservation"]
24pub type MlsperrW<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `MMARVALID` reader - MemManage Fault Address Register valid"]
26pub type MmarvalidR = crate::BitReader;
27#[doc = "Field `MMARVALID` writer - MemManage Fault Address Register valid"]
28pub type MmarvalidW<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `IBUSERR` reader - Instruction bus error"]
30pub type IbuserrR = crate::BitReader;
31#[doc = "Field `IBUSERR` writer - Instruction bus error"]
32pub type IbuserrW<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `PRECISERR` reader - Precise data bus error"]
34pub type PreciserrR = crate::BitReader;
35#[doc = "Field `PRECISERR` writer - Precise data bus error"]
36pub type PreciserrW<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `IMPRECISERR` reader - Imprecise data bus error"]
38pub type ImpreciserrR = crate::BitReader;
39#[doc = "Field `IMPRECISERR` writer - Imprecise data bus error"]
40pub type ImpreciserrW<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `UNSTKERR` reader - BusFault on unstacking for exception return"]
42pub type UnstkerrR = crate::BitReader;
43#[doc = "Field `UNSTKERR` writer - BusFault on unstacking for exception return"]
44pub type UnstkerrW<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `STKERR` reader - BusFault on stacking for exception entry"]
46pub type StkerrR = crate::BitReader;
47#[doc = "Field `STKERR` writer - BusFault on stacking for exception entry"]
48pub type StkerrW<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `LSPERR` reader - BusFault occured during FP lazy state preservation"]
50pub type LsperrR = crate::BitReader;
51#[doc = "Field `LSPERR` writer - BusFault occured during FP lazy state preservation"]
52pub type LsperrW<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `BFARVALID` reader - BusFault Address Register valid"]
54pub type BfarvalidR = crate::BitReader;
55#[doc = "Field `BFARVALID` writer - BusFault Address Register valid"]
56pub type BfarvalidW<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `UNDEFINSTR` reader - Undefined instruction UsageFault"]
58pub type UndefinstrR = crate::BitReader;
59#[doc = "Field `UNDEFINSTR` writer - Undefined instruction UsageFault"]
60pub type UndefinstrW<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `INVSTATE` reader - Invalid state UsageFault"]
62pub type InvstateR = crate::BitReader;
63#[doc = "Field `INVSTATE` writer - Invalid state UsageFault"]
64pub type InvstateW<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `INVPC` reader - Invalid PC load UsageFault"]
66pub type InvpcR = crate::BitReader;
67#[doc = "Field `INVPC` writer - Invalid PC load UsageFault"]
68pub type InvpcW<'a, REG> = crate::BitWriter<'a, REG>;
69#[doc = "Field `NOCP` reader - No coprocessor UsageFault"]
70pub type NocpR = crate::BitReader;
71#[doc = "Field `NOCP` writer - No coprocessor UsageFault"]
72pub type NocpW<'a, REG> = crate::BitWriter<'a, REG>;
73#[doc = "Field `UNALIGNED` reader - Unaligned access UsageFault"]
74pub type UnalignedR = crate::BitReader;
75#[doc = "Field `UNALIGNED` writer - Unaligned access UsageFault"]
76pub type UnalignedW<'a, REG> = crate::BitWriter<'a, REG>;
77#[doc = "Field `DIVBYZERO` reader - Divide by zero UsageFault"]
78pub type DivbyzeroR = crate::BitReader;
79#[doc = "Field `DIVBYZERO` writer - Divide by zero UsageFault"]
80pub type DivbyzeroW<'a, REG> = crate::BitWriter<'a, REG>;
81impl R {
82    #[doc = "Bit 0 - Instruction access violation"]
83    #[inline(always)]
84    pub fn iaccviol(&self) -> IaccviolR {
85        IaccviolR::new((self.bits & 1) != 0)
86    }
87    #[doc = "Bit 1 - Data access violation"]
88    #[inline(always)]
89    pub fn daccviol(&self) -> DaccviolR {
90        DaccviolR::new(((self.bits >> 1) & 1) != 0)
91    }
92    #[doc = "Bit 3 - MemManage Fault on unstacking for exception return"]
93    #[inline(always)]
94    pub fn munstkerr(&self) -> MunstkerrR {
95        MunstkerrR::new(((self.bits >> 3) & 1) != 0)
96    }
97    #[doc = "Bit 4 - MemManage Fault on stacking for exception entry"]
98    #[inline(always)]
99    pub fn mstkerr(&self) -> MstkerrR {
100        MstkerrR::new(((self.bits >> 4) & 1) != 0)
101    }
102    #[doc = "Bit 5 - MemManager Fault occured during FP lazy state preservation"]
103    #[inline(always)]
104    pub fn mlsperr(&self) -> MlsperrR {
105        MlsperrR::new(((self.bits >> 5) & 1) != 0)
106    }
107    #[doc = "Bit 7 - MemManage Fault Address Register valid"]
108    #[inline(always)]
109    pub fn mmarvalid(&self) -> MmarvalidR {
110        MmarvalidR::new(((self.bits >> 7) & 1) != 0)
111    }
112    #[doc = "Bit 8 - Instruction bus error"]
113    #[inline(always)]
114    pub fn ibuserr(&self) -> IbuserrR {
115        IbuserrR::new(((self.bits >> 8) & 1) != 0)
116    }
117    #[doc = "Bit 9 - Precise data bus error"]
118    #[inline(always)]
119    pub fn preciserr(&self) -> PreciserrR {
120        PreciserrR::new(((self.bits >> 9) & 1) != 0)
121    }
122    #[doc = "Bit 10 - Imprecise data bus error"]
123    #[inline(always)]
124    pub fn impreciserr(&self) -> ImpreciserrR {
125        ImpreciserrR::new(((self.bits >> 10) & 1) != 0)
126    }
127    #[doc = "Bit 11 - BusFault on unstacking for exception return"]
128    #[inline(always)]
129    pub fn unstkerr(&self) -> UnstkerrR {
130        UnstkerrR::new(((self.bits >> 11) & 1) != 0)
131    }
132    #[doc = "Bit 12 - BusFault on stacking for exception entry"]
133    #[inline(always)]
134    pub fn stkerr(&self) -> StkerrR {
135        StkerrR::new(((self.bits >> 12) & 1) != 0)
136    }
137    #[doc = "Bit 13 - BusFault occured during FP lazy state preservation"]
138    #[inline(always)]
139    pub fn lsperr(&self) -> LsperrR {
140        LsperrR::new(((self.bits >> 13) & 1) != 0)
141    }
142    #[doc = "Bit 15 - BusFault Address Register valid"]
143    #[inline(always)]
144    pub fn bfarvalid(&self) -> BfarvalidR {
145        BfarvalidR::new(((self.bits >> 15) & 1) != 0)
146    }
147    #[doc = "Bit 16 - Undefined instruction UsageFault"]
148    #[inline(always)]
149    pub fn undefinstr(&self) -> UndefinstrR {
150        UndefinstrR::new(((self.bits >> 16) & 1) != 0)
151    }
152    #[doc = "Bit 17 - Invalid state UsageFault"]
153    #[inline(always)]
154    pub fn invstate(&self) -> InvstateR {
155        InvstateR::new(((self.bits >> 17) & 1) != 0)
156    }
157    #[doc = "Bit 18 - Invalid PC load UsageFault"]
158    #[inline(always)]
159    pub fn invpc(&self) -> InvpcR {
160        InvpcR::new(((self.bits >> 18) & 1) != 0)
161    }
162    #[doc = "Bit 19 - No coprocessor UsageFault"]
163    #[inline(always)]
164    pub fn nocp(&self) -> NocpR {
165        NocpR::new(((self.bits >> 19) & 1) != 0)
166    }
167    #[doc = "Bit 24 - Unaligned access UsageFault"]
168    #[inline(always)]
169    pub fn unaligned(&self) -> UnalignedR {
170        UnalignedR::new(((self.bits >> 24) & 1) != 0)
171    }
172    #[doc = "Bit 25 - Divide by zero UsageFault"]
173    #[inline(always)]
174    pub fn divbyzero(&self) -> DivbyzeroR {
175        DivbyzeroR::new(((self.bits >> 25) & 1) != 0)
176    }
177}
178impl W {
179    #[doc = "Bit 0 - Instruction access violation"]
180    #[inline(always)]
181    #[must_use]
182    pub fn iaccviol(&mut self) -> IaccviolW<CfsrSpec> {
183        IaccviolW::new(self, 0)
184    }
185    #[doc = "Bit 1 - Data access violation"]
186    #[inline(always)]
187    #[must_use]
188    pub fn daccviol(&mut self) -> DaccviolW<CfsrSpec> {
189        DaccviolW::new(self, 1)
190    }
191    #[doc = "Bit 3 - MemManage Fault on unstacking for exception return"]
192    #[inline(always)]
193    #[must_use]
194    pub fn munstkerr(&mut self) -> MunstkerrW<CfsrSpec> {
195        MunstkerrW::new(self, 3)
196    }
197    #[doc = "Bit 4 - MemManage Fault on stacking for exception entry"]
198    #[inline(always)]
199    #[must_use]
200    pub fn mstkerr(&mut self) -> MstkerrW<CfsrSpec> {
201        MstkerrW::new(self, 4)
202    }
203    #[doc = "Bit 5 - MemManager Fault occured during FP lazy state preservation"]
204    #[inline(always)]
205    #[must_use]
206    pub fn mlsperr(&mut self) -> MlsperrW<CfsrSpec> {
207        MlsperrW::new(self, 5)
208    }
209    #[doc = "Bit 7 - MemManage Fault Address Register valid"]
210    #[inline(always)]
211    #[must_use]
212    pub fn mmarvalid(&mut self) -> MmarvalidW<CfsrSpec> {
213        MmarvalidW::new(self, 7)
214    }
215    #[doc = "Bit 8 - Instruction bus error"]
216    #[inline(always)]
217    #[must_use]
218    pub fn ibuserr(&mut self) -> IbuserrW<CfsrSpec> {
219        IbuserrW::new(self, 8)
220    }
221    #[doc = "Bit 9 - Precise data bus error"]
222    #[inline(always)]
223    #[must_use]
224    pub fn preciserr(&mut self) -> PreciserrW<CfsrSpec> {
225        PreciserrW::new(self, 9)
226    }
227    #[doc = "Bit 10 - Imprecise data bus error"]
228    #[inline(always)]
229    #[must_use]
230    pub fn impreciserr(&mut self) -> ImpreciserrW<CfsrSpec> {
231        ImpreciserrW::new(self, 10)
232    }
233    #[doc = "Bit 11 - BusFault on unstacking for exception return"]
234    #[inline(always)]
235    #[must_use]
236    pub fn unstkerr(&mut self) -> UnstkerrW<CfsrSpec> {
237        UnstkerrW::new(self, 11)
238    }
239    #[doc = "Bit 12 - BusFault on stacking for exception entry"]
240    #[inline(always)]
241    #[must_use]
242    pub fn stkerr(&mut self) -> StkerrW<CfsrSpec> {
243        StkerrW::new(self, 12)
244    }
245    #[doc = "Bit 13 - BusFault occured during FP lazy state preservation"]
246    #[inline(always)]
247    #[must_use]
248    pub fn lsperr(&mut self) -> LsperrW<CfsrSpec> {
249        LsperrW::new(self, 13)
250    }
251    #[doc = "Bit 15 - BusFault Address Register valid"]
252    #[inline(always)]
253    #[must_use]
254    pub fn bfarvalid(&mut self) -> BfarvalidW<CfsrSpec> {
255        BfarvalidW::new(self, 15)
256    }
257    #[doc = "Bit 16 - Undefined instruction UsageFault"]
258    #[inline(always)]
259    #[must_use]
260    pub fn undefinstr(&mut self) -> UndefinstrW<CfsrSpec> {
261        UndefinstrW::new(self, 16)
262    }
263    #[doc = "Bit 17 - Invalid state UsageFault"]
264    #[inline(always)]
265    #[must_use]
266    pub fn invstate(&mut self) -> InvstateW<CfsrSpec> {
267        InvstateW::new(self, 17)
268    }
269    #[doc = "Bit 18 - Invalid PC load UsageFault"]
270    #[inline(always)]
271    #[must_use]
272    pub fn invpc(&mut self) -> InvpcW<CfsrSpec> {
273        InvpcW::new(self, 18)
274    }
275    #[doc = "Bit 19 - No coprocessor UsageFault"]
276    #[inline(always)]
277    #[must_use]
278    pub fn nocp(&mut self) -> NocpW<CfsrSpec> {
279        NocpW::new(self, 19)
280    }
281    #[doc = "Bit 24 - Unaligned access UsageFault"]
282    #[inline(always)]
283    #[must_use]
284    pub fn unaligned(&mut self) -> UnalignedW<CfsrSpec> {
285        UnalignedW::new(self, 24)
286    }
287    #[doc = "Bit 25 - Divide by zero UsageFault"]
288    #[inline(always)]
289    #[must_use]
290    pub fn divbyzero(&mut self) -> DivbyzeroW<CfsrSpec> {
291        DivbyzeroW::new(self, 25)
292    }
293}
294#[doc = "Configurable Fault Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cfsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
295pub struct CfsrSpec;
296impl crate::RegisterSpec for CfsrSpec {
297    type Ux = u32;
298}
299#[doc = "`read()` method returns [`cfsr::R`](R) reader structure"]
300impl crate::Readable for CfsrSpec {}
301#[doc = "`write(|w| ..)` method takes [`cfsr::W`](W) writer structure"]
302impl crate::Writable for CfsrSpec {
303    type Safety = crate::Unsafe;
304    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
305    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
306}
307#[doc = "`reset()` method sets CFSR to value 0"]
308impl crate::Resettable for CfsrSpec {
309    const RESET_VALUE: u32 = 0;
310}
atsamd51g/system_control/cfsr.rs

atsamd51g/system_control/
cfsr.rs
