atsamd51g/sercom0/spis/
ctrlb.rs

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1#[doc = "Register `CTRLB` reader"]
2pub type R = crate::R<CtrlbSpec>;
3#[doc = "Register `CTRLB` writer"]
4pub type W = crate::W<CtrlbSpec>;
5#[doc = "Character Size\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7#[repr(u8)]
8pub enum Chsizeselect {
9    #[doc = "0: 8 bits"]
10    _8Bit = 0,
11    #[doc = "1: 9 bits"]
12    _9Bit = 1,
13}
14impl From<Chsizeselect> for u8 {
15    #[inline(always)]
16    fn from(variant: Chsizeselect) -> Self {
17        variant as _
18    }
19}
20impl crate::FieldSpec for Chsizeselect {
21    type Ux = u8;
22}
23impl crate::IsEnum for Chsizeselect {}
24#[doc = "Field `CHSIZE` reader - Character Size"]
25pub type ChsizeR = crate::FieldReader<Chsizeselect>;
26impl ChsizeR {
27    #[doc = "Get enumerated values variant"]
28    #[inline(always)]
29    pub const fn variant(&self) -> Option<Chsizeselect> {
30        match self.bits {
31            0 => Some(Chsizeselect::_8Bit),
32            1 => Some(Chsizeselect::_9Bit),
33            _ => None,
34        }
35    }
36    #[doc = "8 bits"]
37    #[inline(always)]
38    pub fn is_8_bit(&self) -> bool {
39        *self == Chsizeselect::_8Bit
40    }
41    #[doc = "9 bits"]
42    #[inline(always)]
43    pub fn is_9_bit(&self) -> bool {
44        *self == Chsizeselect::_9Bit
45    }
46}
47#[doc = "Field `CHSIZE` writer - Character Size"]
48pub type ChsizeW<'a, REG> = crate::FieldWriter<'a, REG, 3, Chsizeselect>;
49impl<'a, REG> ChsizeW<'a, REG>
50where
51    REG: crate::Writable + crate::RegisterSpec,
52    REG::Ux: From<u8>,
53{
54    #[doc = "8 bits"]
55    #[inline(always)]
56    pub fn _8_bit(self) -> &'a mut crate::W<REG> {
57        self.variant(Chsizeselect::_8Bit)
58    }
59    #[doc = "9 bits"]
60    #[inline(always)]
61    pub fn _9_bit(self) -> &'a mut crate::W<REG> {
62        self.variant(Chsizeselect::_9Bit)
63    }
64}
65#[doc = "Field `PLOADEN` reader - Data Preload Enable"]
66pub type PloadenR = crate::BitReader;
67#[doc = "Field `PLOADEN` writer - Data Preload Enable"]
68pub type PloadenW<'a, REG> = crate::BitWriter<'a, REG>;
69#[doc = "Field `SSDE` reader - Slave Select Low Detect Enable"]
70pub type SsdeR = crate::BitReader;
71#[doc = "Field `SSDE` writer - Slave Select Low Detect Enable"]
72pub type SsdeW<'a, REG> = crate::BitWriter<'a, REG>;
73#[doc = "Field `MSSEN` reader - Master Slave Select Enable"]
74pub type MssenR = crate::BitReader;
75#[doc = "Field `MSSEN` writer - Master Slave Select Enable"]
76pub type MssenW<'a, REG> = crate::BitWriter<'a, REG>;
77#[doc = "Address Mode\n\nValue on reset: 0"]
78#[derive(Clone, Copy, Debug, PartialEq, Eq)]
79#[repr(u8)]
80pub enum Amodeselect {
81    #[doc = "0: SPI Address mask"]
82    Mask = 0,
83    #[doc = "1: Two unique Addressess"]
84    _2Addresses = 1,
85    #[doc = "2: Address Range"]
86    Range = 2,
87}
88impl From<Amodeselect> for u8 {
89    #[inline(always)]
90    fn from(variant: Amodeselect) -> Self {
91        variant as _
92    }
93}
94impl crate::FieldSpec for Amodeselect {
95    type Ux = u8;
96}
97impl crate::IsEnum for Amodeselect {}
98#[doc = "Field `AMODE` reader - Address Mode"]
99pub type AmodeR = crate::FieldReader<Amodeselect>;
100impl AmodeR {
101    #[doc = "Get enumerated values variant"]
102    #[inline(always)]
103    pub const fn variant(&self) -> Option<Amodeselect> {
104        match self.bits {
105            0 => Some(Amodeselect::Mask),
106            1 => Some(Amodeselect::_2Addresses),
107            2 => Some(Amodeselect::Range),
108            _ => None,
109        }
110    }
111    #[doc = "SPI Address mask"]
112    #[inline(always)]
113    pub fn is_mask(&self) -> bool {
114        *self == Amodeselect::Mask
115    }
116    #[doc = "Two unique Addressess"]
117    #[inline(always)]
118    pub fn is_2_addresses(&self) -> bool {
119        *self == Amodeselect::_2Addresses
120    }
121    #[doc = "Address Range"]
122    #[inline(always)]
123    pub fn is_range(&self) -> bool {
124        *self == Amodeselect::Range
125    }
126}
127#[doc = "Field `AMODE` writer - Address Mode"]
128pub type AmodeW<'a, REG> = crate::FieldWriter<'a, REG, 2, Amodeselect>;
129impl<'a, REG> AmodeW<'a, REG>
130where
131    REG: crate::Writable + crate::RegisterSpec,
132    REG::Ux: From<u8>,
133{
134    #[doc = "SPI Address mask"]
135    #[inline(always)]
136    pub fn mask(self) -> &'a mut crate::W<REG> {
137        self.variant(Amodeselect::Mask)
138    }
139    #[doc = "Two unique Addressess"]
140    #[inline(always)]
141    pub fn _2_addresses(self) -> &'a mut crate::W<REG> {
142        self.variant(Amodeselect::_2Addresses)
143    }
144    #[doc = "Address Range"]
145    #[inline(always)]
146    pub fn range(self) -> &'a mut crate::W<REG> {
147        self.variant(Amodeselect::Range)
148    }
149}
150#[doc = "Field `RXEN` reader - Receiver Enable"]
151pub type RxenR = crate::BitReader;
152#[doc = "Field `RXEN` writer - Receiver Enable"]
153pub type RxenW<'a, REG> = crate::BitWriter<'a, REG>;
154impl R {
155    #[doc = "Bits 0:2 - Character Size"]
156    #[inline(always)]
157    pub fn chsize(&self) -> ChsizeR {
158        ChsizeR::new((self.bits & 7) as u8)
159    }
160    #[doc = "Bit 6 - Data Preload Enable"]
161    #[inline(always)]
162    pub fn ploaden(&self) -> PloadenR {
163        PloadenR::new(((self.bits >> 6) & 1) != 0)
164    }
165    #[doc = "Bit 9 - Slave Select Low Detect Enable"]
166    #[inline(always)]
167    pub fn ssde(&self) -> SsdeR {
168        SsdeR::new(((self.bits >> 9) & 1) != 0)
169    }
170    #[doc = "Bit 13 - Master Slave Select Enable"]
171    #[inline(always)]
172    pub fn mssen(&self) -> MssenR {
173        MssenR::new(((self.bits >> 13) & 1) != 0)
174    }
175    #[doc = "Bits 14:15 - Address Mode"]
176    #[inline(always)]
177    pub fn amode(&self) -> AmodeR {
178        AmodeR::new(((self.bits >> 14) & 3) as u8)
179    }
180    #[doc = "Bit 17 - Receiver Enable"]
181    #[inline(always)]
182    pub fn rxen(&self) -> RxenR {
183        RxenR::new(((self.bits >> 17) & 1) != 0)
184    }
185}
186impl W {
187    #[doc = "Bits 0:2 - Character Size"]
188    #[inline(always)]
189    #[must_use]
190    pub fn chsize(&mut self) -> ChsizeW<CtrlbSpec> {
191        ChsizeW::new(self, 0)
192    }
193    #[doc = "Bit 6 - Data Preload Enable"]
194    #[inline(always)]
195    #[must_use]
196    pub fn ploaden(&mut self) -> PloadenW<CtrlbSpec> {
197        PloadenW::new(self, 6)
198    }
199    #[doc = "Bit 9 - Slave Select Low Detect Enable"]
200    #[inline(always)]
201    #[must_use]
202    pub fn ssde(&mut self) -> SsdeW<CtrlbSpec> {
203        SsdeW::new(self, 9)
204    }
205    #[doc = "Bit 13 - Master Slave Select Enable"]
206    #[inline(always)]
207    #[must_use]
208    pub fn mssen(&mut self) -> MssenW<CtrlbSpec> {
209        MssenW::new(self, 13)
210    }
211    #[doc = "Bits 14:15 - Address Mode"]
212    #[inline(always)]
213    #[must_use]
214    pub fn amode(&mut self) -> AmodeW<CtrlbSpec> {
215        AmodeW::new(self, 14)
216    }
217    #[doc = "Bit 17 - Receiver Enable"]
218    #[inline(always)]
219    #[must_use]
220    pub fn rxen(&mut self) -> RxenW<CtrlbSpec> {
221        RxenW::new(self, 17)
222    }
223}
224#[doc = "SPIS Control B\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrlb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrlb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
225pub struct CtrlbSpec;
226impl crate::RegisterSpec for CtrlbSpec {
227    type Ux = u32;
228}
229#[doc = "`read()` method returns [`ctrlb::R`](R) reader structure"]
230impl crate::Readable for CtrlbSpec {}
231#[doc = "`write(|w| ..)` method takes [`ctrlb::W`](W) writer structure"]
232impl crate::Writable for CtrlbSpec {
233    type Safety = crate::Unsafe;
234    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
235    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
236}
237#[doc = "`reset()` method sets CTRLB to value 0"]
238impl crate::Resettable for CtrlbSpec {
239    const RESET_VALUE: u32 = 0;
240}
atsamd51g/sercom0/spis/ctrlb.rs

atsamd51g/sercom0/spis/
ctrlb.rs
