atsamd51g/port/group/
dirclr.rs

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1#[doc = "Register `DIRCLR` reader"]
2pub type R = crate::R<DirclrSpec>;
3#[doc = "Register `DIRCLR` writer"]
4pub type W = crate::W<DirclrSpec>;
5#[doc = "Field `DIRCLR` reader - Port Data Direction Clear"]
6pub type DirclrR = crate::FieldReader<u32>;
7#[doc = "Field `DIRCLR` writer - Port Data Direction Clear"]
8pub type DirclrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
9impl R {
10    #[doc = "Bits 0:31 - Port Data Direction Clear"]
11    #[inline(always)]
12    pub fn dirclr(&self) -> DirclrR {
13        DirclrR::new(self.bits)
14    }
15}
16impl W {
17    #[doc = "Bits 0:31 - Port Data Direction Clear"]
18    #[inline(always)]
19    #[must_use]
20    pub fn dirclr(&mut self) -> DirclrW<DirclrSpec> {
21        DirclrW::new(self, 0)
22    }
23}
24#[doc = "Data Direction Clear\n\nYou can [`read`](crate::Reg::read) this register and get [`dirclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dirclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
25pub struct DirclrSpec;
26impl crate::RegisterSpec for DirclrSpec {
27    type Ux = u32;
28}
29#[doc = "`read()` method returns [`dirclr::R`](R) reader structure"]
30impl crate::Readable for DirclrSpec {}
31#[doc = "`write(|w| ..)` method takes [`dirclr::W`](W) writer structure"]
32impl crate::Writable for DirclrSpec {
33    type Safety = crate::Unsafe;
34    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
35    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
36}
37#[doc = "`reset()` method sets DIRCLR to value 0"]
38impl crate::Resettable for DirclrSpec {
39    const RESET_VALUE: u32 = 0;
40}
atsamd51g/port/group/dirclr.rs

atsamd51g/port/group/
dirclr.rs
