atsamd51g/mclk/
apbbmask.rs

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1#[doc = "Register `APBBMASK` reader"]
2pub type R = crate::R<ApbbmaskSpec>;
3#[doc = "Register `APBBMASK` writer"]
4pub type W = crate::W<ApbbmaskSpec>;
5#[doc = "Field `USB_` reader - USB APB Clock Enable"]
6pub type Usb_R = crate::BitReader;
7#[doc = "Field `USB_` writer - USB APB Clock Enable"]
8pub type Usb_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `DSU_` reader - DSU APB Clock Enable"]
10pub type Dsu_R = crate::BitReader;
11#[doc = "Field `DSU_` writer - DSU APB Clock Enable"]
12pub type Dsu_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `NVMCTRL_` reader - NVMCTRL APB Clock Enable"]
14pub type Nvmctrl_R = crate::BitReader;
15#[doc = "Field `NVMCTRL_` writer - NVMCTRL APB Clock Enable"]
16pub type Nvmctrl_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `PORT_` reader - PORT APB Clock Enable"]
18pub type Port_R = crate::BitReader;
19#[doc = "Field `PORT_` writer - PORT APB Clock Enable"]
20pub type Port_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `EVSYS_` reader - EVSYS APB Clock Enable"]
22pub type Evsys_R = crate::BitReader;
23#[doc = "Field `EVSYS_` writer - EVSYS APB Clock Enable"]
24pub type Evsys_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `SERCOM2_` reader - SERCOM2 APB Clock Enable"]
26pub type Sercom2_R = crate::BitReader;
27#[doc = "Field `SERCOM2_` writer - SERCOM2 APB Clock Enable"]
28pub type Sercom2_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `SERCOM3_` reader - SERCOM3 APB Clock Enable"]
30pub type Sercom3_R = crate::BitReader;
31#[doc = "Field `SERCOM3_` writer - SERCOM3 APB Clock Enable"]
32pub type Sercom3_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `TCC0_` reader - TCC0 APB Clock Enable"]
34pub type Tcc0_R = crate::BitReader;
35#[doc = "Field `TCC0_` writer - TCC0 APB Clock Enable"]
36pub type Tcc0_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `TCC1_` reader - TCC1 APB Clock Enable"]
38pub type Tcc1_R = crate::BitReader;
39#[doc = "Field `TCC1_` writer - TCC1 APB Clock Enable"]
40pub type Tcc1_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `TC2_` reader - TC2 APB Clock Enable"]
42pub type Tc2_R = crate::BitReader;
43#[doc = "Field `TC2_` writer - TC2 APB Clock Enable"]
44pub type Tc2_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `TC3_` reader - TC3 APB Clock Enable"]
46pub type Tc3_R = crate::BitReader;
47#[doc = "Field `TC3_` writer - TC3 APB Clock Enable"]
48pub type Tc3_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `RAMECC_` reader - RAMECC APB Clock Enable"]
50pub type Ramecc_R = crate::BitReader;
51#[doc = "Field `RAMECC_` writer - RAMECC APB Clock Enable"]
52pub type Ramecc_W<'a, REG> = crate::BitWriter<'a, REG>;
53impl R {
54    #[doc = "Bit 0 - USB APB Clock Enable"]
55    #[inline(always)]
56    pub fn usb_(&self) -> Usb_R {
57        Usb_R::new((self.bits & 1) != 0)
58    }
59    #[doc = "Bit 1 - DSU APB Clock Enable"]
60    #[inline(always)]
61    pub fn dsu_(&self) -> Dsu_R {
62        Dsu_R::new(((self.bits >> 1) & 1) != 0)
63    }
64    #[doc = "Bit 2 - NVMCTRL APB Clock Enable"]
65    #[inline(always)]
66    pub fn nvmctrl_(&self) -> Nvmctrl_R {
67        Nvmctrl_R::new(((self.bits >> 2) & 1) != 0)
68    }
69    #[doc = "Bit 4 - PORT APB Clock Enable"]
70    #[inline(always)]
71    pub fn port_(&self) -> Port_R {
72        Port_R::new(((self.bits >> 4) & 1) != 0)
73    }
74    #[doc = "Bit 7 - EVSYS APB Clock Enable"]
75    #[inline(always)]
76    pub fn evsys_(&self) -> Evsys_R {
77        Evsys_R::new(((self.bits >> 7) & 1) != 0)
78    }
79    #[doc = "Bit 9 - SERCOM2 APB Clock Enable"]
80    #[inline(always)]
81    pub fn sercom2_(&self) -> Sercom2_R {
82        Sercom2_R::new(((self.bits >> 9) & 1) != 0)
83    }
84    #[doc = "Bit 10 - SERCOM3 APB Clock Enable"]
85    #[inline(always)]
86    pub fn sercom3_(&self) -> Sercom3_R {
87        Sercom3_R::new(((self.bits >> 10) & 1) != 0)
88    }
89    #[doc = "Bit 11 - TCC0 APB Clock Enable"]
90    #[inline(always)]
91    pub fn tcc0_(&self) -> Tcc0_R {
92        Tcc0_R::new(((self.bits >> 11) & 1) != 0)
93    }
94    #[doc = "Bit 12 - TCC1 APB Clock Enable"]
95    #[inline(always)]
96    pub fn tcc1_(&self) -> Tcc1_R {
97        Tcc1_R::new(((self.bits >> 12) & 1) != 0)
98    }
99    #[doc = "Bit 13 - TC2 APB Clock Enable"]
100    #[inline(always)]
101    pub fn tc2_(&self) -> Tc2_R {
102        Tc2_R::new(((self.bits >> 13) & 1) != 0)
103    }
104    #[doc = "Bit 14 - TC3 APB Clock Enable"]
105    #[inline(always)]
106    pub fn tc3_(&self) -> Tc3_R {
107        Tc3_R::new(((self.bits >> 14) & 1) != 0)
108    }
109    #[doc = "Bit 16 - RAMECC APB Clock Enable"]
110    #[inline(always)]
111    pub fn ramecc_(&self) -> Ramecc_R {
112        Ramecc_R::new(((self.bits >> 16) & 1) != 0)
113    }
114}
115impl W {
116    #[doc = "Bit 0 - USB APB Clock Enable"]
117    #[inline(always)]
118    #[must_use]
119    pub fn usb_(&mut self) -> Usb_W<ApbbmaskSpec> {
120        Usb_W::new(self, 0)
121    }
122    #[doc = "Bit 1 - DSU APB Clock Enable"]
123    #[inline(always)]
124    #[must_use]
125    pub fn dsu_(&mut self) -> Dsu_W<ApbbmaskSpec> {
126        Dsu_W::new(self, 1)
127    }
128    #[doc = "Bit 2 - NVMCTRL APB Clock Enable"]
129    #[inline(always)]
130    #[must_use]
131    pub fn nvmctrl_(&mut self) -> Nvmctrl_W<ApbbmaskSpec> {
132        Nvmctrl_W::new(self, 2)
133    }
134    #[doc = "Bit 4 - PORT APB Clock Enable"]
135    #[inline(always)]
136    #[must_use]
137    pub fn port_(&mut self) -> Port_W<ApbbmaskSpec> {
138        Port_W::new(self, 4)
139    }
140    #[doc = "Bit 7 - EVSYS APB Clock Enable"]
141    #[inline(always)]
142    #[must_use]
143    pub fn evsys_(&mut self) -> Evsys_W<ApbbmaskSpec> {
144        Evsys_W::new(self, 7)
145    }
146    #[doc = "Bit 9 - SERCOM2 APB Clock Enable"]
147    #[inline(always)]
148    #[must_use]
149    pub fn sercom2_(&mut self) -> Sercom2_W<ApbbmaskSpec> {
150        Sercom2_W::new(self, 9)
151    }
152    #[doc = "Bit 10 - SERCOM3 APB Clock Enable"]
153    #[inline(always)]
154    #[must_use]
155    pub fn sercom3_(&mut self) -> Sercom3_W<ApbbmaskSpec> {
156        Sercom3_W::new(self, 10)
157    }
158    #[doc = "Bit 11 - TCC0 APB Clock Enable"]
159    #[inline(always)]
160    #[must_use]
161    pub fn tcc0_(&mut self) -> Tcc0_W<ApbbmaskSpec> {
162        Tcc0_W::new(self, 11)
163    }
164    #[doc = "Bit 12 - TCC1 APB Clock Enable"]
165    #[inline(always)]
166    #[must_use]
167    pub fn tcc1_(&mut self) -> Tcc1_W<ApbbmaskSpec> {
168        Tcc1_W::new(self, 12)
169    }
170    #[doc = "Bit 13 - TC2 APB Clock Enable"]
171    #[inline(always)]
172    #[must_use]
173    pub fn tc2_(&mut self) -> Tc2_W<ApbbmaskSpec> {
174        Tc2_W::new(self, 13)
175    }
176    #[doc = "Bit 14 - TC3 APB Clock Enable"]
177    #[inline(always)]
178    #[must_use]
179    pub fn tc3_(&mut self) -> Tc3_W<ApbbmaskSpec> {
180        Tc3_W::new(self, 14)
181    }
182    #[doc = "Bit 16 - RAMECC APB Clock Enable"]
183    #[inline(always)]
184    #[must_use]
185    pub fn ramecc_(&mut self) -> Ramecc_W<ApbbmaskSpec> {
186        Ramecc_W::new(self, 16)
187    }
188}
189#[doc = "APBB Mask\n\nYou can [`read`](crate::Reg::read) this register and get [`apbbmask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apbbmask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
190pub struct ApbbmaskSpec;
191impl crate::RegisterSpec for ApbbmaskSpec {
192    type Ux = u32;
193}
194#[doc = "`read()` method returns [`apbbmask::R`](R) reader structure"]
195impl crate::Readable for ApbbmaskSpec {}
196#[doc = "`write(|w| ..)` method takes [`apbbmask::W`](W) writer structure"]
197impl crate::Writable for ApbbmaskSpec {
198    type Safety = crate::Unsafe;
199    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
200    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
201}
202#[doc = "`reset()` method sets APBBMASK to value 0x0001_8056"]
203impl crate::Resettable for ApbbmaskSpec {
204    const RESET_VALUE: u32 = 0x0001_8056;
205}
atsamd51g/mclk/apbbmask.rs

atsamd51g/mclk/
apbbmask.rs
