atsamd51g/sdhc0/
hc2r_emmc_mode.rs

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1#[doc = "Register `HC2R_EMMC_MODE` reader"]
2pub type R = crate::R<Hc2rEmmcModeSpec>;
3#[doc = "Register `HC2R_EMMC_MODE` writer"]
4pub type W = crate::W<Hc2rEmmcModeSpec>;
5#[doc = "HS200 Mode Enable\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7#[repr(u8)]
8pub enum Hs200enselect {
9    #[doc = "0: SDR12"]
10    Sdr12 = 0,
11    #[doc = "1: SDR25"]
12    Sdr25 = 1,
13    #[doc = "2: SDR50"]
14    Sdr50 = 2,
15    #[doc = "3: SDR104"]
16    Sdr104 = 3,
17    #[doc = "4: DDR50"]
18    Ddr50 = 4,
19}
20impl From<Hs200enselect> for u8 {
21    #[inline(always)]
22    fn from(variant: Hs200enselect) -> Self {
23        variant as _
24    }
25}
26impl crate::FieldSpec for Hs200enselect {
27    type Ux = u8;
28}
29impl crate::IsEnum for Hs200enselect {}
30#[doc = "Field `HS200EN` reader - HS200 Mode Enable"]
31pub type Hs200enR = crate::FieldReader<Hs200enselect>;
32impl Hs200enR {
33    #[doc = "Get enumerated values variant"]
34    #[inline(always)]
35    pub const fn variant(&self) -> Option<Hs200enselect> {
36        match self.bits {
37            0 => Some(Hs200enselect::Sdr12),
38            1 => Some(Hs200enselect::Sdr25),
39            2 => Some(Hs200enselect::Sdr50),
40            3 => Some(Hs200enselect::Sdr104),
41            4 => Some(Hs200enselect::Ddr50),
42            _ => None,
43        }
44    }
45    #[doc = "SDR12"]
46    #[inline(always)]
47    pub fn is_sdr12(&self) -> bool {
48        *self == Hs200enselect::Sdr12
49    }
50    #[doc = "SDR25"]
51    #[inline(always)]
52    pub fn is_sdr25(&self) -> bool {
53        *self == Hs200enselect::Sdr25
54    }
55    #[doc = "SDR50"]
56    #[inline(always)]
57    pub fn is_sdr50(&self) -> bool {
58        *self == Hs200enselect::Sdr50
59    }
60    #[doc = "SDR104"]
61    #[inline(always)]
62    pub fn is_sdr104(&self) -> bool {
63        *self == Hs200enselect::Sdr104
64    }
65    #[doc = "DDR50"]
66    #[inline(always)]
67    pub fn is_ddr50(&self) -> bool {
68        *self == Hs200enselect::Ddr50
69    }
70}
71#[doc = "Field `HS200EN` writer - HS200 Mode Enable"]
72pub type Hs200enW<'a, REG> = crate::FieldWriter<'a, REG, 4, Hs200enselect>;
73impl<'a, REG> Hs200enW<'a, REG>
74where
75    REG: crate::Writable + crate::RegisterSpec,
76    REG::Ux: From<u8>,
77{
78    #[doc = "SDR12"]
79    #[inline(always)]
80    pub fn sdr12(self) -> &'a mut crate::W<REG> {
81        self.variant(Hs200enselect::Sdr12)
82    }
83    #[doc = "SDR25"]
84    #[inline(always)]
85    pub fn sdr25(self) -> &'a mut crate::W<REG> {
86        self.variant(Hs200enselect::Sdr25)
87    }
88    #[doc = "SDR50"]
89    #[inline(always)]
90    pub fn sdr50(self) -> &'a mut crate::W<REG> {
91        self.variant(Hs200enselect::Sdr50)
92    }
93    #[doc = "SDR104"]
94    #[inline(always)]
95    pub fn sdr104(self) -> &'a mut crate::W<REG> {
96        self.variant(Hs200enselect::Sdr104)
97    }
98    #[doc = "DDR50"]
99    #[inline(always)]
100    pub fn ddr50(self) -> &'a mut crate::W<REG> {
101        self.variant(Hs200enselect::Ddr50)
102    }
103}
104#[doc = "Driver Strength Select\n\nValue on reset: 0"]
105#[derive(Clone, Copy, Debug, PartialEq, Eq)]
106#[repr(u8)]
107pub enum Drvselselect {
108    #[doc = "0: Driver Type B is Selected (Default)"]
109    B = 0,
110    #[doc = "1: Driver Type A is Selected"]
111    A = 1,
112    #[doc = "2: Driver Type C is Selected"]
113    C = 2,
114    #[doc = "3: Driver Type D is Selected"]
115    D = 3,
116}
117impl From<Drvselselect> for u8 {
118    #[inline(always)]
119    fn from(variant: Drvselselect) -> Self {
120        variant as _
121    }
122}
123impl crate::FieldSpec for Drvselselect {
124    type Ux = u8;
125}
126impl crate::IsEnum for Drvselselect {}
127#[doc = "Field `DRVSEL` reader - Driver Strength Select"]
128pub type DrvselR = crate::FieldReader<Drvselselect>;
129impl DrvselR {
130    #[doc = "Get enumerated values variant"]
131    #[inline(always)]
132    pub const fn variant(&self) -> Drvselselect {
133        match self.bits {
134            0 => Drvselselect::B,
135            1 => Drvselselect::A,
136            2 => Drvselselect::C,
137            3 => Drvselselect::D,
138            _ => unreachable!(),
139        }
140    }
141    #[doc = "Driver Type B is Selected (Default)"]
142    #[inline(always)]
143    pub fn is_b(&self) -> bool {
144        *self == Drvselselect::B
145    }
146    #[doc = "Driver Type A is Selected"]
147    #[inline(always)]
148    pub fn is_a(&self) -> bool {
149        *self == Drvselselect::A
150    }
151    #[doc = "Driver Type C is Selected"]
152    #[inline(always)]
153    pub fn is_c(&self) -> bool {
154        *self == Drvselselect::C
155    }
156    #[doc = "Driver Type D is Selected"]
157    #[inline(always)]
158    pub fn is_d(&self) -> bool {
159        *self == Drvselselect::D
160    }
161}
162#[doc = "Field `DRVSEL` writer - Driver Strength Select"]
163pub type DrvselW<'a, REG> = crate::FieldWriter<'a, REG, 2, Drvselselect, crate::Safe>;
164impl<'a, REG> DrvselW<'a, REG>
165where
166    REG: crate::Writable + crate::RegisterSpec,
167    REG::Ux: From<u8>,
168{
169    #[doc = "Driver Type B is Selected (Default)"]
170    #[inline(always)]
171    pub fn b(self) -> &'a mut crate::W<REG> {
172        self.variant(Drvselselect::B)
173    }
174    #[doc = "Driver Type A is Selected"]
175    #[inline(always)]
176    pub fn a(self) -> &'a mut crate::W<REG> {
177        self.variant(Drvselselect::A)
178    }
179    #[doc = "Driver Type C is Selected"]
180    #[inline(always)]
181    pub fn c(self) -> &'a mut crate::W<REG> {
182        self.variant(Drvselselect::C)
183    }
184    #[doc = "Driver Type D is Selected"]
185    #[inline(always)]
186    pub fn d(self) -> &'a mut crate::W<REG> {
187        self.variant(Drvselselect::D)
188    }
189}
190#[doc = "Execute Tuning\n\nValue on reset: 0"]
191#[derive(Clone, Copy, Debug, PartialEq, Eq)]
192pub enum Extunselect {
193    #[doc = "0: Not Tuned or Tuning Completed"]
194    No = 0,
195    #[doc = "1: Execute Tuning"]
196    Requested = 1,
197}
198impl From<Extunselect> for bool {
199    #[inline(always)]
200    fn from(variant: Extunselect) -> Self {
201        variant as u8 != 0
202    }
203}
204#[doc = "Field `EXTUN` reader - Execute Tuning"]
205pub type ExtunR = crate::BitReader<Extunselect>;
206impl ExtunR {
207    #[doc = "Get enumerated values variant"]
208    #[inline(always)]
209    pub const fn variant(&self) -> Extunselect {
210        match self.bits {
211            false => Extunselect::No,
212            true => Extunselect::Requested,
213        }
214    }
215    #[doc = "Not Tuned or Tuning Completed"]
216    #[inline(always)]
217    pub fn is_no(&self) -> bool {
218        *self == Extunselect::No
219    }
220    #[doc = "Execute Tuning"]
221    #[inline(always)]
222    pub fn is_requested(&self) -> bool {
223        *self == Extunselect::Requested
224    }
225}
226#[doc = "Field `EXTUN` writer - Execute Tuning"]
227pub type ExtunW<'a, REG> = crate::BitWriter<'a, REG, Extunselect>;
228impl<'a, REG> ExtunW<'a, REG>
229where
230    REG: crate::Writable + crate::RegisterSpec,
231{
232    #[doc = "Not Tuned or Tuning Completed"]
233    #[inline(always)]
234    pub fn no(self) -> &'a mut crate::W<REG> {
235        self.variant(Extunselect::No)
236    }
237    #[doc = "Execute Tuning"]
238    #[inline(always)]
239    pub fn requested(self) -> &'a mut crate::W<REG> {
240        self.variant(Extunselect::Requested)
241    }
242}
243#[doc = "Sampling Clock Select\n\nValue on reset: 0"]
244#[derive(Clone, Copy, Debug, PartialEq, Eq)]
245pub enum Slckselselect {
246    #[doc = "0: Fixed clock is used to sample data"]
247    Fixed = 0,
248    #[doc = "1: Tuned clock is used to sample data"]
249    Tuned = 1,
250}
251impl From<Slckselselect> for bool {
252    #[inline(always)]
253    fn from(variant: Slckselselect) -> Self {
254        variant as u8 != 0
255    }
256}
257#[doc = "Field `SLCKSEL` reader - Sampling Clock Select"]
258pub type SlckselR = crate::BitReader<Slckselselect>;
259impl SlckselR {
260    #[doc = "Get enumerated values variant"]
261    #[inline(always)]
262    pub const fn variant(&self) -> Slckselselect {
263        match self.bits {
264            false => Slckselselect::Fixed,
265            true => Slckselselect::Tuned,
266        }
267    }
268    #[doc = "Fixed clock is used to sample data"]
269    #[inline(always)]
270    pub fn is_fixed(&self) -> bool {
271        *self == Slckselselect::Fixed
272    }
273    #[doc = "Tuned clock is used to sample data"]
274    #[inline(always)]
275    pub fn is_tuned(&self) -> bool {
276        *self == Slckselselect::Tuned
277    }
278}
279#[doc = "Field `SLCKSEL` writer - Sampling Clock Select"]
280pub type SlckselW<'a, REG> = crate::BitWriter<'a, REG, Slckselselect>;
281impl<'a, REG> SlckselW<'a, REG>
282where
283    REG: crate::Writable + crate::RegisterSpec,
284{
285    #[doc = "Fixed clock is used to sample data"]
286    #[inline(always)]
287    pub fn fixed(self) -> &'a mut crate::W<REG> {
288        self.variant(Slckselselect::Fixed)
289    }
290    #[doc = "Tuned clock is used to sample data"]
291    #[inline(always)]
292    pub fn tuned(self) -> &'a mut crate::W<REG> {
293        self.variant(Slckselselect::Tuned)
294    }
295}
296#[doc = "Preset Value Enable\n\nValue on reset: 0"]
297#[derive(Clone, Copy, Debug, PartialEq, Eq)]
298pub enum Pvalenselect {
299    #[doc = "0: SDCLK and Driver Strength are controlled by Host Controller"]
300    Host = 0,
301    #[doc = "1: Automatic Selection by Preset Value is Enabled"]
302    Auto = 1,
303}
304impl From<Pvalenselect> for bool {
305    #[inline(always)]
306    fn from(variant: Pvalenselect) -> Self {
307        variant as u8 != 0
308    }
309}
310#[doc = "Field `PVALEN` reader - Preset Value Enable"]
311pub type PvalenR = crate::BitReader<Pvalenselect>;
312impl PvalenR {
313    #[doc = "Get enumerated values variant"]
314    #[inline(always)]
315    pub const fn variant(&self) -> Pvalenselect {
316        match self.bits {
317            false => Pvalenselect::Host,
318            true => Pvalenselect::Auto,
319        }
320    }
321    #[doc = "SDCLK and Driver Strength are controlled by Host Controller"]
322    #[inline(always)]
323    pub fn is_host(&self) -> bool {
324        *self == Pvalenselect::Host
325    }
326    #[doc = "Automatic Selection by Preset Value is Enabled"]
327    #[inline(always)]
328    pub fn is_auto(&self) -> bool {
329        *self == Pvalenselect::Auto
330    }
331}
332#[doc = "Field `PVALEN` writer - Preset Value Enable"]
333pub type PvalenW<'a, REG> = crate::BitWriter<'a, REG, Pvalenselect>;
334impl<'a, REG> PvalenW<'a, REG>
335where
336    REG: crate::Writable + crate::RegisterSpec,
337{
338    #[doc = "SDCLK and Driver Strength are controlled by Host Controller"]
339    #[inline(always)]
340    pub fn host(self) -> &'a mut crate::W<REG> {
341        self.variant(Pvalenselect::Host)
342    }
343    #[doc = "Automatic Selection by Preset Value is Enabled"]
344    #[inline(always)]
345    pub fn auto(self) -> &'a mut crate::W<REG> {
346        self.variant(Pvalenselect::Auto)
347    }
348}
349impl R {
350    #[doc = "Bits 0:3 - HS200 Mode Enable"]
351    #[inline(always)]
352    pub fn hs200en(&self) -> Hs200enR {
353        Hs200enR::new((self.bits & 0x0f) as u8)
354    }
355    #[doc = "Bits 4:5 - Driver Strength Select"]
356    #[inline(always)]
357    pub fn drvsel(&self) -> DrvselR {
358        DrvselR::new(((self.bits >> 4) & 3) as u8)
359    }
360    #[doc = "Bit 6 - Execute Tuning"]
361    #[inline(always)]
362    pub fn extun(&self) -> ExtunR {
363        ExtunR::new(((self.bits >> 6) & 1) != 0)
364    }
365    #[doc = "Bit 7 - Sampling Clock Select"]
366    #[inline(always)]
367    pub fn slcksel(&self) -> SlckselR {
368        SlckselR::new(((self.bits >> 7) & 1) != 0)
369    }
370    #[doc = "Bit 15 - Preset Value Enable"]
371    #[inline(always)]
372    pub fn pvalen(&self) -> PvalenR {
373        PvalenR::new(((self.bits >> 15) & 1) != 0)
374    }
375}
376impl W {
377    #[doc = "Bits 0:3 - HS200 Mode Enable"]
378    #[inline(always)]
379    #[must_use]
380    pub fn hs200en(&mut self) -> Hs200enW<Hc2rEmmcModeSpec> {
381        Hs200enW::new(self, 0)
382    }
383    #[doc = "Bits 4:5 - Driver Strength Select"]
384    #[inline(always)]
385    #[must_use]
386    pub fn drvsel(&mut self) -> DrvselW<Hc2rEmmcModeSpec> {
387        DrvselW::new(self, 4)
388    }
389    #[doc = "Bit 6 - Execute Tuning"]
390    #[inline(always)]
391    #[must_use]
392    pub fn extun(&mut self) -> ExtunW<Hc2rEmmcModeSpec> {
393        ExtunW::new(self, 6)
394    }
395    #[doc = "Bit 7 - Sampling Clock Select"]
396    #[inline(always)]
397    #[must_use]
398    pub fn slcksel(&mut self) -> SlckselW<Hc2rEmmcModeSpec> {
399        SlckselW::new(self, 7)
400    }
401    #[doc = "Bit 15 - Preset Value Enable"]
402    #[inline(always)]
403    #[must_use]
404    pub fn pvalen(&mut self) -> PvalenW<Hc2rEmmcModeSpec> {
405        PvalenW::new(self, 15)
406    }
407}
408#[doc = "Host Control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`hc2r_emmc_mode::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hc2r_emmc_mode::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
409pub struct Hc2rEmmcModeSpec;
410impl crate::RegisterSpec for Hc2rEmmcModeSpec {
411    type Ux = u16;
412}
413#[doc = "`read()` method returns [`hc2r_emmc_mode::R`](R) reader structure"]
414impl crate::Readable for Hc2rEmmcModeSpec {}
415#[doc = "`write(|w| ..)` method takes [`hc2r_emmc_mode::W`](W) writer structure"]
416impl crate::Writable for Hc2rEmmcModeSpec {
417    type Safety = crate::Unsafe;
418    const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
419    const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
420}
421#[doc = "`reset()` method sets HC2R_EMMC_MODE to value 0"]
422impl crate::Resettable for Hc2rEmmcModeSpec {
423    const RESET_VALUE: u16 = 0;
424}
atsamd51g/sdhc0/hc2r_emmc_mode.rs

atsamd51g/sdhc0/
hc2r_emmc_mode.rs
