atsamd51g/eic/
asynch.rs

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1#[doc = "Register `ASYNCH` reader"]
2pub type R = crate::R<AsynchSpec>;
3#[doc = "Register `ASYNCH` writer"]
4pub type W = crate::W<AsynchSpec>;
5#[doc = "Asynchronous Edge Detection Mode\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7#[repr(u16)]
8pub enum Asynchselect {
9    #[doc = "0: Edge detection is clock synchronously operated"]
10    Sync = 0,
11    #[doc = "1: Edge detection is clock asynchronously operated"]
12    Async = 1,
13}
14impl From<Asynchselect> for u16 {
15    #[inline(always)]
16    fn from(variant: Asynchselect) -> Self {
17        variant as _
18    }
19}
20impl crate::FieldSpec for Asynchselect {
21    type Ux = u16;
22}
23impl crate::IsEnum for Asynchselect {}
24#[doc = "Field `ASYNCH` reader - Asynchronous Edge Detection Mode"]
25pub type AsynchR = crate::FieldReader<Asynchselect>;
26impl AsynchR {
27    #[doc = "Get enumerated values variant"]
28    #[inline(always)]
29    pub const fn variant(&self) -> Option<Asynchselect> {
30        match self.bits {
31            0 => Some(Asynchselect::Sync),
32            1 => Some(Asynchselect::Async),
33            _ => None,
34        }
35    }
36    #[doc = "Edge detection is clock synchronously operated"]
37    #[inline(always)]
38    pub fn is_sync(&self) -> bool {
39        *self == Asynchselect::Sync
40    }
41    #[doc = "Edge detection is clock asynchronously operated"]
42    #[inline(always)]
43    pub fn is_async(&self) -> bool {
44        *self == Asynchselect::Async
45    }
46}
47#[doc = "Field `ASYNCH` writer - Asynchronous Edge Detection Mode"]
48pub type AsynchW<'a, REG> = crate::FieldWriter<'a, REG, 16, Asynchselect>;
49impl<'a, REG> AsynchW<'a, REG>
50where
51    REG: crate::Writable + crate::RegisterSpec,
52    REG::Ux: From<u16>,
53{
54    #[doc = "Edge detection is clock synchronously operated"]
55    #[inline(always)]
56    pub fn sync(self) -> &'a mut crate::W<REG> {
57        self.variant(Asynchselect::Sync)
58    }
59    #[doc = "Edge detection is clock asynchronously operated"]
60    #[inline(always)]
61    pub fn async_(self) -> &'a mut crate::W<REG> {
62        self.variant(Asynchselect::Async)
63    }
64}
65impl R {
66    #[doc = "Bits 0:15 - Asynchronous Edge Detection Mode"]
67    #[inline(always)]
68    pub fn asynch(&self) -> AsynchR {
69        AsynchR::new((self.bits & 0xffff) as u16)
70    }
71}
72impl W {
73    #[doc = "Bits 0:15 - Asynchronous Edge Detection Mode"]
74    #[inline(always)]
75    #[must_use]
76    pub fn asynch(&mut self) -> AsynchW<AsynchSpec> {
77        AsynchW::new(self, 0)
78    }
79}
80#[doc = "External Interrupt Asynchronous Mode\n\nYou can [`read`](crate::Reg::read) this register and get [`asynch::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`asynch::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
81pub struct AsynchSpec;
82impl crate::RegisterSpec for AsynchSpec {
83    type Ux = u32;
84}
85#[doc = "`read()` method returns [`asynch::R`](R) reader structure"]
86impl crate::Readable for AsynchSpec {}
87#[doc = "`write(|w| ..)` method takes [`asynch::W`](W) writer structure"]
88impl crate::Writable for AsynchSpec {
89    type Safety = crate::Unsafe;
90    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
91    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
92}
93#[doc = "`reset()` method sets ASYNCH to value 0"]
94impl crate::Resettable for AsynchSpec {
95    const RESET_VALUE: u32 = 0;
96}
atsamd51g/eic/asynch.rs

atsamd51g/eic/
asynch.rs
