atsamd51g/mclk/
apbcmask.rs

1#[doc = "Register `APBCMASK` reader"]
2pub type R = crate::R<ApbcmaskSpec>;
3#[doc = "Register `APBCMASK` writer"]
4pub type W = crate::W<ApbcmaskSpec>;
5#[doc = "Field `TCC2_` reader - TCC2 APB Clock Enable"]
6pub type Tcc2_R = crate::BitReader;
7#[doc = "Field `TCC2_` writer - TCC2 APB Clock Enable"]
8pub type Tcc2_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `PDEC_` reader - PDEC APB Clock Enable"]
10pub type Pdec_R = crate::BitReader;
11#[doc = "Field `PDEC_` writer - PDEC APB Clock Enable"]
12pub type Pdec_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `AC_` reader - AC APB Clock Enable"]
14pub type Ac_R = crate::BitReader;
15#[doc = "Field `AC_` writer - AC APB Clock Enable"]
16pub type Ac_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `AES_` reader - AES APB Clock Enable"]
18pub type Aes_R = crate::BitReader;
19#[doc = "Field `AES_` writer - AES APB Clock Enable"]
20pub type Aes_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `TRNG_` reader - TRNG APB Clock Enable"]
22pub type Trng_R = crate::BitReader;
23#[doc = "Field `TRNG_` writer - TRNG APB Clock Enable"]
24pub type Trng_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `ICM_` reader - ICM APB Clock Enable"]
26pub type Icm_R = crate::BitReader;
27#[doc = "Field `ICM_` writer - ICM APB Clock Enable"]
28pub type Icm_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `QSPI_` reader - QSPI APB Clock Enable"]
30pub type Qspi_R = crate::BitReader;
31#[doc = "Field `QSPI_` writer - QSPI APB Clock Enable"]
32pub type Qspi_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `CCL_` reader - CCL APB Clock Enable"]
34pub type Ccl_R = crate::BitReader;
35#[doc = "Field `CCL_` writer - CCL APB Clock Enable"]
36pub type Ccl_W<'a, REG> = crate::BitWriter<'a, REG>;
37impl R {
38    #[doc = "Bit 3 - TCC2 APB Clock Enable"]
39    #[inline(always)]
40    pub fn tcc2_(&self) -> Tcc2_R {
41        Tcc2_R::new(((self.bits >> 3) & 1) != 0)
42    }
43    #[doc = "Bit 7 - PDEC APB Clock Enable"]
44    #[inline(always)]
45    pub fn pdec_(&self) -> Pdec_R {
46        Pdec_R::new(((self.bits >> 7) & 1) != 0)
47    }
48    #[doc = "Bit 8 - AC APB Clock Enable"]
49    #[inline(always)]
50    pub fn ac_(&self) -> Ac_R {
51        Ac_R::new(((self.bits >> 8) & 1) != 0)
52    }
53    #[doc = "Bit 9 - AES APB Clock Enable"]
54    #[inline(always)]
55    pub fn aes_(&self) -> Aes_R {
56        Aes_R::new(((self.bits >> 9) & 1) != 0)
57    }
58    #[doc = "Bit 10 - TRNG APB Clock Enable"]
59    #[inline(always)]
60    pub fn trng_(&self) -> Trng_R {
61        Trng_R::new(((self.bits >> 10) & 1) != 0)
62    }
63    #[doc = "Bit 11 - ICM APB Clock Enable"]
64    #[inline(always)]
65    pub fn icm_(&self) -> Icm_R {
66        Icm_R::new(((self.bits >> 11) & 1) != 0)
67    }
68    #[doc = "Bit 13 - QSPI APB Clock Enable"]
69    #[inline(always)]
70    pub fn qspi_(&self) -> Qspi_R {
71        Qspi_R::new(((self.bits >> 13) & 1) != 0)
72    }
73    #[doc = "Bit 14 - CCL APB Clock Enable"]
74    #[inline(always)]
75    pub fn ccl_(&self) -> Ccl_R {
76        Ccl_R::new(((self.bits >> 14) & 1) != 0)
77    }
78}
79impl W {
80    #[doc = "Bit 3 - TCC2 APB Clock Enable"]
81    #[inline(always)]
82    #[must_use]
83    pub fn tcc2_(&mut self) -> Tcc2_W<ApbcmaskSpec> {
84        Tcc2_W::new(self, 3)
85    }
86    #[doc = "Bit 7 - PDEC APB Clock Enable"]
87    #[inline(always)]
88    #[must_use]
89    pub fn pdec_(&mut self) -> Pdec_W<ApbcmaskSpec> {
90        Pdec_W::new(self, 7)
91    }
92    #[doc = "Bit 8 - AC APB Clock Enable"]
93    #[inline(always)]
94    #[must_use]
95    pub fn ac_(&mut self) -> Ac_W<ApbcmaskSpec> {
96        Ac_W::new(self, 8)
97    }
98    #[doc = "Bit 9 - AES APB Clock Enable"]
99    #[inline(always)]
100    #[must_use]
101    pub fn aes_(&mut self) -> Aes_W<ApbcmaskSpec> {
102        Aes_W::new(self, 9)
103    }
104    #[doc = "Bit 10 - TRNG APB Clock Enable"]
105    #[inline(always)]
106    #[must_use]
107    pub fn trng_(&mut self) -> Trng_W<ApbcmaskSpec> {
108        Trng_W::new(self, 10)
109    }
110    #[doc = "Bit 11 - ICM APB Clock Enable"]
111    #[inline(always)]
112    #[must_use]
113    pub fn icm_(&mut self) -> Icm_W<ApbcmaskSpec> {
114        Icm_W::new(self, 11)
115    }
116    #[doc = "Bit 13 - QSPI APB Clock Enable"]
117    #[inline(always)]
118    #[must_use]
119    pub fn qspi_(&mut self) -> Qspi_W<ApbcmaskSpec> {
120        Qspi_W::new(self, 13)
121    }
122    #[doc = "Bit 14 - CCL APB Clock Enable"]
123    #[inline(always)]
124    #[must_use]
125    pub fn ccl_(&mut self) -> Ccl_W<ApbcmaskSpec> {
126        Ccl_W::new(self, 14)
127    }
128}
129#[doc = "APBC Mask\n\nYou can [`read`](crate::Reg::read) this register and get [`apbcmask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apbcmask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
130pub struct ApbcmaskSpec;
131impl crate::RegisterSpec for ApbcmaskSpec {
132    type Ux = u32;
133}
134#[doc = "`read()` method returns [`apbcmask::R`](R) reader structure"]
135impl crate::Readable for ApbcmaskSpec {}
136#[doc = "`write(|w| ..)` method takes [`apbcmask::W`](W) writer structure"]
137impl crate::Writable for ApbcmaskSpec {
138    type Safety = crate::Unsafe;
139    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
140    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
141}
142#[doc = "`reset()` method sets APBCMASK to value 0x2000"]
143impl crate::Resettable for ApbcmaskSpec {
144    const RESET_VALUE: u32 = 0x2000;
145}
atsamd51g/mclk/apbcmask.rs

atsamd51g/mclk/
apbcmask.rs
