atsamd51g/sercom0/usart_int/
ctrlc.rs

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1#[doc = "Register `CTRLC` reader"]
2pub type R = crate::R<CtrlcSpec>;
3#[doc = "Register `CTRLC` writer"]
4pub type W = crate::W<CtrlcSpec>;
5#[doc = "Field `GTIME` reader - Guard Time"]
6pub type GtimeR = crate::FieldReader;
7#[doc = "Field `GTIME` writer - Guard Time"]
8pub type GtimeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
9#[doc = "LIN Master Break Length\n\nValue on reset: 0"]
10#[derive(Clone, Copy, Debug, PartialEq, Eq)]
11#[repr(u8)]
12pub enum Brklenselect {
13    #[doc = "0: Break field transmission is 13 bit times"]
14    _13Bit = 0,
15    #[doc = "1: Break field transmission is 17 bit times"]
16    _17Bit = 1,
17    #[doc = "2: Break field transmission is 21 bit times"]
18    _21Bit = 2,
19    #[doc = "3: Break field transmission is 26 bit times"]
20    _26Bit = 3,
21}
22impl From<Brklenselect> for u8 {
23    #[inline(always)]
24    fn from(variant: Brklenselect) -> Self {
25        variant as _
26    }
27}
28impl crate::FieldSpec for Brklenselect {
29    type Ux = u8;
30}
31impl crate::IsEnum for Brklenselect {}
32#[doc = "Field `BRKLEN` reader - LIN Master Break Length"]
33pub type BrklenR = crate::FieldReader<Brklenselect>;
34impl BrklenR {
35    #[doc = "Get enumerated values variant"]
36    #[inline(always)]
37    pub const fn variant(&self) -> Brklenselect {
38        match self.bits {
39            0 => Brklenselect::_13Bit,
40            1 => Brklenselect::_17Bit,
41            2 => Brklenselect::_21Bit,
42            3 => Brklenselect::_26Bit,
43            _ => unreachable!(),
44        }
45    }
46    #[doc = "Break field transmission is 13 bit times"]
47    #[inline(always)]
48    pub fn is_13_bit(&self) -> bool {
49        *self == Brklenselect::_13Bit
50    }
51    #[doc = "Break field transmission is 17 bit times"]
52    #[inline(always)]
53    pub fn is_17_bit(&self) -> bool {
54        *self == Brklenselect::_17Bit
55    }
56    #[doc = "Break field transmission is 21 bit times"]
57    #[inline(always)]
58    pub fn is_21_bit(&self) -> bool {
59        *self == Brklenselect::_21Bit
60    }
61    #[doc = "Break field transmission is 26 bit times"]
62    #[inline(always)]
63    pub fn is_26_bit(&self) -> bool {
64        *self == Brklenselect::_26Bit
65    }
66}
67#[doc = "Field `BRKLEN` writer - LIN Master Break Length"]
68pub type BrklenW<'a, REG> = crate::FieldWriter<'a, REG, 2, Brklenselect, crate::Safe>;
69impl<'a, REG> BrklenW<'a, REG>
70where
71    REG: crate::Writable + crate::RegisterSpec,
72    REG::Ux: From<u8>,
73{
74    #[doc = "Break field transmission is 13 bit times"]
75    #[inline(always)]
76    pub fn _13_bit(self) -> &'a mut crate::W<REG> {
77        self.variant(Brklenselect::_13Bit)
78    }
79    #[doc = "Break field transmission is 17 bit times"]
80    #[inline(always)]
81    pub fn _17_bit(self) -> &'a mut crate::W<REG> {
82        self.variant(Brklenselect::_17Bit)
83    }
84    #[doc = "Break field transmission is 21 bit times"]
85    #[inline(always)]
86    pub fn _21_bit(self) -> &'a mut crate::W<REG> {
87        self.variant(Brklenselect::_21Bit)
88    }
89    #[doc = "Break field transmission is 26 bit times"]
90    #[inline(always)]
91    pub fn _26_bit(self) -> &'a mut crate::W<REG> {
92        self.variant(Brklenselect::_26Bit)
93    }
94}
95#[doc = "LIN Master Header Delay\n\nValue on reset: 0"]
96#[derive(Clone, Copy, Debug, PartialEq, Eq)]
97#[repr(u8)]
98pub enum Hdrdlyselect {
99    #[doc = "0: Delay between break and sync transmission is 1 bit time; Delay between sync and ID transmission is 1 bit time"]
100    Delay0 = 0,
101    #[doc = "1: Delay between break and sync transmission is 4 bit time; Delay between sync and ID transmission is 4 bit time"]
102    Delay1 = 1,
103    #[doc = "2: Delay between break and sync transmission is 8 bit time; Delay between sync and ID transmission is 4 bit time"]
104    Delay2 = 2,
105    #[doc = "3: Delay between break and sync transmission is 14 bit time; Delay between sync and ID transmission is 4 bit time"]
106    Delay3 = 3,
107}
108impl From<Hdrdlyselect> for u8 {
109    #[inline(always)]
110    fn from(variant: Hdrdlyselect) -> Self {
111        variant as _
112    }
113}
114impl crate::FieldSpec for Hdrdlyselect {
115    type Ux = u8;
116}
117impl crate::IsEnum for Hdrdlyselect {}
118#[doc = "Field `HDRDLY` reader - LIN Master Header Delay"]
119pub type HdrdlyR = crate::FieldReader<Hdrdlyselect>;
120impl HdrdlyR {
121    #[doc = "Get enumerated values variant"]
122    #[inline(always)]
123    pub const fn variant(&self) -> Hdrdlyselect {
124        match self.bits {
125            0 => Hdrdlyselect::Delay0,
126            1 => Hdrdlyselect::Delay1,
127            2 => Hdrdlyselect::Delay2,
128            3 => Hdrdlyselect::Delay3,
129            _ => unreachable!(),
130        }
131    }
132    #[doc = "Delay between break and sync transmission is 1 bit time; Delay between sync and ID transmission is 1 bit time"]
133    #[inline(always)]
134    pub fn is_delay0(&self) -> bool {
135        *self == Hdrdlyselect::Delay0
136    }
137    #[doc = "Delay between break and sync transmission is 4 bit time; Delay between sync and ID transmission is 4 bit time"]
138    #[inline(always)]
139    pub fn is_delay1(&self) -> bool {
140        *self == Hdrdlyselect::Delay1
141    }
142    #[doc = "Delay between break and sync transmission is 8 bit time; Delay between sync and ID transmission is 4 bit time"]
143    #[inline(always)]
144    pub fn is_delay2(&self) -> bool {
145        *self == Hdrdlyselect::Delay2
146    }
147    #[doc = "Delay between break and sync transmission is 14 bit time; Delay between sync and ID transmission is 4 bit time"]
148    #[inline(always)]
149    pub fn is_delay3(&self) -> bool {
150        *self == Hdrdlyselect::Delay3
151    }
152}
153#[doc = "Field `HDRDLY` writer - LIN Master Header Delay"]
154pub type HdrdlyW<'a, REG> = crate::FieldWriter<'a, REG, 2, Hdrdlyselect, crate::Safe>;
155impl<'a, REG> HdrdlyW<'a, REG>
156where
157    REG: crate::Writable + crate::RegisterSpec,
158    REG::Ux: From<u8>,
159{
160    #[doc = "Delay between break and sync transmission is 1 bit time; Delay between sync and ID transmission is 1 bit time"]
161    #[inline(always)]
162    pub fn delay0(self) -> &'a mut crate::W<REG> {
163        self.variant(Hdrdlyselect::Delay0)
164    }
165    #[doc = "Delay between break and sync transmission is 4 bit time; Delay between sync and ID transmission is 4 bit time"]
166    #[inline(always)]
167    pub fn delay1(self) -> &'a mut crate::W<REG> {
168        self.variant(Hdrdlyselect::Delay1)
169    }
170    #[doc = "Delay between break and sync transmission is 8 bit time; Delay between sync and ID transmission is 4 bit time"]
171    #[inline(always)]
172    pub fn delay2(self) -> &'a mut crate::W<REG> {
173        self.variant(Hdrdlyselect::Delay2)
174    }
175    #[doc = "Delay between break and sync transmission is 14 bit time; Delay between sync and ID transmission is 4 bit time"]
176    #[inline(always)]
177    pub fn delay3(self) -> &'a mut crate::W<REG> {
178        self.variant(Hdrdlyselect::Delay3)
179    }
180}
181#[doc = "Field `INACK` reader - Inhibit Not Acknowledge"]
182pub type InackR = crate::BitReader;
183#[doc = "Field `INACK` writer - Inhibit Not Acknowledge"]
184pub type InackW<'a, REG> = crate::BitWriter<'a, REG>;
185#[doc = "Field `DSNACK` reader - Disable Successive NACK"]
186pub type DsnackR = crate::BitReader;
187#[doc = "Field `DSNACK` writer - Disable Successive NACK"]
188pub type DsnackW<'a, REG> = crate::BitWriter<'a, REG>;
189#[doc = "Field `MAXITER` reader - Maximum Iterations"]
190pub type MaxiterR = crate::FieldReader;
191#[doc = "Field `MAXITER` writer - Maximum Iterations"]
192pub type MaxiterW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
193#[doc = "Data 32 Bit\n\nValue on reset: 0"]
194#[derive(Clone, Copy, Debug, PartialEq, Eq)]
195#[repr(u8)]
196pub enum Data32bselect {
197    #[doc = "0: Data reads and writes according CTRLB.CHSIZE"]
198    DataReadWriteChsize = 0,
199    #[doc = "1: Data reads according CTRLB.CHSIZE and writes according 32-bit extension"]
200    DataReadChsizeWrite32bit = 1,
201    #[doc = "2: Data reads according 32-bit extension and writes according CTRLB.CHSIZE"]
202    DataRead32bitWriteChsize = 2,
203    #[doc = "3: Data reads and writes according 32-bit extension"]
204    DataReadWrite32bit = 3,
205}
206impl From<Data32bselect> for u8 {
207    #[inline(always)]
208    fn from(variant: Data32bselect) -> Self {
209        variant as _
210    }
211}
212impl crate::FieldSpec for Data32bselect {
213    type Ux = u8;
214}
215impl crate::IsEnum for Data32bselect {}
216#[doc = "Field `DATA32B` reader - Data 32 Bit"]
217pub type Data32bR = crate::FieldReader<Data32bselect>;
218impl Data32bR {
219    #[doc = "Get enumerated values variant"]
220    #[inline(always)]
221    pub const fn variant(&self) -> Data32bselect {
222        match self.bits {
223            0 => Data32bselect::DataReadWriteChsize,
224            1 => Data32bselect::DataReadChsizeWrite32bit,
225            2 => Data32bselect::DataRead32bitWriteChsize,
226            3 => Data32bselect::DataReadWrite32bit,
227            _ => unreachable!(),
228        }
229    }
230    #[doc = "Data reads and writes according CTRLB.CHSIZE"]
231    #[inline(always)]
232    pub fn is_data_read_write_chsize(&self) -> bool {
233        *self == Data32bselect::DataReadWriteChsize
234    }
235    #[doc = "Data reads according CTRLB.CHSIZE and writes according 32-bit extension"]
236    #[inline(always)]
237    pub fn is_data_read_chsize_write_32bit(&self) -> bool {
238        *self == Data32bselect::DataReadChsizeWrite32bit
239    }
240    #[doc = "Data reads according 32-bit extension and writes according CTRLB.CHSIZE"]
241    #[inline(always)]
242    pub fn is_data_read_32bit_write_chsize(&self) -> bool {
243        *self == Data32bselect::DataRead32bitWriteChsize
244    }
245    #[doc = "Data reads and writes according 32-bit extension"]
246    #[inline(always)]
247    pub fn is_data_read_write_32bit(&self) -> bool {
248        *self == Data32bselect::DataReadWrite32bit
249    }
250}
251#[doc = "Field `DATA32B` writer - Data 32 Bit"]
252pub type Data32bW<'a, REG> = crate::FieldWriter<'a, REG, 2, Data32bselect, crate::Safe>;
253impl<'a, REG> Data32bW<'a, REG>
254where
255    REG: crate::Writable + crate::RegisterSpec,
256    REG::Ux: From<u8>,
257{
258    #[doc = "Data reads and writes according CTRLB.CHSIZE"]
259    #[inline(always)]
260    pub fn data_read_write_chsize(self) -> &'a mut crate::W<REG> {
261        self.variant(Data32bselect::DataReadWriteChsize)
262    }
263    #[doc = "Data reads according CTRLB.CHSIZE and writes according 32-bit extension"]
264    #[inline(always)]
265    pub fn data_read_chsize_write_32bit(self) -> &'a mut crate::W<REG> {
266        self.variant(Data32bselect::DataReadChsizeWrite32bit)
267    }
268    #[doc = "Data reads according 32-bit extension and writes according CTRLB.CHSIZE"]
269    #[inline(always)]
270    pub fn data_read_32bit_write_chsize(self) -> &'a mut crate::W<REG> {
271        self.variant(Data32bselect::DataRead32bitWriteChsize)
272    }
273    #[doc = "Data reads and writes according 32-bit extension"]
274    #[inline(always)]
275    pub fn data_read_write_32bit(self) -> &'a mut crate::W<REG> {
276        self.variant(Data32bselect::DataReadWrite32bit)
277    }
278}
279impl R {
280    #[doc = "Bits 0:2 - Guard Time"]
281    #[inline(always)]
282    pub fn gtime(&self) -> GtimeR {
283        GtimeR::new((self.bits & 7) as u8)
284    }
285    #[doc = "Bits 8:9 - LIN Master Break Length"]
286    #[inline(always)]
287    pub fn brklen(&self) -> BrklenR {
288        BrklenR::new(((self.bits >> 8) & 3) as u8)
289    }
290    #[doc = "Bits 10:11 - LIN Master Header Delay"]
291    #[inline(always)]
292    pub fn hdrdly(&self) -> HdrdlyR {
293        HdrdlyR::new(((self.bits >> 10) & 3) as u8)
294    }
295    #[doc = "Bit 16 - Inhibit Not Acknowledge"]
296    #[inline(always)]
297    pub fn inack(&self) -> InackR {
298        InackR::new(((self.bits >> 16) & 1) != 0)
299    }
300    #[doc = "Bit 17 - Disable Successive NACK"]
301    #[inline(always)]
302    pub fn dsnack(&self) -> DsnackR {
303        DsnackR::new(((self.bits >> 17) & 1) != 0)
304    }
305    #[doc = "Bits 20:22 - Maximum Iterations"]
306    #[inline(always)]
307    pub fn maxiter(&self) -> MaxiterR {
308        MaxiterR::new(((self.bits >> 20) & 7) as u8)
309    }
310    #[doc = "Bits 24:25 - Data 32 Bit"]
311    #[inline(always)]
312    pub fn data32b(&self) -> Data32bR {
313        Data32bR::new(((self.bits >> 24) & 3) as u8)
314    }
315}
316impl W {
317    #[doc = "Bits 0:2 - Guard Time"]
318    #[inline(always)]
319    #[must_use]
320    pub fn gtime(&mut self) -> GtimeW<CtrlcSpec> {
321        GtimeW::new(self, 0)
322    }
323    #[doc = "Bits 8:9 - LIN Master Break Length"]
324    #[inline(always)]
325    #[must_use]
326    pub fn brklen(&mut self) -> BrklenW<CtrlcSpec> {
327        BrklenW::new(self, 8)
328    }
329    #[doc = "Bits 10:11 - LIN Master Header Delay"]
330    #[inline(always)]
331    #[must_use]
332    pub fn hdrdly(&mut self) -> HdrdlyW<CtrlcSpec> {
333        HdrdlyW::new(self, 10)
334    }
335    #[doc = "Bit 16 - Inhibit Not Acknowledge"]
336    #[inline(always)]
337    #[must_use]
338    pub fn inack(&mut self) -> InackW<CtrlcSpec> {
339        InackW::new(self, 16)
340    }
341    #[doc = "Bit 17 - Disable Successive NACK"]
342    #[inline(always)]
343    #[must_use]
344    pub fn dsnack(&mut self) -> DsnackW<CtrlcSpec> {
345        DsnackW::new(self, 17)
346    }
347    #[doc = "Bits 20:22 - Maximum Iterations"]
348    #[inline(always)]
349    #[must_use]
350    pub fn maxiter(&mut self) -> MaxiterW<CtrlcSpec> {
351        MaxiterW::new(self, 20)
352    }
353    #[doc = "Bits 24:25 - Data 32 Bit"]
354    #[inline(always)]
355    #[must_use]
356    pub fn data32b(&mut self) -> Data32bW<CtrlcSpec> {
357        Data32bW::new(self, 24)
358    }
359}
360#[doc = "USART_INT Control C\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrlc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrlc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
361pub struct CtrlcSpec;
362impl crate::RegisterSpec for CtrlcSpec {
363    type Ux = u32;
364}
365#[doc = "`read()` method returns [`ctrlc::R`](R) reader structure"]
366impl crate::Readable for CtrlcSpec {}
367#[doc = "`write(|w| ..)` method takes [`ctrlc::W`](W) writer structure"]
368impl crate::Writable for CtrlcSpec {
369    type Safety = crate::Unsafe;
370    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
371    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
372}
373#[doc = "`reset()` method sets CTRLC to value 0"]
374impl crate::Resettable for CtrlcSpec {
375    const RESET_VALUE: u32 = 0;
376}
atsamd51g/sercom0/usart_int/ctrlc.rs

atsamd51g/sercom0/usart_int/
ctrlc.rs
