atsamd51g/system_control/
shcsr.rs

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1#[doc = "Register `SHCSR` reader"]
2pub type R = crate::R<ShcsrSpec>;
3#[doc = "Register `SHCSR` writer"]
4pub type W = crate::W<ShcsrSpec>;
5#[doc = "Field `MEMFAULTACT` reader - MemManage exception active bit"]
6pub type MemfaultactR = crate::BitReader;
7#[doc = "Field `MEMFAULTACT` writer - MemManage exception active bit"]
8pub type MemfaultactW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `BUSFAULTACT` reader - BusFault exception active bit"]
10pub type BusfaultactR = crate::BitReader;
11#[doc = "Field `BUSFAULTACT` writer - BusFault exception active bit"]
12pub type BusfaultactW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `USGFAULTACT` reader - UsageFault exception active bit"]
14pub type UsgfaultactR = crate::BitReader;
15#[doc = "Field `USGFAULTACT` writer - UsageFault exception active bit"]
16pub type UsgfaultactW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `SVCALLACT` reader - SVCall active bit"]
18pub type SvcallactR = crate::BitReader;
19#[doc = "Field `SVCALLACT` writer - SVCall active bit"]
20pub type SvcallactW<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `MONITORACT` reader - DebugMonitor exception active bit"]
22pub type MonitoractR = crate::BitReader;
23#[doc = "Field `MONITORACT` writer - DebugMonitor exception active bit"]
24pub type MonitoractW<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `PENDSVACT` reader - PendSV exception active bit"]
26pub type PendsvactR = crate::BitReader;
27#[doc = "Field `PENDSVACT` writer - PendSV exception active bit"]
28pub type PendsvactW<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `SYSTICKACT` reader - SysTick exception active bit"]
30pub type SystickactR = crate::BitReader;
31#[doc = "Field `SYSTICKACT` writer - SysTick exception active bit"]
32pub type SystickactW<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `USGFAULTPENDED` reader - UsageFault exception pending bit"]
34pub type UsgfaultpendedR = crate::BitReader;
35#[doc = "Field `USGFAULTPENDED` writer - UsageFault exception pending bit"]
36pub type UsgfaultpendedW<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `MEMFAULTPENDED` reader - MemManage exception pending bit"]
38pub type MemfaultpendedR = crate::BitReader;
39#[doc = "Field `MEMFAULTPENDED` writer - MemManage exception pending bit"]
40pub type MemfaultpendedW<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `BUSFAULTPENDED` reader - BusFault exception pending bit"]
42pub type BusfaultpendedR = crate::BitReader;
43#[doc = "Field `BUSFAULTPENDED` writer - BusFault exception pending bit"]
44pub type BusfaultpendedW<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `SVCALLPENDED` reader - SVCall pending bit"]
46pub type SvcallpendedR = crate::BitReader;
47#[doc = "Field `SVCALLPENDED` writer - SVCall pending bit"]
48pub type SvcallpendedW<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `MEMFAULTENA` reader - MemManage enable bit"]
50pub type MemfaultenaR = crate::BitReader;
51#[doc = "Field `MEMFAULTENA` writer - MemManage enable bit"]
52pub type MemfaultenaW<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `BUSFAULTENA` reader - BusFault enable bit"]
54pub type BusfaultenaR = crate::BitReader;
55#[doc = "Field `BUSFAULTENA` writer - BusFault enable bit"]
56pub type BusfaultenaW<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `USGFAULTENA` reader - UsageFault enable bit"]
58pub type UsgfaultenaR = crate::BitReader;
59#[doc = "Field `USGFAULTENA` writer - UsageFault enable bit"]
60pub type UsgfaultenaW<'a, REG> = crate::BitWriter<'a, REG>;
61impl R {
62    #[doc = "Bit 0 - MemManage exception active bit"]
63    #[inline(always)]
64    pub fn memfaultact(&self) -> MemfaultactR {
65        MemfaultactR::new((self.bits & 1) != 0)
66    }
67    #[doc = "Bit 1 - BusFault exception active bit"]
68    #[inline(always)]
69    pub fn busfaultact(&self) -> BusfaultactR {
70        BusfaultactR::new(((self.bits >> 1) & 1) != 0)
71    }
72    #[doc = "Bit 3 - UsageFault exception active bit"]
73    #[inline(always)]
74    pub fn usgfaultact(&self) -> UsgfaultactR {
75        UsgfaultactR::new(((self.bits >> 3) & 1) != 0)
76    }
77    #[doc = "Bit 7 - SVCall active bit"]
78    #[inline(always)]
79    pub fn svcallact(&self) -> SvcallactR {
80        SvcallactR::new(((self.bits >> 7) & 1) != 0)
81    }
82    #[doc = "Bit 8 - DebugMonitor exception active bit"]
83    #[inline(always)]
84    pub fn monitoract(&self) -> MonitoractR {
85        MonitoractR::new(((self.bits >> 8) & 1) != 0)
86    }
87    #[doc = "Bit 10 - PendSV exception active bit"]
88    #[inline(always)]
89    pub fn pendsvact(&self) -> PendsvactR {
90        PendsvactR::new(((self.bits >> 10) & 1) != 0)
91    }
92    #[doc = "Bit 11 - SysTick exception active bit"]
93    #[inline(always)]
94    pub fn systickact(&self) -> SystickactR {
95        SystickactR::new(((self.bits >> 11) & 1) != 0)
96    }
97    #[doc = "Bit 12 - UsageFault exception pending bit"]
98    #[inline(always)]
99    pub fn usgfaultpended(&self) -> UsgfaultpendedR {
100        UsgfaultpendedR::new(((self.bits >> 12) & 1) != 0)
101    }
102    #[doc = "Bit 13 - MemManage exception pending bit"]
103    #[inline(always)]
104    pub fn memfaultpended(&self) -> MemfaultpendedR {
105        MemfaultpendedR::new(((self.bits >> 13) & 1) != 0)
106    }
107    #[doc = "Bit 14 - BusFault exception pending bit"]
108    #[inline(always)]
109    pub fn busfaultpended(&self) -> BusfaultpendedR {
110        BusfaultpendedR::new(((self.bits >> 14) & 1) != 0)
111    }
112    #[doc = "Bit 15 - SVCall pending bit"]
113    #[inline(always)]
114    pub fn svcallpended(&self) -> SvcallpendedR {
115        SvcallpendedR::new(((self.bits >> 15) & 1) != 0)
116    }
117    #[doc = "Bit 16 - MemManage enable bit"]
118    #[inline(always)]
119    pub fn memfaultena(&self) -> MemfaultenaR {
120        MemfaultenaR::new(((self.bits >> 16) & 1) != 0)
121    }
122    #[doc = "Bit 17 - BusFault enable bit"]
123    #[inline(always)]
124    pub fn busfaultena(&self) -> BusfaultenaR {
125        BusfaultenaR::new(((self.bits >> 17) & 1) != 0)
126    }
127    #[doc = "Bit 18 - UsageFault enable bit"]
128    #[inline(always)]
129    pub fn usgfaultena(&self) -> UsgfaultenaR {
130        UsgfaultenaR::new(((self.bits >> 18) & 1) != 0)
131    }
132}
133impl W {
134    #[doc = "Bit 0 - MemManage exception active bit"]
135    #[inline(always)]
136    #[must_use]
137    pub fn memfaultact(&mut self) -> MemfaultactW<ShcsrSpec> {
138        MemfaultactW::new(self, 0)
139    }
140    #[doc = "Bit 1 - BusFault exception active bit"]
141    #[inline(always)]
142    #[must_use]
143    pub fn busfaultact(&mut self) -> BusfaultactW<ShcsrSpec> {
144        BusfaultactW::new(self, 1)
145    }
146    #[doc = "Bit 3 - UsageFault exception active bit"]
147    #[inline(always)]
148    #[must_use]
149    pub fn usgfaultact(&mut self) -> UsgfaultactW<ShcsrSpec> {
150        UsgfaultactW::new(self, 3)
151    }
152    #[doc = "Bit 7 - SVCall active bit"]
153    #[inline(always)]
154    #[must_use]
155    pub fn svcallact(&mut self) -> SvcallactW<ShcsrSpec> {
156        SvcallactW::new(self, 7)
157    }
158    #[doc = "Bit 8 - DebugMonitor exception active bit"]
159    #[inline(always)]
160    #[must_use]
161    pub fn monitoract(&mut self) -> MonitoractW<ShcsrSpec> {
162        MonitoractW::new(self, 8)
163    }
164    #[doc = "Bit 10 - PendSV exception active bit"]
165    #[inline(always)]
166    #[must_use]
167    pub fn pendsvact(&mut self) -> PendsvactW<ShcsrSpec> {
168        PendsvactW::new(self, 10)
169    }
170    #[doc = "Bit 11 - SysTick exception active bit"]
171    #[inline(always)]
172    #[must_use]
173    pub fn systickact(&mut self) -> SystickactW<ShcsrSpec> {
174        SystickactW::new(self, 11)
175    }
176    #[doc = "Bit 12 - UsageFault exception pending bit"]
177    #[inline(always)]
178    #[must_use]
179    pub fn usgfaultpended(&mut self) -> UsgfaultpendedW<ShcsrSpec> {
180        UsgfaultpendedW::new(self, 12)
181    }
182    #[doc = "Bit 13 - MemManage exception pending bit"]
183    #[inline(always)]
184    #[must_use]
185    pub fn memfaultpended(&mut self) -> MemfaultpendedW<ShcsrSpec> {
186        MemfaultpendedW::new(self, 13)
187    }
188    #[doc = "Bit 14 - BusFault exception pending bit"]
189    #[inline(always)]
190    #[must_use]
191    pub fn busfaultpended(&mut self) -> BusfaultpendedW<ShcsrSpec> {
192        BusfaultpendedW::new(self, 14)
193    }
194    #[doc = "Bit 15 - SVCall pending bit"]
195    #[inline(always)]
196    #[must_use]
197    pub fn svcallpended(&mut self) -> SvcallpendedW<ShcsrSpec> {
198        SvcallpendedW::new(self, 15)
199    }
200    #[doc = "Bit 16 - MemManage enable bit"]
201    #[inline(always)]
202    #[must_use]
203    pub fn memfaultena(&mut self) -> MemfaultenaW<ShcsrSpec> {
204        MemfaultenaW::new(self, 16)
205    }
206    #[doc = "Bit 17 - BusFault enable bit"]
207    #[inline(always)]
208    #[must_use]
209    pub fn busfaultena(&mut self) -> BusfaultenaW<ShcsrSpec> {
210        BusfaultenaW::new(self, 17)
211    }
212    #[doc = "Bit 18 - UsageFault enable bit"]
213    #[inline(always)]
214    #[must_use]
215    pub fn usgfaultena(&mut self) -> UsgfaultenaW<ShcsrSpec> {
216        UsgfaultenaW::new(self, 18)
217    }
218}
219#[doc = "System Handler Control and State Register\n\nYou can [`read`](crate::Reg::read) this register and get [`shcsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shcsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
220pub struct ShcsrSpec;
221impl crate::RegisterSpec for ShcsrSpec {
222    type Ux = u32;
223}
224#[doc = "`read()` method returns [`shcsr::R`](R) reader structure"]
225impl crate::Readable for ShcsrSpec {}
226#[doc = "`write(|w| ..)` method takes [`shcsr::W`](W) writer structure"]
227impl crate::Writable for ShcsrSpec {
228    type Safety = crate::Unsafe;
229    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
230    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
231}
232#[doc = "`reset()` method sets SHCSR to value 0"]
233impl crate::Resettable for ShcsrSpec {
234    const RESET_VALUE: u32 = 0;
235}
atsamd51g/system_control/shcsr.rs

atsamd51g/system_control/
shcsr.rs
