atsamd51g/sdhc0/
nisier_emmc_mode.rs

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1#[doc = "Register `NISIER_EMMC_MODE` reader"]
2pub type R = crate::R<NisierEmmcModeSpec>;
3#[doc = "Register `NISIER_EMMC_MODE` writer"]
4pub type W = crate::W<NisierEmmcModeSpec>;
5#[doc = "Command Complete Signal Enable\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7pub enum Cmdcselect {
8    #[doc = "0: Masked"]
9    Masked = 0,
10    #[doc = "1: Enabled"]
11    Enabled = 1,
12}
13impl From<Cmdcselect> for bool {
14    #[inline(always)]
15    fn from(variant: Cmdcselect) -> Self {
16        variant as u8 != 0
17    }
18}
19#[doc = "Field `CMDC` reader - Command Complete Signal Enable"]
20pub type CmdcR = crate::BitReader<Cmdcselect>;
21impl CmdcR {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> Cmdcselect {
25        match self.bits {
26            false => Cmdcselect::Masked,
27            true => Cmdcselect::Enabled,
28        }
29    }
30    #[doc = "Masked"]
31    #[inline(always)]
32    pub fn is_masked(&self) -> bool {
33        *self == Cmdcselect::Masked
34    }
35    #[doc = "Enabled"]
36    #[inline(always)]
37    pub fn is_enabled(&self) -> bool {
38        *self == Cmdcselect::Enabled
39    }
40}
41#[doc = "Field `CMDC` writer - Command Complete Signal Enable"]
42pub type CmdcW<'a, REG> = crate::BitWriter<'a, REG, Cmdcselect>;
43impl<'a, REG> CmdcW<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "Masked"]
48    #[inline(always)]
49    pub fn masked(self) -> &'a mut crate::W<REG> {
50        self.variant(Cmdcselect::Masked)
51    }
52    #[doc = "Enabled"]
53    #[inline(always)]
54    pub fn enabled(self) -> &'a mut crate::W<REG> {
55        self.variant(Cmdcselect::Enabled)
56    }
57}
58#[doc = "Transfer Complete Signal Enable\n\nValue on reset: 0"]
59#[derive(Clone, Copy, Debug, PartialEq, Eq)]
60pub enum Trfcselect {
61    #[doc = "0: Masked"]
62    Masked = 0,
63    #[doc = "1: Enabled"]
64    Enabled = 1,
65}
66impl From<Trfcselect> for bool {
67    #[inline(always)]
68    fn from(variant: Trfcselect) -> Self {
69        variant as u8 != 0
70    }
71}
72#[doc = "Field `TRFC` reader - Transfer Complete Signal Enable"]
73pub type TrfcR = crate::BitReader<Trfcselect>;
74impl TrfcR {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> Trfcselect {
78        match self.bits {
79            false => Trfcselect::Masked,
80            true => Trfcselect::Enabled,
81        }
82    }
83    #[doc = "Masked"]
84    #[inline(always)]
85    pub fn is_masked(&self) -> bool {
86        *self == Trfcselect::Masked
87    }
88    #[doc = "Enabled"]
89    #[inline(always)]
90    pub fn is_enabled(&self) -> bool {
91        *self == Trfcselect::Enabled
92    }
93}
94#[doc = "Field `TRFC` writer - Transfer Complete Signal Enable"]
95pub type TrfcW<'a, REG> = crate::BitWriter<'a, REG, Trfcselect>;
96impl<'a, REG> TrfcW<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "Masked"]
101    #[inline(always)]
102    pub fn masked(self) -> &'a mut crate::W<REG> {
103        self.variant(Trfcselect::Masked)
104    }
105    #[doc = "Enabled"]
106    #[inline(always)]
107    pub fn enabled(self) -> &'a mut crate::W<REG> {
108        self.variant(Trfcselect::Enabled)
109    }
110}
111#[doc = "Block Gap Event Signal Enable\n\nValue on reset: 0"]
112#[derive(Clone, Copy, Debug, PartialEq, Eq)]
113pub enum Blkgeselect {
114    #[doc = "0: Masked"]
115    Masked = 0,
116    #[doc = "1: Enabled"]
117    Enabled = 1,
118}
119impl From<Blkgeselect> for bool {
120    #[inline(always)]
121    fn from(variant: Blkgeselect) -> Self {
122        variant as u8 != 0
123    }
124}
125#[doc = "Field `BLKGE` reader - Block Gap Event Signal Enable"]
126pub type BlkgeR = crate::BitReader<Blkgeselect>;
127impl BlkgeR {
128    #[doc = "Get enumerated values variant"]
129    #[inline(always)]
130    pub const fn variant(&self) -> Blkgeselect {
131        match self.bits {
132            false => Blkgeselect::Masked,
133            true => Blkgeselect::Enabled,
134        }
135    }
136    #[doc = "Masked"]
137    #[inline(always)]
138    pub fn is_masked(&self) -> bool {
139        *self == Blkgeselect::Masked
140    }
141    #[doc = "Enabled"]
142    #[inline(always)]
143    pub fn is_enabled(&self) -> bool {
144        *self == Blkgeselect::Enabled
145    }
146}
147#[doc = "Field `BLKGE` writer - Block Gap Event Signal Enable"]
148pub type BlkgeW<'a, REG> = crate::BitWriter<'a, REG, Blkgeselect>;
149impl<'a, REG> BlkgeW<'a, REG>
150where
151    REG: crate::Writable + crate::RegisterSpec,
152{
153    #[doc = "Masked"]
154    #[inline(always)]
155    pub fn masked(self) -> &'a mut crate::W<REG> {
156        self.variant(Blkgeselect::Masked)
157    }
158    #[doc = "Enabled"]
159    #[inline(always)]
160    pub fn enabled(self) -> &'a mut crate::W<REG> {
161        self.variant(Blkgeselect::Enabled)
162    }
163}
164#[doc = "DMA Interrupt Signal Enable\n\nValue on reset: 0"]
165#[derive(Clone, Copy, Debug, PartialEq, Eq)]
166pub enum Dmaintselect {
167    #[doc = "0: Masked"]
168    Masked = 0,
169    #[doc = "1: Enabled"]
170    Enabled = 1,
171}
172impl From<Dmaintselect> for bool {
173    #[inline(always)]
174    fn from(variant: Dmaintselect) -> Self {
175        variant as u8 != 0
176    }
177}
178#[doc = "Field `DMAINT` reader - DMA Interrupt Signal Enable"]
179pub type DmaintR = crate::BitReader<Dmaintselect>;
180impl DmaintR {
181    #[doc = "Get enumerated values variant"]
182    #[inline(always)]
183    pub const fn variant(&self) -> Dmaintselect {
184        match self.bits {
185            false => Dmaintselect::Masked,
186            true => Dmaintselect::Enabled,
187        }
188    }
189    #[doc = "Masked"]
190    #[inline(always)]
191    pub fn is_masked(&self) -> bool {
192        *self == Dmaintselect::Masked
193    }
194    #[doc = "Enabled"]
195    #[inline(always)]
196    pub fn is_enabled(&self) -> bool {
197        *self == Dmaintselect::Enabled
198    }
199}
200#[doc = "Field `DMAINT` writer - DMA Interrupt Signal Enable"]
201pub type DmaintW<'a, REG> = crate::BitWriter<'a, REG, Dmaintselect>;
202impl<'a, REG> DmaintW<'a, REG>
203where
204    REG: crate::Writable + crate::RegisterSpec,
205{
206    #[doc = "Masked"]
207    #[inline(always)]
208    pub fn masked(self) -> &'a mut crate::W<REG> {
209        self.variant(Dmaintselect::Masked)
210    }
211    #[doc = "Enabled"]
212    #[inline(always)]
213    pub fn enabled(self) -> &'a mut crate::W<REG> {
214        self.variant(Dmaintselect::Enabled)
215    }
216}
217#[doc = "Buffer Write Ready Signal Enable\n\nValue on reset: 0"]
218#[derive(Clone, Copy, Debug, PartialEq, Eq)]
219pub enum Bwrrdyselect {
220    #[doc = "0: Masked"]
221    Masked = 0,
222    #[doc = "1: Enabled"]
223    Enabled = 1,
224}
225impl From<Bwrrdyselect> for bool {
226    #[inline(always)]
227    fn from(variant: Bwrrdyselect) -> Self {
228        variant as u8 != 0
229    }
230}
231#[doc = "Field `BWRRDY` reader - Buffer Write Ready Signal Enable"]
232pub type BwrrdyR = crate::BitReader<Bwrrdyselect>;
233impl BwrrdyR {
234    #[doc = "Get enumerated values variant"]
235    #[inline(always)]
236    pub const fn variant(&self) -> Bwrrdyselect {
237        match self.bits {
238            false => Bwrrdyselect::Masked,
239            true => Bwrrdyselect::Enabled,
240        }
241    }
242    #[doc = "Masked"]
243    #[inline(always)]
244    pub fn is_masked(&self) -> bool {
245        *self == Bwrrdyselect::Masked
246    }
247    #[doc = "Enabled"]
248    #[inline(always)]
249    pub fn is_enabled(&self) -> bool {
250        *self == Bwrrdyselect::Enabled
251    }
252}
253#[doc = "Field `BWRRDY` writer - Buffer Write Ready Signal Enable"]
254pub type BwrrdyW<'a, REG> = crate::BitWriter<'a, REG, Bwrrdyselect>;
255impl<'a, REG> BwrrdyW<'a, REG>
256where
257    REG: crate::Writable + crate::RegisterSpec,
258{
259    #[doc = "Masked"]
260    #[inline(always)]
261    pub fn masked(self) -> &'a mut crate::W<REG> {
262        self.variant(Bwrrdyselect::Masked)
263    }
264    #[doc = "Enabled"]
265    #[inline(always)]
266    pub fn enabled(self) -> &'a mut crate::W<REG> {
267        self.variant(Bwrrdyselect::Enabled)
268    }
269}
270#[doc = "Buffer Read Ready Signal Enable\n\nValue on reset: 0"]
271#[derive(Clone, Copy, Debug, PartialEq, Eq)]
272pub enum Brdrdyselect {
273    #[doc = "0: Masked"]
274    Masked = 0,
275    #[doc = "1: Enabled"]
276    Enabled = 1,
277}
278impl From<Brdrdyselect> for bool {
279    #[inline(always)]
280    fn from(variant: Brdrdyselect) -> Self {
281        variant as u8 != 0
282    }
283}
284#[doc = "Field `BRDRDY` reader - Buffer Read Ready Signal Enable"]
285pub type BrdrdyR = crate::BitReader<Brdrdyselect>;
286impl BrdrdyR {
287    #[doc = "Get enumerated values variant"]
288    #[inline(always)]
289    pub const fn variant(&self) -> Brdrdyselect {
290        match self.bits {
291            false => Brdrdyselect::Masked,
292            true => Brdrdyselect::Enabled,
293        }
294    }
295    #[doc = "Masked"]
296    #[inline(always)]
297    pub fn is_masked(&self) -> bool {
298        *self == Brdrdyselect::Masked
299    }
300    #[doc = "Enabled"]
301    #[inline(always)]
302    pub fn is_enabled(&self) -> bool {
303        *self == Brdrdyselect::Enabled
304    }
305}
306#[doc = "Field `BRDRDY` writer - Buffer Read Ready Signal Enable"]
307pub type BrdrdyW<'a, REG> = crate::BitWriter<'a, REG, Brdrdyselect>;
308impl<'a, REG> BrdrdyW<'a, REG>
309where
310    REG: crate::Writable + crate::RegisterSpec,
311{
312    #[doc = "Masked"]
313    #[inline(always)]
314    pub fn masked(self) -> &'a mut crate::W<REG> {
315        self.variant(Brdrdyselect::Masked)
316    }
317    #[doc = "Enabled"]
318    #[inline(always)]
319    pub fn enabled(self) -> &'a mut crate::W<REG> {
320        self.variant(Brdrdyselect::Enabled)
321    }
322}
323#[doc = "Field `BOOTAR` reader - Boot Acknowledge Received Signal Enable"]
324pub type BootarR = crate::BitReader;
325#[doc = "Field `BOOTAR` writer - Boot Acknowledge Received Signal Enable"]
326pub type BootarW<'a, REG> = crate::BitWriter<'a, REG>;
327impl R {
328    #[doc = "Bit 0 - Command Complete Signal Enable"]
329    #[inline(always)]
330    pub fn cmdc(&self) -> CmdcR {
331        CmdcR::new((self.bits & 1) != 0)
332    }
333    #[doc = "Bit 1 - Transfer Complete Signal Enable"]
334    #[inline(always)]
335    pub fn trfc(&self) -> TrfcR {
336        TrfcR::new(((self.bits >> 1) & 1) != 0)
337    }
338    #[doc = "Bit 2 - Block Gap Event Signal Enable"]
339    #[inline(always)]
340    pub fn blkge(&self) -> BlkgeR {
341        BlkgeR::new(((self.bits >> 2) & 1) != 0)
342    }
343    #[doc = "Bit 3 - DMA Interrupt Signal Enable"]
344    #[inline(always)]
345    pub fn dmaint(&self) -> DmaintR {
346        DmaintR::new(((self.bits >> 3) & 1) != 0)
347    }
348    #[doc = "Bit 4 - Buffer Write Ready Signal Enable"]
349    #[inline(always)]
350    pub fn bwrrdy(&self) -> BwrrdyR {
351        BwrrdyR::new(((self.bits >> 4) & 1) != 0)
352    }
353    #[doc = "Bit 5 - Buffer Read Ready Signal Enable"]
354    #[inline(always)]
355    pub fn brdrdy(&self) -> BrdrdyR {
356        BrdrdyR::new(((self.bits >> 5) & 1) != 0)
357    }
358    #[doc = "Bit 14 - Boot Acknowledge Received Signal Enable"]
359    #[inline(always)]
360    pub fn bootar(&self) -> BootarR {
361        BootarR::new(((self.bits >> 14) & 1) != 0)
362    }
363}
364impl W {
365    #[doc = "Bit 0 - Command Complete Signal Enable"]
366    #[inline(always)]
367    #[must_use]
368    pub fn cmdc(&mut self) -> CmdcW<NisierEmmcModeSpec> {
369        CmdcW::new(self, 0)
370    }
371    #[doc = "Bit 1 - Transfer Complete Signal Enable"]
372    #[inline(always)]
373    #[must_use]
374    pub fn trfc(&mut self) -> TrfcW<NisierEmmcModeSpec> {
375        TrfcW::new(self, 1)
376    }
377    #[doc = "Bit 2 - Block Gap Event Signal Enable"]
378    #[inline(always)]
379    #[must_use]
380    pub fn blkge(&mut self) -> BlkgeW<NisierEmmcModeSpec> {
381        BlkgeW::new(self, 2)
382    }
383    #[doc = "Bit 3 - DMA Interrupt Signal Enable"]
384    #[inline(always)]
385    #[must_use]
386    pub fn dmaint(&mut self) -> DmaintW<NisierEmmcModeSpec> {
387        DmaintW::new(self, 3)
388    }
389    #[doc = "Bit 4 - Buffer Write Ready Signal Enable"]
390    #[inline(always)]
391    #[must_use]
392    pub fn bwrrdy(&mut self) -> BwrrdyW<NisierEmmcModeSpec> {
393        BwrrdyW::new(self, 4)
394    }
395    #[doc = "Bit 5 - Buffer Read Ready Signal Enable"]
396    #[inline(always)]
397    #[must_use]
398    pub fn brdrdy(&mut self) -> BrdrdyW<NisierEmmcModeSpec> {
399        BrdrdyW::new(self, 5)
400    }
401    #[doc = "Bit 14 - Boot Acknowledge Received Signal Enable"]
402    #[inline(always)]
403    #[must_use]
404    pub fn bootar(&mut self) -> BootarW<NisierEmmcModeSpec> {
405        BootarW::new(self, 14)
406    }
407}
408#[doc = "Normal Interrupt Signal Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`nisier_emmc_mode::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nisier_emmc_mode::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
409pub struct NisierEmmcModeSpec;
410impl crate::RegisterSpec for NisierEmmcModeSpec {
411    type Ux = u16;
412}
413#[doc = "`read()` method returns [`nisier_emmc_mode::R`](R) reader structure"]
414impl crate::Readable for NisierEmmcModeSpec {}
415#[doc = "`write(|w| ..)` method takes [`nisier_emmc_mode::W`](W) writer structure"]
416impl crate::Writable for NisierEmmcModeSpec {
417    type Safety = crate::Unsafe;
418    const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
419    const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
420}
421#[doc = "`reset()` method sets NISIER_EMMC_MODE to value 0"]
422impl crate::Resettable for NisierEmmcModeSpec {
423    const RESET_VALUE: u16 = 0;
424}
atsamd51g/sdhc0/nisier_emmc_mode.rs

atsamd51g/sdhc0/
nisier_emmc_mode.rs
