atsamd51g/pdec/
intenclr.rs

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1#[doc = "Register `INTENCLR` reader"]
2pub type R = crate::R<IntenclrSpec>;
3#[doc = "Register `INTENCLR` writer"]
4pub type W = crate::W<IntenclrSpec>;
5#[doc = "Field `OVF` reader - Overflow/Underflow Interrupt Disable"]
6pub type OvfR = crate::BitReader;
7#[doc = "Field `OVF` writer - Overflow/Underflow Interrupt Disable"]
8pub type OvfW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `ERR` reader - Error Interrupt Disable"]
10pub type ErrR = crate::BitReader;
11#[doc = "Field `ERR` writer - Error Interrupt Disable"]
12pub type ErrW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `DIR` reader - Direction Interrupt Disable"]
14pub type DirR = crate::BitReader;
15#[doc = "Field `DIR` writer - Direction Interrupt Disable"]
16pub type DirW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `VLC` reader - Velocity Interrupt Disable"]
18pub type VlcR = crate::BitReader;
19#[doc = "Field `VLC` writer - Velocity Interrupt Disable"]
20pub type VlcW<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `MC0` reader - Channel 0 Compare Match Disable"]
22pub type Mc0R = crate::BitReader;
23#[doc = "Field `MC0` writer - Channel 0 Compare Match Disable"]
24pub type Mc0W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `MC1` reader - Channel 1 Compare Match Disable"]
26pub type Mc1R = crate::BitReader;
27#[doc = "Field `MC1` writer - Channel 1 Compare Match Disable"]
28pub type Mc1W<'a, REG> = crate::BitWriter<'a, REG>;
29impl R {
30    #[doc = "Bit 0 - Overflow/Underflow Interrupt Disable"]
31    #[inline(always)]
32    pub fn ovf(&self) -> OvfR {
33        OvfR::new((self.bits & 1) != 0)
34    }
35    #[doc = "Bit 1 - Error Interrupt Disable"]
36    #[inline(always)]
37    pub fn err(&self) -> ErrR {
38        ErrR::new(((self.bits >> 1) & 1) != 0)
39    }
40    #[doc = "Bit 2 - Direction Interrupt Disable"]
41    #[inline(always)]
42    pub fn dir(&self) -> DirR {
43        DirR::new(((self.bits >> 2) & 1) != 0)
44    }
45    #[doc = "Bit 3 - Velocity Interrupt Disable"]
46    #[inline(always)]
47    pub fn vlc(&self) -> VlcR {
48        VlcR::new(((self.bits >> 3) & 1) != 0)
49    }
50    #[doc = "Bit 4 - Channel 0 Compare Match Disable"]
51    #[inline(always)]
52    pub fn mc0(&self) -> Mc0R {
53        Mc0R::new(((self.bits >> 4) & 1) != 0)
54    }
55    #[doc = "Bit 5 - Channel 1 Compare Match Disable"]
56    #[inline(always)]
57    pub fn mc1(&self) -> Mc1R {
58        Mc1R::new(((self.bits >> 5) & 1) != 0)
59    }
60}
61impl W {
62    #[doc = "Bit 0 - Overflow/Underflow Interrupt Disable"]
63    #[inline(always)]
64    #[must_use]
65    pub fn ovf(&mut self) -> OvfW<IntenclrSpec> {
66        OvfW::new(self, 0)
67    }
68    #[doc = "Bit 1 - Error Interrupt Disable"]
69    #[inline(always)]
70    #[must_use]
71    pub fn err(&mut self) -> ErrW<IntenclrSpec> {
72        ErrW::new(self, 1)
73    }
74    #[doc = "Bit 2 - Direction Interrupt Disable"]
75    #[inline(always)]
76    #[must_use]
77    pub fn dir(&mut self) -> DirW<IntenclrSpec> {
78        DirW::new(self, 2)
79    }
80    #[doc = "Bit 3 - Velocity Interrupt Disable"]
81    #[inline(always)]
82    #[must_use]
83    pub fn vlc(&mut self) -> VlcW<IntenclrSpec> {
84        VlcW::new(self, 3)
85    }
86    #[doc = "Bit 4 - Channel 0 Compare Match Disable"]
87    #[inline(always)]
88    #[must_use]
89    pub fn mc0(&mut self) -> Mc0W<IntenclrSpec> {
90        Mc0W::new(self, 4)
91    }
92    #[doc = "Bit 5 - Channel 1 Compare Match Disable"]
93    #[inline(always)]
94    #[must_use]
95    pub fn mc1(&mut self) -> Mc1W<IntenclrSpec> {
96        Mc1W::new(self, 5)
97    }
98}
99#[doc = "Interrupt Enable Clear\n\nYou can [`read`](crate::Reg::read) this register and get [`intenclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intenclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
100pub struct IntenclrSpec;
101impl crate::RegisterSpec for IntenclrSpec {
102    type Ux = u8;
103}
104#[doc = "`read()` method returns [`intenclr::R`](R) reader structure"]
105impl crate::Readable for IntenclrSpec {}
106#[doc = "`write(|w| ..)` method takes [`intenclr::W`](W) writer structure"]
107impl crate::Writable for IntenclrSpec {
108    type Safety = crate::Unsafe;
109    const ZERO_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
110    const ONE_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
111}
112#[doc = "`reset()` method sets INTENCLR to value 0"]
113impl crate::Resettable for IntenclrSpec {
114    const RESET_VALUE: u8 = 0;
115}
atsamd51g/pdec/intenclr.rs

atsamd51g/pdec/
intenclr.rs
