atsamd51g/nvmctrl/
intenclr.rs

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1#[doc = "Register `INTENCLR` reader"]
2pub type R = crate::R<IntenclrSpec>;
3#[doc = "Register `INTENCLR` writer"]
4pub type W = crate::W<IntenclrSpec>;
5#[doc = "Field `DONE` reader - Command Done Interrupt Clear"]
6pub type DoneR = crate::BitReader;
7#[doc = "Field `DONE` writer - Command Done Interrupt Clear"]
8pub type DoneW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `ADDRE` reader - Address Error"]
10pub type AddreR = crate::BitReader;
11#[doc = "Field `ADDRE` writer - Address Error"]
12pub type AddreW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `PROGE` reader - Programming Error Interrupt Clear"]
14pub type ProgeR = crate::BitReader;
15#[doc = "Field `PROGE` writer - Programming Error Interrupt Clear"]
16pub type ProgeW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `LOCKE` reader - Lock Error Interrupt Clear"]
18pub type LockeR = crate::BitReader;
19#[doc = "Field `LOCKE` writer - Lock Error Interrupt Clear"]
20pub type LockeW<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `ECCSE` reader - ECC Single Error Interrupt Clear"]
22pub type EccseR = crate::BitReader;
23#[doc = "Field `ECCSE` writer - ECC Single Error Interrupt Clear"]
24pub type EccseW<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `ECCDE` reader - ECC Dual Error Interrupt Clear"]
26pub type EccdeR = crate::BitReader;
27#[doc = "Field `ECCDE` writer - ECC Dual Error Interrupt Clear"]
28pub type EccdeW<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `NVME` reader - NVM Error Interrupt Clear"]
30pub type NvmeR = crate::BitReader;
31#[doc = "Field `NVME` writer - NVM Error Interrupt Clear"]
32pub type NvmeW<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `SUSP` reader - Suspended Write Or Erase Interrupt Clear"]
34pub type SuspR = crate::BitReader;
35#[doc = "Field `SUSP` writer - Suspended Write Or Erase Interrupt Clear"]
36pub type SuspW<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `SEESFULL` reader - Active SEES Full Interrupt Clear"]
38pub type SeesfullR = crate::BitReader;
39#[doc = "Field `SEESFULL` writer - Active SEES Full Interrupt Clear"]
40pub type SeesfullW<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `SEESOVF` reader - Active SEES Overflow Interrupt Clear"]
42pub type SeesovfR = crate::BitReader;
43#[doc = "Field `SEESOVF` writer - Active SEES Overflow Interrupt Clear"]
44pub type SeesovfW<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `SEEWRC` reader - SEE Write Completed Interrupt Clear"]
46pub type SeewrcR = crate::BitReader;
47#[doc = "Field `SEEWRC` writer - SEE Write Completed Interrupt Clear"]
48pub type SeewrcW<'a, REG> = crate::BitWriter<'a, REG>;
49impl R {
50    #[doc = "Bit 0 - Command Done Interrupt Clear"]
51    #[inline(always)]
52    pub fn done(&self) -> DoneR {
53        DoneR::new((self.bits & 1) != 0)
54    }
55    #[doc = "Bit 1 - Address Error"]
56    #[inline(always)]
57    pub fn addre(&self) -> AddreR {
58        AddreR::new(((self.bits >> 1) & 1) != 0)
59    }
60    #[doc = "Bit 2 - Programming Error Interrupt Clear"]
61    #[inline(always)]
62    pub fn proge(&self) -> ProgeR {
63        ProgeR::new(((self.bits >> 2) & 1) != 0)
64    }
65    #[doc = "Bit 3 - Lock Error Interrupt Clear"]
66    #[inline(always)]
67    pub fn locke(&self) -> LockeR {
68        LockeR::new(((self.bits >> 3) & 1) != 0)
69    }
70    #[doc = "Bit 4 - ECC Single Error Interrupt Clear"]
71    #[inline(always)]
72    pub fn eccse(&self) -> EccseR {
73        EccseR::new(((self.bits >> 4) & 1) != 0)
74    }
75    #[doc = "Bit 5 - ECC Dual Error Interrupt Clear"]
76    #[inline(always)]
77    pub fn eccde(&self) -> EccdeR {
78        EccdeR::new(((self.bits >> 5) & 1) != 0)
79    }
80    #[doc = "Bit 6 - NVM Error Interrupt Clear"]
81    #[inline(always)]
82    pub fn nvme(&self) -> NvmeR {
83        NvmeR::new(((self.bits >> 6) & 1) != 0)
84    }
85    #[doc = "Bit 7 - Suspended Write Or Erase Interrupt Clear"]
86    #[inline(always)]
87    pub fn susp(&self) -> SuspR {
88        SuspR::new(((self.bits >> 7) & 1) != 0)
89    }
90    #[doc = "Bit 8 - Active SEES Full Interrupt Clear"]
91    #[inline(always)]
92    pub fn seesfull(&self) -> SeesfullR {
93        SeesfullR::new(((self.bits >> 8) & 1) != 0)
94    }
95    #[doc = "Bit 9 - Active SEES Overflow Interrupt Clear"]
96    #[inline(always)]
97    pub fn seesovf(&self) -> SeesovfR {
98        SeesovfR::new(((self.bits >> 9) & 1) != 0)
99    }
100    #[doc = "Bit 10 - SEE Write Completed Interrupt Clear"]
101    #[inline(always)]
102    pub fn seewrc(&self) -> SeewrcR {
103        SeewrcR::new(((self.bits >> 10) & 1) != 0)
104    }
105}
106impl W {
107    #[doc = "Bit 0 - Command Done Interrupt Clear"]
108    #[inline(always)]
109    #[must_use]
110    pub fn done(&mut self) -> DoneW<IntenclrSpec> {
111        DoneW::new(self, 0)
112    }
113    #[doc = "Bit 1 - Address Error"]
114    #[inline(always)]
115    #[must_use]
116    pub fn addre(&mut self) -> AddreW<IntenclrSpec> {
117        AddreW::new(self, 1)
118    }
119    #[doc = "Bit 2 - Programming Error Interrupt Clear"]
120    #[inline(always)]
121    #[must_use]
122    pub fn proge(&mut self) -> ProgeW<IntenclrSpec> {
123        ProgeW::new(self, 2)
124    }
125    #[doc = "Bit 3 - Lock Error Interrupt Clear"]
126    #[inline(always)]
127    #[must_use]
128    pub fn locke(&mut self) -> LockeW<IntenclrSpec> {
129        LockeW::new(self, 3)
130    }
131    #[doc = "Bit 4 - ECC Single Error Interrupt Clear"]
132    #[inline(always)]
133    #[must_use]
134    pub fn eccse(&mut self) -> EccseW<IntenclrSpec> {
135        EccseW::new(self, 4)
136    }
137    #[doc = "Bit 5 - ECC Dual Error Interrupt Clear"]
138    #[inline(always)]
139    #[must_use]
140    pub fn eccde(&mut self) -> EccdeW<IntenclrSpec> {
141        EccdeW::new(self, 5)
142    }
143    #[doc = "Bit 6 - NVM Error Interrupt Clear"]
144    #[inline(always)]
145    #[must_use]
146    pub fn nvme(&mut self) -> NvmeW<IntenclrSpec> {
147        NvmeW::new(self, 6)
148    }
149    #[doc = "Bit 7 - Suspended Write Or Erase Interrupt Clear"]
150    #[inline(always)]
151    #[must_use]
152    pub fn susp(&mut self) -> SuspW<IntenclrSpec> {
153        SuspW::new(self, 7)
154    }
155    #[doc = "Bit 8 - Active SEES Full Interrupt Clear"]
156    #[inline(always)]
157    #[must_use]
158    pub fn seesfull(&mut self) -> SeesfullW<IntenclrSpec> {
159        SeesfullW::new(self, 8)
160    }
161    #[doc = "Bit 9 - Active SEES Overflow Interrupt Clear"]
162    #[inline(always)]
163    #[must_use]
164    pub fn seesovf(&mut self) -> SeesovfW<IntenclrSpec> {
165        SeesovfW::new(self, 9)
166    }
167    #[doc = "Bit 10 - SEE Write Completed Interrupt Clear"]
168    #[inline(always)]
169    #[must_use]
170    pub fn seewrc(&mut self) -> SeewrcW<IntenclrSpec> {
171        SeewrcW::new(self, 10)
172    }
173}
174#[doc = "Interrupt Enable Clear\n\nYou can [`read`](crate::Reg::read) this register and get [`intenclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intenclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
175pub struct IntenclrSpec;
176impl crate::RegisterSpec for IntenclrSpec {
177    type Ux = u16;
178}
179#[doc = "`read()` method returns [`intenclr::R`](R) reader structure"]
180impl crate::Readable for IntenclrSpec {}
181#[doc = "`write(|w| ..)` method takes [`intenclr::W`](W) writer structure"]
182impl crate::Writable for IntenclrSpec {
183    type Safety = crate::Unsafe;
184    const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
185    const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
186}
187#[doc = "`reset()` method sets INTENCLR to value 0"]
188impl crate::Resettable for IntenclrSpec {
189    const RESET_VALUE: u16 = 0;
190}
atsamd51g/nvmctrl/intenclr.rs

atsamd51g/nvmctrl/
intenclr.rs
