atsamd51g/sdhc0/
ccr.rs

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1#[doc = "Register `CCR` reader"]
2pub type R = crate::R<CcrSpec>;
3#[doc = "Register `CCR` writer"]
4pub type W = crate::W<CcrSpec>;
5#[doc = "Internal Clock Enable\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7pub enum Intclkenselect {
8    #[doc = "0: Stop"]
9    Off = 0,
10    #[doc = "1: Oscillate"]
11    On = 1,
12}
13impl From<Intclkenselect> for bool {
14    #[inline(always)]
15    fn from(variant: Intclkenselect) -> Self {
16        variant as u8 != 0
17    }
18}
19#[doc = "Field `INTCLKEN` reader - Internal Clock Enable"]
20pub type IntclkenR = crate::BitReader<Intclkenselect>;
21impl IntclkenR {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> Intclkenselect {
25        match self.bits {
26            false => Intclkenselect::Off,
27            true => Intclkenselect::On,
28        }
29    }
30    #[doc = "Stop"]
31    #[inline(always)]
32    pub fn is_off(&self) -> bool {
33        *self == Intclkenselect::Off
34    }
35    #[doc = "Oscillate"]
36    #[inline(always)]
37    pub fn is_on(&self) -> bool {
38        *self == Intclkenselect::On
39    }
40}
41#[doc = "Field `INTCLKEN` writer - Internal Clock Enable"]
42pub type IntclkenW<'a, REG> = crate::BitWriter<'a, REG, Intclkenselect>;
43impl<'a, REG> IntclkenW<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "Stop"]
48    #[inline(always)]
49    pub fn off(self) -> &'a mut crate::W<REG> {
50        self.variant(Intclkenselect::Off)
51    }
52    #[doc = "Oscillate"]
53    #[inline(always)]
54    pub fn on(self) -> &'a mut crate::W<REG> {
55        self.variant(Intclkenselect::On)
56    }
57}
58#[doc = "Internal Clock Stable\n\nValue on reset: 0"]
59#[derive(Clone, Copy, Debug, PartialEq, Eq)]
60pub enum Intclksselect {
61    #[doc = "0: Not Ready"]
62    NotReady = 0,
63    #[doc = "1: Ready"]
64    Ready = 1,
65}
66impl From<Intclksselect> for bool {
67    #[inline(always)]
68    fn from(variant: Intclksselect) -> Self {
69        variant as u8 != 0
70    }
71}
72#[doc = "Field `INTCLKS` reader - Internal Clock Stable"]
73pub type IntclksR = crate::BitReader<Intclksselect>;
74impl IntclksR {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> Intclksselect {
78        match self.bits {
79            false => Intclksselect::NotReady,
80            true => Intclksselect::Ready,
81        }
82    }
83    #[doc = "Not Ready"]
84    #[inline(always)]
85    pub fn is_not_ready(&self) -> bool {
86        *self == Intclksselect::NotReady
87    }
88    #[doc = "Ready"]
89    #[inline(always)]
90    pub fn is_ready(&self) -> bool {
91        *self == Intclksselect::Ready
92    }
93}
94#[doc = "Field `INTCLKS` writer - Internal Clock Stable"]
95pub type IntclksW<'a, REG> = crate::BitWriter<'a, REG, Intclksselect>;
96impl<'a, REG> IntclksW<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "Not Ready"]
101    #[inline(always)]
102    pub fn not_ready(self) -> &'a mut crate::W<REG> {
103        self.variant(Intclksselect::NotReady)
104    }
105    #[doc = "Ready"]
106    #[inline(always)]
107    pub fn ready(self) -> &'a mut crate::W<REG> {
108        self.variant(Intclksselect::Ready)
109    }
110}
111#[doc = "SD Clock Enable\n\nValue on reset: 0"]
112#[derive(Clone, Copy, Debug, PartialEq, Eq)]
113pub enum Sdclkenselect {
114    #[doc = "0: Disable"]
115    Disable = 0,
116    #[doc = "1: Enable"]
117    Enable = 1,
118}
119impl From<Sdclkenselect> for bool {
120    #[inline(always)]
121    fn from(variant: Sdclkenselect) -> Self {
122        variant as u8 != 0
123    }
124}
125#[doc = "Field `SDCLKEN` reader - SD Clock Enable"]
126pub type SdclkenR = crate::BitReader<Sdclkenselect>;
127impl SdclkenR {
128    #[doc = "Get enumerated values variant"]
129    #[inline(always)]
130    pub const fn variant(&self) -> Sdclkenselect {
131        match self.bits {
132            false => Sdclkenselect::Disable,
133            true => Sdclkenselect::Enable,
134        }
135    }
136    #[doc = "Disable"]
137    #[inline(always)]
138    pub fn is_disable(&self) -> bool {
139        *self == Sdclkenselect::Disable
140    }
141    #[doc = "Enable"]
142    #[inline(always)]
143    pub fn is_enable(&self) -> bool {
144        *self == Sdclkenselect::Enable
145    }
146}
147#[doc = "Field `SDCLKEN` writer - SD Clock Enable"]
148pub type SdclkenW<'a, REG> = crate::BitWriter<'a, REG, Sdclkenselect>;
149impl<'a, REG> SdclkenW<'a, REG>
150where
151    REG: crate::Writable + crate::RegisterSpec,
152{
153    #[doc = "Disable"]
154    #[inline(always)]
155    pub fn disable(self) -> &'a mut crate::W<REG> {
156        self.variant(Sdclkenselect::Disable)
157    }
158    #[doc = "Enable"]
159    #[inline(always)]
160    pub fn enable(self) -> &'a mut crate::W<REG> {
161        self.variant(Sdclkenselect::Enable)
162    }
163}
164#[doc = "Clock Generator Select\n\nValue on reset: 0"]
165#[derive(Clone, Copy, Debug, PartialEq, Eq)]
166pub enum Clkgselselect {
167    #[doc = "0: Divided Clock Mode"]
168    Div = 0,
169    #[doc = "1: Programmable Clock Mode"]
170    Prog = 1,
171}
172impl From<Clkgselselect> for bool {
173    #[inline(always)]
174    fn from(variant: Clkgselselect) -> Self {
175        variant as u8 != 0
176    }
177}
178#[doc = "Field `CLKGSEL` reader - Clock Generator Select"]
179pub type ClkgselR = crate::BitReader<Clkgselselect>;
180impl ClkgselR {
181    #[doc = "Get enumerated values variant"]
182    #[inline(always)]
183    pub const fn variant(&self) -> Clkgselselect {
184        match self.bits {
185            false => Clkgselselect::Div,
186            true => Clkgselselect::Prog,
187        }
188    }
189    #[doc = "Divided Clock Mode"]
190    #[inline(always)]
191    pub fn is_div(&self) -> bool {
192        *self == Clkgselselect::Div
193    }
194    #[doc = "Programmable Clock Mode"]
195    #[inline(always)]
196    pub fn is_prog(&self) -> bool {
197        *self == Clkgselselect::Prog
198    }
199}
200#[doc = "Field `CLKGSEL` writer - Clock Generator Select"]
201pub type ClkgselW<'a, REG> = crate::BitWriter<'a, REG, Clkgselselect>;
202impl<'a, REG> ClkgselW<'a, REG>
203where
204    REG: crate::Writable + crate::RegisterSpec,
205{
206    #[doc = "Divided Clock Mode"]
207    #[inline(always)]
208    pub fn div(self) -> &'a mut crate::W<REG> {
209        self.variant(Clkgselselect::Div)
210    }
211    #[doc = "Programmable Clock Mode"]
212    #[inline(always)]
213    pub fn prog(self) -> &'a mut crate::W<REG> {
214        self.variant(Clkgselselect::Prog)
215    }
216}
217#[doc = "Field `USDCLKFSEL` reader - Upper Bits of SDCLK Frequency Select"]
218pub type UsdclkfselR = crate::FieldReader;
219#[doc = "Field `USDCLKFSEL` writer - Upper Bits of SDCLK Frequency Select"]
220pub type UsdclkfselW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
221#[doc = "Field `SDCLKFSEL` reader - SDCLK Frequency Select"]
222pub type SdclkfselR = crate::FieldReader;
223#[doc = "Field `SDCLKFSEL` writer - SDCLK Frequency Select"]
224pub type SdclkfselW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
225impl R {
226    #[doc = "Bit 0 - Internal Clock Enable"]
227    #[inline(always)]
228    pub fn intclken(&self) -> IntclkenR {
229        IntclkenR::new((self.bits & 1) != 0)
230    }
231    #[doc = "Bit 1 - Internal Clock Stable"]
232    #[inline(always)]
233    pub fn intclks(&self) -> IntclksR {
234        IntclksR::new(((self.bits >> 1) & 1) != 0)
235    }
236    #[doc = "Bit 2 - SD Clock Enable"]
237    #[inline(always)]
238    pub fn sdclken(&self) -> SdclkenR {
239        SdclkenR::new(((self.bits >> 2) & 1) != 0)
240    }
241    #[doc = "Bit 5 - Clock Generator Select"]
242    #[inline(always)]
243    pub fn clkgsel(&self) -> ClkgselR {
244        ClkgselR::new(((self.bits >> 5) & 1) != 0)
245    }
246    #[doc = "Bits 6:7 - Upper Bits of SDCLK Frequency Select"]
247    #[inline(always)]
248    pub fn usdclkfsel(&self) -> UsdclkfselR {
249        UsdclkfselR::new(((self.bits >> 6) & 3) as u8)
250    }
251    #[doc = "Bits 8:15 - SDCLK Frequency Select"]
252    #[inline(always)]
253    pub fn sdclkfsel(&self) -> SdclkfselR {
254        SdclkfselR::new(((self.bits >> 8) & 0xff) as u8)
255    }
256}
257impl W {
258    #[doc = "Bit 0 - Internal Clock Enable"]
259    #[inline(always)]
260    #[must_use]
261    pub fn intclken(&mut self) -> IntclkenW<CcrSpec> {
262        IntclkenW::new(self, 0)
263    }
264    #[doc = "Bit 1 - Internal Clock Stable"]
265    #[inline(always)]
266    #[must_use]
267    pub fn intclks(&mut self) -> IntclksW<CcrSpec> {
268        IntclksW::new(self, 1)
269    }
270    #[doc = "Bit 2 - SD Clock Enable"]
271    #[inline(always)]
272    #[must_use]
273    pub fn sdclken(&mut self) -> SdclkenW<CcrSpec> {
274        SdclkenW::new(self, 2)
275    }
276    #[doc = "Bit 5 - Clock Generator Select"]
277    #[inline(always)]
278    #[must_use]
279    pub fn clkgsel(&mut self) -> ClkgselW<CcrSpec> {
280        ClkgselW::new(self, 5)
281    }
282    #[doc = "Bits 6:7 - Upper Bits of SDCLK Frequency Select"]
283    #[inline(always)]
284    #[must_use]
285    pub fn usdclkfsel(&mut self) -> UsdclkfselW<CcrSpec> {
286        UsdclkfselW::new(self, 6)
287    }
288    #[doc = "Bits 8:15 - SDCLK Frequency Select"]
289    #[inline(always)]
290    #[must_use]
291    pub fn sdclkfsel(&mut self) -> SdclkfselW<CcrSpec> {
292        SdclkfselW::new(self, 8)
293    }
294}
295#[doc = "Clock Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ccr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
296pub struct CcrSpec;
297impl crate::RegisterSpec for CcrSpec {
298    type Ux = u16;
299}
300#[doc = "`read()` method returns [`ccr::R`](R) reader structure"]
301impl crate::Readable for CcrSpec {}
302#[doc = "`write(|w| ..)` method takes [`ccr::W`](W) writer structure"]
303impl crate::Writable for CcrSpec {
304    type Safety = crate::Unsafe;
305    const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
306    const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
307}
308#[doc = "`reset()` method sets CCR to value 0"]
309impl crate::Resettable for CcrSpec {
310    const RESET_VALUE: u16 = 0;
311}
atsamd51g/sdhc0/ccr.rs

atsamd51g/sdhc0/
ccr.rs
