atsamd51g/evsys/channels/
channel.rs

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1#[doc = "Register `CHANNEL` reader"]
2pub type R = crate::R<ChannelSpec>;
3#[doc = "Register `CHANNEL` writer"]
4pub type W = crate::W<ChannelSpec>;
5#[doc = "Field `EVGEN` reader - Event Generator Selection"]
6pub type EvgenR = crate::FieldReader;
7#[doc = "Field `EVGEN` writer - Event Generator Selection"]
8pub type EvgenW<'a, REG> = crate::FieldWriter<'a, REG, 7>;
9#[doc = "Path Selection\n\nValue on reset: 0"]
10#[derive(Clone, Copy, Debug, PartialEq, Eq)]
11#[repr(u8)]
12pub enum Pathselect {
13    #[doc = "0: Synchronous path"]
14    Synchronous = 0,
15    #[doc = "1: Resynchronized path"]
16    Resynchronized = 1,
17    #[doc = "2: Asynchronous path"]
18    Asynchronous = 2,
19}
20impl From<Pathselect> for u8 {
21    #[inline(always)]
22    fn from(variant: Pathselect) -> Self {
23        variant as _
24    }
25}
26impl crate::FieldSpec for Pathselect {
27    type Ux = u8;
28}
29impl crate::IsEnum for Pathselect {}
30#[doc = "Field `PATH` reader - Path Selection"]
31pub type PathR = crate::FieldReader<Pathselect>;
32impl PathR {
33    #[doc = "Get enumerated values variant"]
34    #[inline(always)]
35    pub const fn variant(&self) -> Option<Pathselect> {
36        match self.bits {
37            0 => Some(Pathselect::Synchronous),
38            1 => Some(Pathselect::Resynchronized),
39            2 => Some(Pathselect::Asynchronous),
40            _ => None,
41        }
42    }
43    #[doc = "Synchronous path"]
44    #[inline(always)]
45    pub fn is_synchronous(&self) -> bool {
46        *self == Pathselect::Synchronous
47    }
48    #[doc = "Resynchronized path"]
49    #[inline(always)]
50    pub fn is_resynchronized(&self) -> bool {
51        *self == Pathselect::Resynchronized
52    }
53    #[doc = "Asynchronous path"]
54    #[inline(always)]
55    pub fn is_asynchronous(&self) -> bool {
56        *self == Pathselect::Asynchronous
57    }
58}
59#[doc = "Field `PATH` writer - Path Selection"]
60pub type PathW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pathselect>;
61impl<'a, REG> PathW<'a, REG>
62where
63    REG: crate::Writable + crate::RegisterSpec,
64    REG::Ux: From<u8>,
65{
66    #[doc = "Synchronous path"]
67    #[inline(always)]
68    pub fn synchronous(self) -> &'a mut crate::W<REG> {
69        self.variant(Pathselect::Synchronous)
70    }
71    #[doc = "Resynchronized path"]
72    #[inline(always)]
73    pub fn resynchronized(self) -> &'a mut crate::W<REG> {
74        self.variant(Pathselect::Resynchronized)
75    }
76    #[doc = "Asynchronous path"]
77    #[inline(always)]
78    pub fn asynchronous(self) -> &'a mut crate::W<REG> {
79        self.variant(Pathselect::Asynchronous)
80    }
81}
82#[doc = "Edge Detection Selection\n\nValue on reset: 0"]
83#[derive(Clone, Copy, Debug, PartialEq, Eq)]
84#[repr(u8)]
85pub enum Edgselselect {
86    #[doc = "0: No event output when using the resynchronized or synchronous path"]
87    NoEvtOutput = 0,
88    #[doc = "1: Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path"]
89    RisingEdge = 1,
90    #[doc = "2: Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path"]
91    FallingEdge = 2,
92    #[doc = "3: Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path"]
93    BothEdges = 3,
94}
95impl From<Edgselselect> for u8 {
96    #[inline(always)]
97    fn from(variant: Edgselselect) -> Self {
98        variant as _
99    }
100}
101impl crate::FieldSpec for Edgselselect {
102    type Ux = u8;
103}
104impl crate::IsEnum for Edgselselect {}
105#[doc = "Field `EDGSEL` reader - Edge Detection Selection"]
106pub type EdgselR = crate::FieldReader<Edgselselect>;
107impl EdgselR {
108    #[doc = "Get enumerated values variant"]
109    #[inline(always)]
110    pub const fn variant(&self) -> Edgselselect {
111        match self.bits {
112            0 => Edgselselect::NoEvtOutput,
113            1 => Edgselselect::RisingEdge,
114            2 => Edgselselect::FallingEdge,
115            3 => Edgselselect::BothEdges,
116            _ => unreachable!(),
117        }
118    }
119    #[doc = "No event output when using the resynchronized or synchronous path"]
120    #[inline(always)]
121    pub fn is_no_evt_output(&self) -> bool {
122        *self == Edgselselect::NoEvtOutput
123    }
124    #[doc = "Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path"]
125    #[inline(always)]
126    pub fn is_rising_edge(&self) -> bool {
127        *self == Edgselselect::RisingEdge
128    }
129    #[doc = "Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path"]
130    #[inline(always)]
131    pub fn is_falling_edge(&self) -> bool {
132        *self == Edgselselect::FallingEdge
133    }
134    #[doc = "Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path"]
135    #[inline(always)]
136    pub fn is_both_edges(&self) -> bool {
137        *self == Edgselselect::BothEdges
138    }
139}
140#[doc = "Field `EDGSEL` writer - Edge Detection Selection"]
141pub type EdgselW<'a, REG> = crate::FieldWriter<'a, REG, 2, Edgselselect, crate::Safe>;
142impl<'a, REG> EdgselW<'a, REG>
143where
144    REG: crate::Writable + crate::RegisterSpec,
145    REG::Ux: From<u8>,
146{
147    #[doc = "No event output when using the resynchronized or synchronous path"]
148    #[inline(always)]
149    pub fn no_evt_output(self) -> &'a mut crate::W<REG> {
150        self.variant(Edgselselect::NoEvtOutput)
151    }
152    #[doc = "Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path"]
153    #[inline(always)]
154    pub fn rising_edge(self) -> &'a mut crate::W<REG> {
155        self.variant(Edgselselect::RisingEdge)
156    }
157    #[doc = "Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path"]
158    #[inline(always)]
159    pub fn falling_edge(self) -> &'a mut crate::W<REG> {
160        self.variant(Edgselselect::FallingEdge)
161    }
162    #[doc = "Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path"]
163    #[inline(always)]
164    pub fn both_edges(self) -> &'a mut crate::W<REG> {
165        self.variant(Edgselselect::BothEdges)
166    }
167}
168#[doc = "Field `RUNSTDBY` reader - Run in standby"]
169pub type RunstdbyR = crate::BitReader;
170#[doc = "Field `RUNSTDBY` writer - Run in standby"]
171pub type RunstdbyW<'a, REG> = crate::BitWriter<'a, REG>;
172#[doc = "Field `ONDEMAND` reader - Generic Clock On Demand"]
173pub type OndemandR = crate::BitReader;
174#[doc = "Field `ONDEMAND` writer - Generic Clock On Demand"]
175pub type OndemandW<'a, REG> = crate::BitWriter<'a, REG>;
176impl R {
177    #[doc = "Bits 0:6 - Event Generator Selection"]
178    #[inline(always)]
179    pub fn evgen(&self) -> EvgenR {
180        EvgenR::new((self.bits & 0x7f) as u8)
181    }
182    #[doc = "Bits 8:9 - Path Selection"]
183    #[inline(always)]
184    pub fn path(&self) -> PathR {
185        PathR::new(((self.bits >> 8) & 3) as u8)
186    }
187    #[doc = "Bits 10:11 - Edge Detection Selection"]
188    #[inline(always)]
189    pub fn edgsel(&self) -> EdgselR {
190        EdgselR::new(((self.bits >> 10) & 3) as u8)
191    }
192    #[doc = "Bit 14 - Run in standby"]
193    #[inline(always)]
194    pub fn runstdby(&self) -> RunstdbyR {
195        RunstdbyR::new(((self.bits >> 14) & 1) != 0)
196    }
197    #[doc = "Bit 15 - Generic Clock On Demand"]
198    #[inline(always)]
199    pub fn ondemand(&self) -> OndemandR {
200        OndemandR::new(((self.bits >> 15) & 1) != 0)
201    }
202}
203impl W {
204    #[doc = "Bits 0:6 - Event Generator Selection"]
205    #[inline(always)]
206    #[must_use]
207    pub fn evgen(&mut self) -> EvgenW<ChannelSpec> {
208        EvgenW::new(self, 0)
209    }
210    #[doc = "Bits 8:9 - Path Selection"]
211    #[inline(always)]
212    #[must_use]
213    pub fn path(&mut self) -> PathW<ChannelSpec> {
214        PathW::new(self, 8)
215    }
216    #[doc = "Bits 10:11 - Edge Detection Selection"]
217    #[inline(always)]
218    #[must_use]
219    pub fn edgsel(&mut self) -> EdgselW<ChannelSpec> {
220        EdgselW::new(self, 10)
221    }
222    #[doc = "Bit 14 - Run in standby"]
223    #[inline(always)]
224    #[must_use]
225    pub fn runstdby(&mut self) -> RunstdbyW<ChannelSpec> {
226        RunstdbyW::new(self, 14)
227    }
228    #[doc = "Bit 15 - Generic Clock On Demand"]
229    #[inline(always)]
230    #[must_use]
231    pub fn ondemand(&mut self) -> OndemandW<ChannelSpec> {
232        OndemandW::new(self, 15)
233    }
234}
235#[doc = "Channel n Control\n\nYou can [`read`](crate::Reg::read) this register and get [`channel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`channel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
236pub struct ChannelSpec;
237impl crate::RegisterSpec for ChannelSpec {
238    type Ux = u32;
239}
240#[doc = "`read()` method returns [`channel::R`](R) reader structure"]
241impl crate::Readable for ChannelSpec {}
242#[doc = "`write(|w| ..)` method takes [`channel::W`](W) writer structure"]
243impl crate::Writable for ChannelSpec {
244    type Safety = crate::Unsafe;
245    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
246    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
247}
248#[doc = "`reset()` method sets CHANNEL to value 0x8000"]
249impl crate::Resettable for ChannelSpec {
250    const RESET_VALUE: u32 = 0x8000;
251}
atsamd51g/evsys/channels/channel.rs

atsamd51g/evsys/channels/
channel.rs
