atsamd51g/sdhc0/
hc2r.rs

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1#[doc = "Register `HC2R` reader"]
2pub type R = crate::R<Hc2rSpec>;
3#[doc = "Register `HC2R` writer"]
4pub type W = crate::W<Hc2rSpec>;
5#[doc = "UHS Mode Select\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7#[repr(u8)]
8pub enum Uhsmsselect {
9    #[doc = "0: SDR12"]
10    Sdr12 = 0,
11    #[doc = "1: SDR25"]
12    Sdr25 = 1,
13    #[doc = "2: SDR50"]
14    Sdr50 = 2,
15    #[doc = "3: SDR104"]
16    Sdr104 = 3,
17    #[doc = "4: DDR50"]
18    Ddr50 = 4,
19}
20impl From<Uhsmsselect> for u8 {
21    #[inline(always)]
22    fn from(variant: Uhsmsselect) -> Self {
23        variant as _
24    }
25}
26impl crate::FieldSpec for Uhsmsselect {
27    type Ux = u8;
28}
29impl crate::IsEnum for Uhsmsselect {}
30#[doc = "Field `UHSMS` reader - UHS Mode Select"]
31pub type UhsmsR = crate::FieldReader<Uhsmsselect>;
32impl UhsmsR {
33    #[doc = "Get enumerated values variant"]
34    #[inline(always)]
35    pub const fn variant(&self) -> Option<Uhsmsselect> {
36        match self.bits {
37            0 => Some(Uhsmsselect::Sdr12),
38            1 => Some(Uhsmsselect::Sdr25),
39            2 => Some(Uhsmsselect::Sdr50),
40            3 => Some(Uhsmsselect::Sdr104),
41            4 => Some(Uhsmsselect::Ddr50),
42            _ => None,
43        }
44    }
45    #[doc = "SDR12"]
46    #[inline(always)]
47    pub fn is_sdr12(&self) -> bool {
48        *self == Uhsmsselect::Sdr12
49    }
50    #[doc = "SDR25"]
51    #[inline(always)]
52    pub fn is_sdr25(&self) -> bool {
53        *self == Uhsmsselect::Sdr25
54    }
55    #[doc = "SDR50"]
56    #[inline(always)]
57    pub fn is_sdr50(&self) -> bool {
58        *self == Uhsmsselect::Sdr50
59    }
60    #[doc = "SDR104"]
61    #[inline(always)]
62    pub fn is_sdr104(&self) -> bool {
63        *self == Uhsmsselect::Sdr104
64    }
65    #[doc = "DDR50"]
66    #[inline(always)]
67    pub fn is_ddr50(&self) -> bool {
68        *self == Uhsmsselect::Ddr50
69    }
70}
71#[doc = "Field `UHSMS` writer - UHS Mode Select"]
72pub type UhsmsW<'a, REG> = crate::FieldWriter<'a, REG, 3, Uhsmsselect>;
73impl<'a, REG> UhsmsW<'a, REG>
74where
75    REG: crate::Writable + crate::RegisterSpec,
76    REG::Ux: From<u8>,
77{
78    #[doc = "SDR12"]
79    #[inline(always)]
80    pub fn sdr12(self) -> &'a mut crate::W<REG> {
81        self.variant(Uhsmsselect::Sdr12)
82    }
83    #[doc = "SDR25"]
84    #[inline(always)]
85    pub fn sdr25(self) -> &'a mut crate::W<REG> {
86        self.variant(Uhsmsselect::Sdr25)
87    }
88    #[doc = "SDR50"]
89    #[inline(always)]
90    pub fn sdr50(self) -> &'a mut crate::W<REG> {
91        self.variant(Uhsmsselect::Sdr50)
92    }
93    #[doc = "SDR104"]
94    #[inline(always)]
95    pub fn sdr104(self) -> &'a mut crate::W<REG> {
96        self.variant(Uhsmsselect::Sdr104)
97    }
98    #[doc = "DDR50"]
99    #[inline(always)]
100    pub fn ddr50(self) -> &'a mut crate::W<REG> {
101        self.variant(Uhsmsselect::Ddr50)
102    }
103}
104#[doc = "1.8V Signaling Enable\n\nValue on reset: 0"]
105#[derive(Clone, Copy, Debug, PartialEq, Eq)]
106pub enum Vs18enselect {
107    #[doc = "0: 3.3V Signaling"]
108    S33v = 0,
109    #[doc = "1: 1.8V Signaling"]
110    S18v = 1,
111}
112impl From<Vs18enselect> for bool {
113    #[inline(always)]
114    fn from(variant: Vs18enselect) -> Self {
115        variant as u8 != 0
116    }
117}
118#[doc = "Field `VS18EN` reader - 1.8V Signaling Enable"]
119pub type Vs18enR = crate::BitReader<Vs18enselect>;
120impl Vs18enR {
121    #[doc = "Get enumerated values variant"]
122    #[inline(always)]
123    pub const fn variant(&self) -> Vs18enselect {
124        match self.bits {
125            false => Vs18enselect::S33v,
126            true => Vs18enselect::S18v,
127        }
128    }
129    #[doc = "3.3V Signaling"]
130    #[inline(always)]
131    pub fn is_s33v(&self) -> bool {
132        *self == Vs18enselect::S33v
133    }
134    #[doc = "1.8V Signaling"]
135    #[inline(always)]
136    pub fn is_s18v(&self) -> bool {
137        *self == Vs18enselect::S18v
138    }
139}
140#[doc = "Field `VS18EN` writer - 1.8V Signaling Enable"]
141pub type Vs18enW<'a, REG> = crate::BitWriter<'a, REG, Vs18enselect>;
142impl<'a, REG> Vs18enW<'a, REG>
143where
144    REG: crate::Writable + crate::RegisterSpec,
145{
146    #[doc = "3.3V Signaling"]
147    #[inline(always)]
148    pub fn s33v(self) -> &'a mut crate::W<REG> {
149        self.variant(Vs18enselect::S33v)
150    }
151    #[doc = "1.8V Signaling"]
152    #[inline(always)]
153    pub fn s18v(self) -> &'a mut crate::W<REG> {
154        self.variant(Vs18enselect::S18v)
155    }
156}
157#[doc = "Driver Strength Select\n\nValue on reset: 0"]
158#[derive(Clone, Copy, Debug, PartialEq, Eq)]
159#[repr(u8)]
160pub enum Drvselselect {
161    #[doc = "0: Driver Type B is Selected (Default)"]
162    B = 0,
163    #[doc = "1: Driver Type A is Selected"]
164    A = 1,
165    #[doc = "2: Driver Type C is Selected"]
166    C = 2,
167    #[doc = "3: Driver Type D is Selected"]
168    D = 3,
169}
170impl From<Drvselselect> for u8 {
171    #[inline(always)]
172    fn from(variant: Drvselselect) -> Self {
173        variant as _
174    }
175}
176impl crate::FieldSpec for Drvselselect {
177    type Ux = u8;
178}
179impl crate::IsEnum for Drvselselect {}
180#[doc = "Field `DRVSEL` reader - Driver Strength Select"]
181pub type DrvselR = crate::FieldReader<Drvselselect>;
182impl DrvselR {
183    #[doc = "Get enumerated values variant"]
184    #[inline(always)]
185    pub const fn variant(&self) -> Drvselselect {
186        match self.bits {
187            0 => Drvselselect::B,
188            1 => Drvselselect::A,
189            2 => Drvselselect::C,
190            3 => Drvselselect::D,
191            _ => unreachable!(),
192        }
193    }
194    #[doc = "Driver Type B is Selected (Default)"]
195    #[inline(always)]
196    pub fn is_b(&self) -> bool {
197        *self == Drvselselect::B
198    }
199    #[doc = "Driver Type A is Selected"]
200    #[inline(always)]
201    pub fn is_a(&self) -> bool {
202        *self == Drvselselect::A
203    }
204    #[doc = "Driver Type C is Selected"]
205    #[inline(always)]
206    pub fn is_c(&self) -> bool {
207        *self == Drvselselect::C
208    }
209    #[doc = "Driver Type D is Selected"]
210    #[inline(always)]
211    pub fn is_d(&self) -> bool {
212        *self == Drvselselect::D
213    }
214}
215#[doc = "Field `DRVSEL` writer - Driver Strength Select"]
216pub type DrvselW<'a, REG> = crate::FieldWriter<'a, REG, 2, Drvselselect, crate::Safe>;
217impl<'a, REG> DrvselW<'a, REG>
218where
219    REG: crate::Writable + crate::RegisterSpec,
220    REG::Ux: From<u8>,
221{
222    #[doc = "Driver Type B is Selected (Default)"]
223    #[inline(always)]
224    pub fn b(self) -> &'a mut crate::W<REG> {
225        self.variant(Drvselselect::B)
226    }
227    #[doc = "Driver Type A is Selected"]
228    #[inline(always)]
229    pub fn a(self) -> &'a mut crate::W<REG> {
230        self.variant(Drvselselect::A)
231    }
232    #[doc = "Driver Type C is Selected"]
233    #[inline(always)]
234    pub fn c(self) -> &'a mut crate::W<REG> {
235        self.variant(Drvselselect::C)
236    }
237    #[doc = "Driver Type D is Selected"]
238    #[inline(always)]
239    pub fn d(self) -> &'a mut crate::W<REG> {
240        self.variant(Drvselselect::D)
241    }
242}
243#[doc = "Execute Tuning\n\nValue on reset: 0"]
244#[derive(Clone, Copy, Debug, PartialEq, Eq)]
245pub enum Extunselect {
246    #[doc = "0: Not Tuned or Tuning Completed"]
247    No = 0,
248    #[doc = "1: Execute Tuning"]
249    Requested = 1,
250}
251impl From<Extunselect> for bool {
252    #[inline(always)]
253    fn from(variant: Extunselect) -> Self {
254        variant as u8 != 0
255    }
256}
257#[doc = "Field `EXTUN` reader - Execute Tuning"]
258pub type ExtunR = crate::BitReader<Extunselect>;
259impl ExtunR {
260    #[doc = "Get enumerated values variant"]
261    #[inline(always)]
262    pub const fn variant(&self) -> Extunselect {
263        match self.bits {
264            false => Extunselect::No,
265            true => Extunselect::Requested,
266        }
267    }
268    #[doc = "Not Tuned or Tuning Completed"]
269    #[inline(always)]
270    pub fn is_no(&self) -> bool {
271        *self == Extunselect::No
272    }
273    #[doc = "Execute Tuning"]
274    #[inline(always)]
275    pub fn is_requested(&self) -> bool {
276        *self == Extunselect::Requested
277    }
278}
279#[doc = "Field `EXTUN` writer - Execute Tuning"]
280pub type ExtunW<'a, REG> = crate::BitWriter<'a, REG, Extunselect>;
281impl<'a, REG> ExtunW<'a, REG>
282where
283    REG: crate::Writable + crate::RegisterSpec,
284{
285    #[doc = "Not Tuned or Tuning Completed"]
286    #[inline(always)]
287    pub fn no(self) -> &'a mut crate::W<REG> {
288        self.variant(Extunselect::No)
289    }
290    #[doc = "Execute Tuning"]
291    #[inline(always)]
292    pub fn requested(self) -> &'a mut crate::W<REG> {
293        self.variant(Extunselect::Requested)
294    }
295}
296#[doc = "Sampling Clock Select\n\nValue on reset: 0"]
297#[derive(Clone, Copy, Debug, PartialEq, Eq)]
298pub enum Slckselselect {
299    #[doc = "0: Fixed clock is used to sample data"]
300    Fixed = 0,
301    #[doc = "1: Tuned clock is used to sample data"]
302    Tuned = 1,
303}
304impl From<Slckselselect> for bool {
305    #[inline(always)]
306    fn from(variant: Slckselselect) -> Self {
307        variant as u8 != 0
308    }
309}
310#[doc = "Field `SLCKSEL` reader - Sampling Clock Select"]
311pub type SlckselR = crate::BitReader<Slckselselect>;
312impl SlckselR {
313    #[doc = "Get enumerated values variant"]
314    #[inline(always)]
315    pub const fn variant(&self) -> Slckselselect {
316        match self.bits {
317            false => Slckselselect::Fixed,
318            true => Slckselselect::Tuned,
319        }
320    }
321    #[doc = "Fixed clock is used to sample data"]
322    #[inline(always)]
323    pub fn is_fixed(&self) -> bool {
324        *self == Slckselselect::Fixed
325    }
326    #[doc = "Tuned clock is used to sample data"]
327    #[inline(always)]
328    pub fn is_tuned(&self) -> bool {
329        *self == Slckselselect::Tuned
330    }
331}
332#[doc = "Field `SLCKSEL` writer - Sampling Clock Select"]
333pub type SlckselW<'a, REG> = crate::BitWriter<'a, REG, Slckselselect>;
334impl<'a, REG> SlckselW<'a, REG>
335where
336    REG: crate::Writable + crate::RegisterSpec,
337{
338    #[doc = "Fixed clock is used to sample data"]
339    #[inline(always)]
340    pub fn fixed(self) -> &'a mut crate::W<REG> {
341        self.variant(Slckselselect::Fixed)
342    }
343    #[doc = "Tuned clock is used to sample data"]
344    #[inline(always)]
345    pub fn tuned(self) -> &'a mut crate::W<REG> {
346        self.variant(Slckselselect::Tuned)
347    }
348}
349#[doc = "Asynchronous Interrupt Enable\n\nValue on reset: 0"]
350#[derive(Clone, Copy, Debug, PartialEq, Eq)]
351pub enum Asintenselect {
352    #[doc = "0: Disabled"]
353    Disabled = 0,
354    #[doc = "1: Enabled"]
355    Enabled = 1,
356}
357impl From<Asintenselect> for bool {
358    #[inline(always)]
359    fn from(variant: Asintenselect) -> Self {
360        variant as u8 != 0
361    }
362}
363#[doc = "Field `ASINTEN` reader - Asynchronous Interrupt Enable"]
364pub type AsintenR = crate::BitReader<Asintenselect>;
365impl AsintenR {
366    #[doc = "Get enumerated values variant"]
367    #[inline(always)]
368    pub const fn variant(&self) -> Asintenselect {
369        match self.bits {
370            false => Asintenselect::Disabled,
371            true => Asintenselect::Enabled,
372        }
373    }
374    #[doc = "Disabled"]
375    #[inline(always)]
376    pub fn is_disabled(&self) -> bool {
377        *self == Asintenselect::Disabled
378    }
379    #[doc = "Enabled"]
380    #[inline(always)]
381    pub fn is_enabled(&self) -> bool {
382        *self == Asintenselect::Enabled
383    }
384}
385#[doc = "Field `ASINTEN` writer - Asynchronous Interrupt Enable"]
386pub type AsintenW<'a, REG> = crate::BitWriter<'a, REG, Asintenselect>;
387impl<'a, REG> AsintenW<'a, REG>
388where
389    REG: crate::Writable + crate::RegisterSpec,
390{
391    #[doc = "Disabled"]
392    #[inline(always)]
393    pub fn disabled(self) -> &'a mut crate::W<REG> {
394        self.variant(Asintenselect::Disabled)
395    }
396    #[doc = "Enabled"]
397    #[inline(always)]
398    pub fn enabled(self) -> &'a mut crate::W<REG> {
399        self.variant(Asintenselect::Enabled)
400    }
401}
402#[doc = "Preset Value Enable\n\nValue on reset: 0"]
403#[derive(Clone, Copy, Debug, PartialEq, Eq)]
404pub enum Pvalenselect {
405    #[doc = "0: SDCLK and Driver Strength are controlled by Host Controller"]
406    Host = 0,
407    #[doc = "1: Automatic Selection by Preset Value is Enabled"]
408    Auto = 1,
409}
410impl From<Pvalenselect> for bool {
411    #[inline(always)]
412    fn from(variant: Pvalenselect) -> Self {
413        variant as u8 != 0
414    }
415}
416#[doc = "Field `PVALEN` reader - Preset Value Enable"]
417pub type PvalenR = crate::BitReader<Pvalenselect>;
418impl PvalenR {
419    #[doc = "Get enumerated values variant"]
420    #[inline(always)]
421    pub const fn variant(&self) -> Pvalenselect {
422        match self.bits {
423            false => Pvalenselect::Host,
424            true => Pvalenselect::Auto,
425        }
426    }
427    #[doc = "SDCLK and Driver Strength are controlled by Host Controller"]
428    #[inline(always)]
429    pub fn is_host(&self) -> bool {
430        *self == Pvalenselect::Host
431    }
432    #[doc = "Automatic Selection by Preset Value is Enabled"]
433    #[inline(always)]
434    pub fn is_auto(&self) -> bool {
435        *self == Pvalenselect::Auto
436    }
437}
438#[doc = "Field `PVALEN` writer - Preset Value Enable"]
439pub type PvalenW<'a, REG> = crate::BitWriter<'a, REG, Pvalenselect>;
440impl<'a, REG> PvalenW<'a, REG>
441where
442    REG: crate::Writable + crate::RegisterSpec,
443{
444    #[doc = "SDCLK and Driver Strength are controlled by Host Controller"]
445    #[inline(always)]
446    pub fn host(self) -> &'a mut crate::W<REG> {
447        self.variant(Pvalenselect::Host)
448    }
449    #[doc = "Automatic Selection by Preset Value is Enabled"]
450    #[inline(always)]
451    pub fn auto(self) -> &'a mut crate::W<REG> {
452        self.variant(Pvalenselect::Auto)
453    }
454}
455impl R {
456    #[doc = "Bits 0:2 - UHS Mode Select"]
457    #[inline(always)]
458    pub fn uhsms(&self) -> UhsmsR {
459        UhsmsR::new((self.bits & 7) as u8)
460    }
461    #[doc = "Bit 3 - 1.8V Signaling Enable"]
462    #[inline(always)]
463    pub fn vs18en(&self) -> Vs18enR {
464        Vs18enR::new(((self.bits >> 3) & 1) != 0)
465    }
466    #[doc = "Bits 4:5 - Driver Strength Select"]
467    #[inline(always)]
468    pub fn drvsel(&self) -> DrvselR {
469        DrvselR::new(((self.bits >> 4) & 3) as u8)
470    }
471    #[doc = "Bit 6 - Execute Tuning"]
472    #[inline(always)]
473    pub fn extun(&self) -> ExtunR {
474        ExtunR::new(((self.bits >> 6) & 1) != 0)
475    }
476    #[doc = "Bit 7 - Sampling Clock Select"]
477    #[inline(always)]
478    pub fn slcksel(&self) -> SlckselR {
479        SlckselR::new(((self.bits >> 7) & 1) != 0)
480    }
481    #[doc = "Bit 14 - Asynchronous Interrupt Enable"]
482    #[inline(always)]
483    pub fn asinten(&self) -> AsintenR {
484        AsintenR::new(((self.bits >> 14) & 1) != 0)
485    }
486    #[doc = "Bit 15 - Preset Value Enable"]
487    #[inline(always)]
488    pub fn pvalen(&self) -> PvalenR {
489        PvalenR::new(((self.bits >> 15) & 1) != 0)
490    }
491}
492impl W {
493    #[doc = "Bits 0:2 - UHS Mode Select"]
494    #[inline(always)]
495    #[must_use]
496    pub fn uhsms(&mut self) -> UhsmsW<Hc2rSpec> {
497        UhsmsW::new(self, 0)
498    }
499    #[doc = "Bit 3 - 1.8V Signaling Enable"]
500    #[inline(always)]
501    #[must_use]
502    pub fn vs18en(&mut self) -> Vs18enW<Hc2rSpec> {
503        Vs18enW::new(self, 3)
504    }
505    #[doc = "Bits 4:5 - Driver Strength Select"]
506    #[inline(always)]
507    #[must_use]
508    pub fn drvsel(&mut self) -> DrvselW<Hc2rSpec> {
509        DrvselW::new(self, 4)
510    }
511    #[doc = "Bit 6 - Execute Tuning"]
512    #[inline(always)]
513    #[must_use]
514    pub fn extun(&mut self) -> ExtunW<Hc2rSpec> {
515        ExtunW::new(self, 6)
516    }
517    #[doc = "Bit 7 - Sampling Clock Select"]
518    #[inline(always)]
519    #[must_use]
520    pub fn slcksel(&mut self) -> SlckselW<Hc2rSpec> {
521        SlckselW::new(self, 7)
522    }
523    #[doc = "Bit 14 - Asynchronous Interrupt Enable"]
524    #[inline(always)]
525    #[must_use]
526    pub fn asinten(&mut self) -> AsintenW<Hc2rSpec> {
527        AsintenW::new(self, 14)
528    }
529    #[doc = "Bit 15 - Preset Value Enable"]
530    #[inline(always)]
531    #[must_use]
532    pub fn pvalen(&mut self) -> PvalenW<Hc2rSpec> {
533        PvalenW::new(self, 15)
534    }
535}
536#[doc = "Host Control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`hc2r::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hc2r::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
537pub struct Hc2rSpec;
538impl crate::RegisterSpec for Hc2rSpec {
539    type Ux = u16;
540}
541#[doc = "`read()` method returns [`hc2r::R`](R) reader structure"]
542impl crate::Readable for Hc2rSpec {}
543#[doc = "`write(|w| ..)` method takes [`hc2r::W`](W) writer structure"]
544impl crate::Writable for Hc2rSpec {
545    type Safety = crate::Unsafe;
546    const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
547    const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
548}
549#[doc = "`reset()` method sets HC2R to value 0"]
550impl crate::Resettable for Hc2rSpec {
551    const RESET_VALUE: u16 = 0;
552}
atsamd51g/sdhc0/hc2r.rs

atsamd51g/sdhc0/
hc2r.rs
