atsamd51g/qspi/
intenset.rs

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1#[doc = "Register `INTENSET` reader"]
2pub type R = crate::R<IntensetSpec>;
3#[doc = "Register `INTENSET` writer"]
4pub type W = crate::W<IntensetSpec>;
5#[doc = "Field `RXC` reader - Receive Data Register Full Interrupt Enable"]
6pub type RxcR = crate::BitReader;
7#[doc = "Field `RXC` writer - Receive Data Register Full Interrupt Enable"]
8pub type RxcW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `DRE` reader - Transmit Data Register Empty Interrupt Enable"]
10pub type DreR = crate::BitReader;
11#[doc = "Field `DRE` writer - Transmit Data Register Empty Interrupt Enable"]
12pub type DreW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `TXC` reader - Transmission Complete Interrupt Enable"]
14pub type TxcR = crate::BitReader;
15#[doc = "Field `TXC` writer - Transmission Complete Interrupt Enable"]
16pub type TxcW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `ERROR` reader - Overrun Error Interrupt Enable"]
18pub type ErrorR = crate::BitReader;
19#[doc = "Field `ERROR` writer - Overrun Error Interrupt Enable"]
20pub type ErrorW<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `CSRISE` reader - Chip Select Rise Interrupt Enable"]
22pub type CsriseR = crate::BitReader;
23#[doc = "Field `CSRISE` writer - Chip Select Rise Interrupt Enable"]
24pub type CsriseW<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `INSTREND` reader - Instruction End Interrupt Enable"]
26pub type InstrendR = crate::BitReader;
27#[doc = "Field `INSTREND` writer - Instruction End Interrupt Enable"]
28pub type InstrendW<'a, REG> = crate::BitWriter<'a, REG>;
29impl R {
30    #[doc = "Bit 0 - Receive Data Register Full Interrupt Enable"]
31    #[inline(always)]
32    pub fn rxc(&self) -> RxcR {
33        RxcR::new((self.bits & 1) != 0)
34    }
35    #[doc = "Bit 1 - Transmit Data Register Empty Interrupt Enable"]
36    #[inline(always)]
37    pub fn dre(&self) -> DreR {
38        DreR::new(((self.bits >> 1) & 1) != 0)
39    }
40    #[doc = "Bit 2 - Transmission Complete Interrupt Enable"]
41    #[inline(always)]
42    pub fn txc(&self) -> TxcR {
43        TxcR::new(((self.bits >> 2) & 1) != 0)
44    }
45    #[doc = "Bit 3 - Overrun Error Interrupt Enable"]
46    #[inline(always)]
47    pub fn error(&self) -> ErrorR {
48        ErrorR::new(((self.bits >> 3) & 1) != 0)
49    }
50    #[doc = "Bit 8 - Chip Select Rise Interrupt Enable"]
51    #[inline(always)]
52    pub fn csrise(&self) -> CsriseR {
53        CsriseR::new(((self.bits >> 8) & 1) != 0)
54    }
55    #[doc = "Bit 10 - Instruction End Interrupt Enable"]
56    #[inline(always)]
57    pub fn instrend(&self) -> InstrendR {
58        InstrendR::new(((self.bits >> 10) & 1) != 0)
59    }
60}
61impl W {
62    #[doc = "Bit 0 - Receive Data Register Full Interrupt Enable"]
63    #[inline(always)]
64    #[must_use]
65    pub fn rxc(&mut self) -> RxcW<IntensetSpec> {
66        RxcW::new(self, 0)
67    }
68    #[doc = "Bit 1 - Transmit Data Register Empty Interrupt Enable"]
69    #[inline(always)]
70    #[must_use]
71    pub fn dre(&mut self) -> DreW<IntensetSpec> {
72        DreW::new(self, 1)
73    }
74    #[doc = "Bit 2 - Transmission Complete Interrupt Enable"]
75    #[inline(always)]
76    #[must_use]
77    pub fn txc(&mut self) -> TxcW<IntensetSpec> {
78        TxcW::new(self, 2)
79    }
80    #[doc = "Bit 3 - Overrun Error Interrupt Enable"]
81    #[inline(always)]
82    #[must_use]
83    pub fn error(&mut self) -> ErrorW<IntensetSpec> {
84        ErrorW::new(self, 3)
85    }
86    #[doc = "Bit 8 - Chip Select Rise Interrupt Enable"]
87    #[inline(always)]
88    #[must_use]
89    pub fn csrise(&mut self) -> CsriseW<IntensetSpec> {
90        CsriseW::new(self, 8)
91    }
92    #[doc = "Bit 10 - Instruction End Interrupt Enable"]
93    #[inline(always)]
94    #[must_use]
95    pub fn instrend(&mut self) -> InstrendW<IntensetSpec> {
96        InstrendW::new(self, 10)
97    }
98}
99#[doc = "Interrupt Enable Set\n\nYou can [`read`](crate::Reg::read) this register and get [`intenset::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intenset::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
100pub struct IntensetSpec;
101impl crate::RegisterSpec for IntensetSpec {
102    type Ux = u32;
103}
104#[doc = "`read()` method returns [`intenset::R`](R) reader structure"]
105impl crate::Readable for IntensetSpec {}
106#[doc = "`write(|w| ..)` method takes [`intenset::W`](W) writer structure"]
107impl crate::Writable for IntensetSpec {
108    type Safety = crate::Unsafe;
109    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
110    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
111}
112#[doc = "`reset()` method sets INTENSET to value 0"]
113impl crate::Resettable for IntensetSpec {
114    const RESET_VALUE: u32 = 0;
115}
atsamd51g/qspi/intenset.rs

atsamd51g/qspi/
intenset.rs
