atsamd51g/oscctrl/
dfllsync.rs

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1#[doc = "Register `DFLLSYNC` reader"]
2pub type R = crate::R<DfllsyncSpec>;
3#[doc = "Register `DFLLSYNC` writer"]
4pub type W = crate::W<DfllsyncSpec>;
5#[doc = "Field `ENABLE` reader - ENABLE Synchronization Busy"]
6pub type EnableR = crate::BitReader;
7#[doc = "Field `ENABLE` writer - ENABLE Synchronization Busy"]
8pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `DFLLCTRLB` reader - DFLLCTRLB Synchronization Busy"]
10pub type DfllctrlbR = crate::BitReader;
11#[doc = "Field `DFLLCTRLB` writer - DFLLCTRLB Synchronization Busy"]
12pub type DfllctrlbW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `DFLLVAL` reader - DFLLVAL Synchronization Busy"]
14pub type DfllvalR = crate::BitReader;
15#[doc = "Field `DFLLVAL` writer - DFLLVAL Synchronization Busy"]
16pub type DfllvalW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `DFLLMUL` reader - DFLLMUL Synchronization Busy"]
18pub type DfllmulR = crate::BitReader;
19#[doc = "Field `DFLLMUL` writer - DFLLMUL Synchronization Busy"]
20pub type DfllmulW<'a, REG> = crate::BitWriter<'a, REG>;
21impl R {
22    #[doc = "Bit 1 - ENABLE Synchronization Busy"]
23    #[inline(always)]
24    pub fn enable(&self) -> EnableR {
25        EnableR::new(((self.bits >> 1) & 1) != 0)
26    }
27    #[doc = "Bit 2 - DFLLCTRLB Synchronization Busy"]
28    #[inline(always)]
29    pub fn dfllctrlb(&self) -> DfllctrlbR {
30        DfllctrlbR::new(((self.bits >> 2) & 1) != 0)
31    }
32    #[doc = "Bit 3 - DFLLVAL Synchronization Busy"]
33    #[inline(always)]
34    pub fn dfllval(&self) -> DfllvalR {
35        DfllvalR::new(((self.bits >> 3) & 1) != 0)
36    }
37    #[doc = "Bit 4 - DFLLMUL Synchronization Busy"]
38    #[inline(always)]
39    pub fn dfllmul(&self) -> DfllmulR {
40        DfllmulR::new(((self.bits >> 4) & 1) != 0)
41    }
42}
43impl W {
44    #[doc = "Bit 1 - ENABLE Synchronization Busy"]
45    #[inline(always)]
46    #[must_use]
47    pub fn enable(&mut self) -> EnableW<DfllsyncSpec> {
48        EnableW::new(self, 1)
49    }
50    #[doc = "Bit 2 - DFLLCTRLB Synchronization Busy"]
51    #[inline(always)]
52    #[must_use]
53    pub fn dfllctrlb(&mut self) -> DfllctrlbW<DfllsyncSpec> {
54        DfllctrlbW::new(self, 2)
55    }
56    #[doc = "Bit 3 - DFLLVAL Synchronization Busy"]
57    #[inline(always)]
58    #[must_use]
59    pub fn dfllval(&mut self) -> DfllvalW<DfllsyncSpec> {
60        DfllvalW::new(self, 3)
61    }
62    #[doc = "Bit 4 - DFLLMUL Synchronization Busy"]
63    #[inline(always)]
64    #[must_use]
65    pub fn dfllmul(&mut self) -> DfllmulW<DfllsyncSpec> {
66        DfllmulW::new(self, 4)
67    }
68}
69#[doc = "DFLL48M Synchronization\n\nYou can [`read`](crate::Reg::read) this register and get [`dfllsync::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfllsync::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
70pub struct DfllsyncSpec;
71impl crate::RegisterSpec for DfllsyncSpec {
72    type Ux = u8;
73}
74#[doc = "`read()` method returns [`dfllsync::R`](R) reader structure"]
75impl crate::Readable for DfllsyncSpec {}
76#[doc = "`write(|w| ..)` method takes [`dfllsync::W`](W) writer structure"]
77impl crate::Writable for DfllsyncSpec {
78    type Safety = crate::Unsafe;
79    const ZERO_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
80    const ONE_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
81}
82#[doc = "`reset()` method sets DFLLSYNC to value 0"]
83impl crate::Resettable for DfllsyncSpec {
84    const RESET_VALUE: u8 = 0;
85}
atsamd51g/oscctrl/dfllsync.rs

atsamd51g/oscctrl/
dfllsync.rs
