1#[doc = "Register `PRICTRL0` reader"]
2pub type R = crate::R<Prictrl0Spec>;
3#[doc = "Register `PRICTRL0` writer"]
4pub type W = crate::W<Prictrl0Spec>;
5#[doc = "Field `LVLPRI0` reader - Level 0 Channel Priority Number"]
6pub type Lvlpri0R = crate::FieldReader;
7#[doc = "Field `LVLPRI0` writer - Level 0 Channel Priority Number"]
8pub type Lvlpri0W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
9#[doc = "Level 0 Quality of Service\n\nValue on reset: 2"]
10#[derive(Clone, Copy, Debug, PartialEq, Eq)]
11#[repr(u8)]
12pub enum Qos0select {
13 #[doc = "0: Regular delivery"]
14 Regular = 0,
15 #[doc = "1: Bandwidth shortage"]
16 Shortage = 1,
17 #[doc = "2: Latency sensitive"]
18 Sensitive = 2,
19 #[doc = "3: Latency critical"]
20 Critical = 3,
21}
22impl From<Qos0select> for u8 {
23 #[inline(always)]
24 fn from(variant: Qos0select) -> Self {
25 variant as _
26 }
27}
28impl crate::FieldSpec for Qos0select {
29 type Ux = u8;
30}
31impl crate::IsEnum for Qos0select {}
32#[doc = "Field `QOS0` reader - Level 0 Quality of Service"]
33pub type Qos0R = crate::FieldReader<Qos0select>;
34impl Qos0R {
35 #[doc = "Get enumerated values variant"]
36 #[inline(always)]
37 pub const fn variant(&self) -> Qos0select {
38 match self.bits {
39 0 => Qos0select::Regular,
40 1 => Qos0select::Shortage,
41 2 => Qos0select::Sensitive,
42 3 => Qos0select::Critical,
43 _ => unreachable!(),
44 }
45 }
46 #[doc = "Regular delivery"]
47 #[inline(always)]
48 pub fn is_regular(&self) -> bool {
49 *self == Qos0select::Regular
50 }
51 #[doc = "Bandwidth shortage"]
52 #[inline(always)]
53 pub fn is_shortage(&self) -> bool {
54 *self == Qos0select::Shortage
55 }
56 #[doc = "Latency sensitive"]
57 #[inline(always)]
58 pub fn is_sensitive(&self) -> bool {
59 *self == Qos0select::Sensitive
60 }
61 #[doc = "Latency critical"]
62 #[inline(always)]
63 pub fn is_critical(&self) -> bool {
64 *self == Qos0select::Critical
65 }
66}
67#[doc = "Field `QOS0` writer - Level 0 Quality of Service"]
68pub type Qos0W<'a, REG> = crate::FieldWriter<'a, REG, 2, Qos0select, crate::Safe>;
69impl<'a, REG> Qos0W<'a, REG>
70where
71 REG: crate::Writable + crate::RegisterSpec,
72 REG::Ux: From<u8>,
73{
74 #[doc = "Regular delivery"]
75 #[inline(always)]
76 pub fn regular(self) -> &'a mut crate::W<REG> {
77 self.variant(Qos0select::Regular)
78 }
79 #[doc = "Bandwidth shortage"]
80 #[inline(always)]
81 pub fn shortage(self) -> &'a mut crate::W<REG> {
82 self.variant(Qos0select::Shortage)
83 }
84 #[doc = "Latency sensitive"]
85 #[inline(always)]
86 pub fn sensitive(self) -> &'a mut crate::W<REG> {
87 self.variant(Qos0select::Sensitive)
88 }
89 #[doc = "Latency critical"]
90 #[inline(always)]
91 pub fn critical(self) -> &'a mut crate::W<REG> {
92 self.variant(Qos0select::Critical)
93 }
94}
95#[doc = "Field `RRLVLEN0` reader - Level 0 Round-Robin Scheduling Enable"]
96pub type Rrlvlen0R = crate::BitReader;
97#[doc = "Field `RRLVLEN0` writer - Level 0 Round-Robin Scheduling Enable"]
98pub type Rrlvlen0W<'a, REG> = crate::BitWriter<'a, REG>;
99#[doc = "Field `LVLPRI1` reader - Level 1 Channel Priority Number"]
100pub type Lvlpri1R = crate::FieldReader;
101#[doc = "Field `LVLPRI1` writer - Level 1 Channel Priority Number"]
102pub type Lvlpri1W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
103#[doc = "Level 1 Quality of Service\n\nValue on reset: 2"]
104#[derive(Clone, Copy, Debug, PartialEq, Eq)]
105#[repr(u8)]
106pub enum Qos1select {
107 #[doc = "0: Regular delivery"]
108 Regular = 0,
109 #[doc = "1: Bandwidth shortage"]
110 Shortage = 1,
111 #[doc = "2: Latency sensitive"]
112 Sensitive = 2,
113 #[doc = "3: Latency critical"]
114 Critical = 3,
115}
116impl From<Qos1select> for u8 {
117 #[inline(always)]
118 fn from(variant: Qos1select) -> Self {
119 variant as _
120 }
121}
122impl crate::FieldSpec for Qos1select {
123 type Ux = u8;
124}
125impl crate::IsEnum for Qos1select {}
126#[doc = "Field `QOS1` reader - Level 1 Quality of Service"]
127pub type Qos1R = crate::FieldReader<Qos1select>;
128impl Qos1R {
129 #[doc = "Get enumerated values variant"]
130 #[inline(always)]
131 pub const fn variant(&self) -> Qos1select {
132 match self.bits {
133 0 => Qos1select::Regular,
134 1 => Qos1select::Shortage,
135 2 => Qos1select::Sensitive,
136 3 => Qos1select::Critical,
137 _ => unreachable!(),
138 }
139 }
140 #[doc = "Regular delivery"]
141 #[inline(always)]
142 pub fn is_regular(&self) -> bool {
143 *self == Qos1select::Regular
144 }
145 #[doc = "Bandwidth shortage"]
146 #[inline(always)]
147 pub fn is_shortage(&self) -> bool {
148 *self == Qos1select::Shortage
149 }
150 #[doc = "Latency sensitive"]
151 #[inline(always)]
152 pub fn is_sensitive(&self) -> bool {
153 *self == Qos1select::Sensitive
154 }
155 #[doc = "Latency critical"]
156 #[inline(always)]
157 pub fn is_critical(&self) -> bool {
158 *self == Qos1select::Critical
159 }
160}
161#[doc = "Field `QOS1` writer - Level 1 Quality of Service"]
162pub type Qos1W<'a, REG> = crate::FieldWriter<'a, REG, 2, Qos1select, crate::Safe>;
163impl<'a, REG> Qos1W<'a, REG>
164where
165 REG: crate::Writable + crate::RegisterSpec,
166 REG::Ux: From<u8>,
167{
168 #[doc = "Regular delivery"]
169 #[inline(always)]
170 pub fn regular(self) -> &'a mut crate::W<REG> {
171 self.variant(Qos1select::Regular)
172 }
173 #[doc = "Bandwidth shortage"]
174 #[inline(always)]
175 pub fn shortage(self) -> &'a mut crate::W<REG> {
176 self.variant(Qos1select::Shortage)
177 }
178 #[doc = "Latency sensitive"]
179 #[inline(always)]
180 pub fn sensitive(self) -> &'a mut crate::W<REG> {
181 self.variant(Qos1select::Sensitive)
182 }
183 #[doc = "Latency critical"]
184 #[inline(always)]
185 pub fn critical(self) -> &'a mut crate::W<REG> {
186 self.variant(Qos1select::Critical)
187 }
188}
189#[doc = "Field `RRLVLEN1` reader - Level 1 Round-Robin Scheduling Enable"]
190pub type Rrlvlen1R = crate::BitReader;
191#[doc = "Field `RRLVLEN1` writer - Level 1 Round-Robin Scheduling Enable"]
192pub type Rrlvlen1W<'a, REG> = crate::BitWriter<'a, REG>;
193#[doc = "Field `LVLPRI2` reader - Level 2 Channel Priority Number"]
194pub type Lvlpri2R = crate::FieldReader;
195#[doc = "Field `LVLPRI2` writer - Level 2 Channel Priority Number"]
196pub type Lvlpri2W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
197#[doc = "Level 2 Quality of Service\n\nValue on reset: 2"]
198#[derive(Clone, Copy, Debug, PartialEq, Eq)]
199#[repr(u8)]
200pub enum Qos2select {
201 #[doc = "0: Regular delivery"]
202 Regular = 0,
203 #[doc = "1: Bandwidth shortage"]
204 Shortage = 1,
205 #[doc = "2: Latency sensitive"]
206 Sensitive = 2,
207 #[doc = "3: Latency critical"]
208 Critical = 3,
209}
210impl From<Qos2select> for u8 {
211 #[inline(always)]
212 fn from(variant: Qos2select) -> Self {
213 variant as _
214 }
215}
216impl crate::FieldSpec for Qos2select {
217 type Ux = u8;
218}
219impl crate::IsEnum for Qos2select {}
220#[doc = "Field `QOS2` reader - Level 2 Quality of Service"]
221pub type Qos2R = crate::FieldReader<Qos2select>;
222impl Qos2R {
223 #[doc = "Get enumerated values variant"]
224 #[inline(always)]
225 pub const fn variant(&self) -> Qos2select {
226 match self.bits {
227 0 => Qos2select::Regular,
228 1 => Qos2select::Shortage,
229 2 => Qos2select::Sensitive,
230 3 => Qos2select::Critical,
231 _ => unreachable!(),
232 }
233 }
234 #[doc = "Regular delivery"]
235 #[inline(always)]
236 pub fn is_regular(&self) -> bool {
237 *self == Qos2select::Regular
238 }
239 #[doc = "Bandwidth shortage"]
240 #[inline(always)]
241 pub fn is_shortage(&self) -> bool {
242 *self == Qos2select::Shortage
243 }
244 #[doc = "Latency sensitive"]
245 #[inline(always)]
246 pub fn is_sensitive(&self) -> bool {
247 *self == Qos2select::Sensitive
248 }
249 #[doc = "Latency critical"]
250 #[inline(always)]
251 pub fn is_critical(&self) -> bool {
252 *self == Qos2select::Critical
253 }
254}
255#[doc = "Field `QOS2` writer - Level 2 Quality of Service"]
256pub type Qos2W<'a, REG> = crate::FieldWriter<'a, REG, 2, Qos2select, crate::Safe>;
257impl<'a, REG> Qos2W<'a, REG>
258where
259 REG: crate::Writable + crate::RegisterSpec,
260 REG::Ux: From<u8>,
261{
262 #[doc = "Regular delivery"]
263 #[inline(always)]
264 pub fn regular(self) -> &'a mut crate::W<REG> {
265 self.variant(Qos2select::Regular)
266 }
267 #[doc = "Bandwidth shortage"]
268 #[inline(always)]
269 pub fn shortage(self) -> &'a mut crate::W<REG> {
270 self.variant(Qos2select::Shortage)
271 }
272 #[doc = "Latency sensitive"]
273 #[inline(always)]
274 pub fn sensitive(self) -> &'a mut crate::W<REG> {
275 self.variant(Qos2select::Sensitive)
276 }
277 #[doc = "Latency critical"]
278 #[inline(always)]
279 pub fn critical(self) -> &'a mut crate::W<REG> {
280 self.variant(Qos2select::Critical)
281 }
282}
283#[doc = "Field `RRLVLEN2` reader - Level 2 Round-Robin Scheduling Enable"]
284pub type Rrlvlen2R = crate::BitReader;
285#[doc = "Field `RRLVLEN2` writer - Level 2 Round-Robin Scheduling Enable"]
286pub type Rrlvlen2W<'a, REG> = crate::BitWriter<'a, REG>;
287#[doc = "Field `LVLPRI3` reader - Level 3 Channel Priority Number"]
288pub type Lvlpri3R = crate::FieldReader;
289#[doc = "Field `LVLPRI3` writer - Level 3 Channel Priority Number"]
290pub type Lvlpri3W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
291#[doc = "Level 3 Quality of Service\n\nValue on reset: 2"]
292#[derive(Clone, Copy, Debug, PartialEq, Eq)]
293#[repr(u8)]
294pub enum Qos3select {
295 #[doc = "0: Regular delivery"]
296 Regular = 0,
297 #[doc = "1: Bandwidth shortage"]
298 Shortage = 1,
299 #[doc = "2: Latency sensitive"]
300 Sensitive = 2,
301 #[doc = "3: Latency critical"]
302 Critical = 3,
303}
304impl From<Qos3select> for u8 {
305 #[inline(always)]
306 fn from(variant: Qos3select) -> Self {
307 variant as _
308 }
309}
310impl crate::FieldSpec for Qos3select {
311 type Ux = u8;
312}
313impl crate::IsEnum for Qos3select {}
314#[doc = "Field `QOS3` reader - Level 3 Quality of Service"]
315pub type Qos3R = crate::FieldReader<Qos3select>;
316impl Qos3R {
317 #[doc = "Get enumerated values variant"]
318 #[inline(always)]
319 pub const fn variant(&self) -> Qos3select {
320 match self.bits {
321 0 => Qos3select::Regular,
322 1 => Qos3select::Shortage,
323 2 => Qos3select::Sensitive,
324 3 => Qos3select::Critical,
325 _ => unreachable!(),
326 }
327 }
328 #[doc = "Regular delivery"]
329 #[inline(always)]
330 pub fn is_regular(&self) -> bool {
331 *self == Qos3select::Regular
332 }
333 #[doc = "Bandwidth shortage"]
334 #[inline(always)]
335 pub fn is_shortage(&self) -> bool {
336 *self == Qos3select::Shortage
337 }
338 #[doc = "Latency sensitive"]
339 #[inline(always)]
340 pub fn is_sensitive(&self) -> bool {
341 *self == Qos3select::Sensitive
342 }
343 #[doc = "Latency critical"]
344 #[inline(always)]
345 pub fn is_critical(&self) -> bool {
346 *self == Qos3select::Critical
347 }
348}
349#[doc = "Field `QOS3` writer - Level 3 Quality of Service"]
350pub type Qos3W<'a, REG> = crate::FieldWriter<'a, REG, 2, Qos3select, crate::Safe>;
351impl<'a, REG> Qos3W<'a, REG>
352where
353 REG: crate::Writable + crate::RegisterSpec,
354 REG::Ux: From<u8>,
355{
356 #[doc = "Regular delivery"]
357 #[inline(always)]
358 pub fn regular(self) -> &'a mut crate::W<REG> {
359 self.variant(Qos3select::Regular)
360 }
361 #[doc = "Bandwidth shortage"]
362 #[inline(always)]
363 pub fn shortage(self) -> &'a mut crate::W<REG> {
364 self.variant(Qos3select::Shortage)
365 }
366 #[doc = "Latency sensitive"]
367 #[inline(always)]
368 pub fn sensitive(self) -> &'a mut crate::W<REG> {
369 self.variant(Qos3select::Sensitive)
370 }
371 #[doc = "Latency critical"]
372 #[inline(always)]
373 pub fn critical(self) -> &'a mut crate::W<REG> {
374 self.variant(Qos3select::Critical)
375 }
376}
377#[doc = "Field `RRLVLEN3` reader - Level 3 Round-Robin Scheduling Enable"]
378pub type Rrlvlen3R = crate::BitReader;
379#[doc = "Field `RRLVLEN3` writer - Level 3 Round-Robin Scheduling Enable"]
380pub type Rrlvlen3W<'a, REG> = crate::BitWriter<'a, REG>;
381impl R {
382 #[doc = "Bits 0:4 - Level 0 Channel Priority Number"]
383 #[inline(always)]
384 pub fn lvlpri0(&self) -> Lvlpri0R {
385 Lvlpri0R::new((self.bits & 0x1f) as u8)
386 }
387 #[doc = "Bits 5:6 - Level 0 Quality of Service"]
388 #[inline(always)]
389 pub fn qos0(&self) -> Qos0R {
390 Qos0R::new(((self.bits >> 5) & 3) as u8)
391 }
392 #[doc = "Bit 7 - Level 0 Round-Robin Scheduling Enable"]
393 #[inline(always)]
394 pub fn rrlvlen0(&self) -> Rrlvlen0R {
395 Rrlvlen0R::new(((self.bits >> 7) & 1) != 0)
396 }
397 #[doc = "Bits 8:12 - Level 1 Channel Priority Number"]
398 #[inline(always)]
399 pub fn lvlpri1(&self) -> Lvlpri1R {
400 Lvlpri1R::new(((self.bits >> 8) & 0x1f) as u8)
401 }
402 #[doc = "Bits 13:14 - Level 1 Quality of Service"]
403 #[inline(always)]
404 pub fn qos1(&self) -> Qos1R {
405 Qos1R::new(((self.bits >> 13) & 3) as u8)
406 }
407 #[doc = "Bit 15 - Level 1 Round-Robin Scheduling Enable"]
408 #[inline(always)]
409 pub fn rrlvlen1(&self) -> Rrlvlen1R {
410 Rrlvlen1R::new(((self.bits >> 15) & 1) != 0)
411 }
412 #[doc = "Bits 16:20 - Level 2 Channel Priority Number"]
413 #[inline(always)]
414 pub fn lvlpri2(&self) -> Lvlpri2R {
415 Lvlpri2R::new(((self.bits >> 16) & 0x1f) as u8)
416 }
417 #[doc = "Bits 21:22 - Level 2 Quality of Service"]
418 #[inline(always)]
419 pub fn qos2(&self) -> Qos2R {
420 Qos2R::new(((self.bits >> 21) & 3) as u8)
421 }
422 #[doc = "Bit 23 - Level 2 Round-Robin Scheduling Enable"]
423 #[inline(always)]
424 pub fn rrlvlen2(&self) -> Rrlvlen2R {
425 Rrlvlen2R::new(((self.bits >> 23) & 1) != 0)
426 }
427 #[doc = "Bits 24:28 - Level 3 Channel Priority Number"]
428 #[inline(always)]
429 pub fn lvlpri3(&self) -> Lvlpri3R {
430 Lvlpri3R::new(((self.bits >> 24) & 0x1f) as u8)
431 }
432 #[doc = "Bits 29:30 - Level 3 Quality of Service"]
433 #[inline(always)]
434 pub fn qos3(&self) -> Qos3R {
435 Qos3R::new(((self.bits >> 29) & 3) as u8)
436 }
437 #[doc = "Bit 31 - Level 3 Round-Robin Scheduling Enable"]
438 #[inline(always)]
439 pub fn rrlvlen3(&self) -> Rrlvlen3R {
440 Rrlvlen3R::new(((self.bits >> 31) & 1) != 0)
441 }
442}
443impl W {
444 #[doc = "Bits 0:4 - Level 0 Channel Priority Number"]
445 #[inline(always)]
446 #[must_use]
447 pub fn lvlpri0(&mut self) -> Lvlpri0W<Prictrl0Spec> {
448 Lvlpri0W::new(self, 0)
449 }
450 #[doc = "Bits 5:6 - Level 0 Quality of Service"]
451 #[inline(always)]
452 #[must_use]
453 pub fn qos0(&mut self) -> Qos0W<Prictrl0Spec> {
454 Qos0W::new(self, 5)
455 }
456 #[doc = "Bit 7 - Level 0 Round-Robin Scheduling Enable"]
457 #[inline(always)]
458 #[must_use]
459 pub fn rrlvlen0(&mut self) -> Rrlvlen0W<Prictrl0Spec> {
460 Rrlvlen0W::new(self, 7)
461 }
462 #[doc = "Bits 8:12 - Level 1 Channel Priority Number"]
463 #[inline(always)]
464 #[must_use]
465 pub fn lvlpri1(&mut self) -> Lvlpri1W<Prictrl0Spec> {
466 Lvlpri1W::new(self, 8)
467 }
468 #[doc = "Bits 13:14 - Level 1 Quality of Service"]
469 #[inline(always)]
470 #[must_use]
471 pub fn qos1(&mut self) -> Qos1W<Prictrl0Spec> {
472 Qos1W::new(self, 13)
473 }
474 #[doc = "Bit 15 - Level 1 Round-Robin Scheduling Enable"]
475 #[inline(always)]
476 #[must_use]
477 pub fn rrlvlen1(&mut self) -> Rrlvlen1W<Prictrl0Spec> {
478 Rrlvlen1W::new(self, 15)
479 }
480 #[doc = "Bits 16:20 - Level 2 Channel Priority Number"]
481 #[inline(always)]
482 #[must_use]
483 pub fn lvlpri2(&mut self) -> Lvlpri2W<Prictrl0Spec> {
484 Lvlpri2W::new(self, 16)
485 }
486 #[doc = "Bits 21:22 - Level 2 Quality of Service"]
487 #[inline(always)]
488 #[must_use]
489 pub fn qos2(&mut self) -> Qos2W<Prictrl0Spec> {
490 Qos2W::new(self, 21)
491 }
492 #[doc = "Bit 23 - Level 2 Round-Robin Scheduling Enable"]
493 #[inline(always)]
494 #[must_use]
495 pub fn rrlvlen2(&mut self) -> Rrlvlen2W<Prictrl0Spec> {
496 Rrlvlen2W::new(self, 23)
497 }
498 #[doc = "Bits 24:28 - Level 3 Channel Priority Number"]
499 #[inline(always)]
500 #[must_use]
501 pub fn lvlpri3(&mut self) -> Lvlpri3W<Prictrl0Spec> {
502 Lvlpri3W::new(self, 24)
503 }
504 #[doc = "Bits 29:30 - Level 3 Quality of Service"]
505 #[inline(always)]
506 #[must_use]
507 pub fn qos3(&mut self) -> Qos3W<Prictrl0Spec> {
508 Qos3W::new(self, 29)
509 }
510 #[doc = "Bit 31 - Level 3 Round-Robin Scheduling Enable"]
511 #[inline(always)]
512 #[must_use]
513 pub fn rrlvlen3(&mut self) -> Rrlvlen3W<Prictrl0Spec> {
514 Rrlvlen3W::new(self, 31)
515 }
516}
517#[doc = "Priority Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`prictrl0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`prictrl0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
518pub struct Prictrl0Spec;
519impl crate::RegisterSpec for Prictrl0Spec {
520 type Ux = u32;
521}
522#[doc = "`read()` method returns [`prictrl0::R`](R) reader structure"]
523impl crate::Readable for Prictrl0Spec {}
524#[doc = "`write(|w| ..)` method takes [`prictrl0::W`](W) writer structure"]
525impl crate::Writable for Prictrl0Spec {
526 type Safety = crate::Unsafe;
527 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
528 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
529}
530#[doc = "`reset()` method sets PRICTRL0 to value 0x4040_4040"]
531impl crate::Resettable for Prictrl0Spec {
532 const RESET_VALUE: u32 = 0x4040_4040;
533}