atsamd51g/pdec/
ctrla.rs

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1#[doc = "Register `CTRLA` reader"]
2pub type R = crate::R<CtrlaSpec>;
3#[doc = "Register `CTRLA` writer"]
4pub type W = crate::W<CtrlaSpec>;
5#[doc = "Field `SWRST` reader - Software Reset"]
6pub type SwrstR = crate::BitReader;
7#[doc = "Field `SWRST` writer - Software Reset"]
8pub type SwrstW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `ENABLE` reader - Enable"]
10pub type EnableR = crate::BitReader;
11#[doc = "Field `ENABLE` writer - Enable"]
12pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Operation Mode\n\nValue on reset: 0"]
14#[derive(Clone, Copy, Debug, PartialEq, Eq)]
15#[repr(u8)]
16pub enum Modeselect {
17    #[doc = "0: QDEC operating mode"]
18    Qdec = 0,
19    #[doc = "1: HALL operating mode"]
20    Hall = 1,
21    #[doc = "2: COUNTER operating mode"]
22    Counter = 2,
23}
24impl From<Modeselect> for u8 {
25    #[inline(always)]
26    fn from(variant: Modeselect) -> Self {
27        variant as _
28    }
29}
30impl crate::FieldSpec for Modeselect {
31    type Ux = u8;
32}
33impl crate::IsEnum for Modeselect {}
34#[doc = "Field `MODE` reader - Operation Mode"]
35pub type ModeR = crate::FieldReader<Modeselect>;
36impl ModeR {
37    #[doc = "Get enumerated values variant"]
38    #[inline(always)]
39    pub const fn variant(&self) -> Option<Modeselect> {
40        match self.bits {
41            0 => Some(Modeselect::Qdec),
42            1 => Some(Modeselect::Hall),
43            2 => Some(Modeselect::Counter),
44            _ => None,
45        }
46    }
47    #[doc = "QDEC operating mode"]
48    #[inline(always)]
49    pub fn is_qdec(&self) -> bool {
50        *self == Modeselect::Qdec
51    }
52    #[doc = "HALL operating mode"]
53    #[inline(always)]
54    pub fn is_hall(&self) -> bool {
55        *self == Modeselect::Hall
56    }
57    #[doc = "COUNTER operating mode"]
58    #[inline(always)]
59    pub fn is_counter(&self) -> bool {
60        *self == Modeselect::Counter
61    }
62}
63#[doc = "Field `MODE` writer - Operation Mode"]
64pub type ModeW<'a, REG> = crate::FieldWriter<'a, REG, 2, Modeselect>;
65impl<'a, REG> ModeW<'a, REG>
66where
67    REG: crate::Writable + crate::RegisterSpec,
68    REG::Ux: From<u8>,
69{
70    #[doc = "QDEC operating mode"]
71    #[inline(always)]
72    pub fn qdec(self) -> &'a mut crate::W<REG> {
73        self.variant(Modeselect::Qdec)
74    }
75    #[doc = "HALL operating mode"]
76    #[inline(always)]
77    pub fn hall(self) -> &'a mut crate::W<REG> {
78        self.variant(Modeselect::Hall)
79    }
80    #[doc = "COUNTER operating mode"]
81    #[inline(always)]
82    pub fn counter(self) -> &'a mut crate::W<REG> {
83        self.variant(Modeselect::Counter)
84    }
85}
86#[doc = "Field `RUNSTDBY` reader - Run in Standby"]
87pub type RunstdbyR = crate::BitReader;
88#[doc = "Field `RUNSTDBY` writer - Run in Standby"]
89pub type RunstdbyW<'a, REG> = crate::BitWriter<'a, REG>;
90#[doc = "PDEC Configuration\n\nValue on reset: 0"]
91#[derive(Clone, Copy, Debug, PartialEq, Eq)]
92#[repr(u8)]
93pub enum Confselect {
94    #[doc = "0: Quadrature decoder direction"]
95    X4 = 0,
96    #[doc = "1: Secure Quadrature decoder direction"]
97    X4s = 1,
98    #[doc = "2: Decoder direction"]
99    X2 = 2,
100    #[doc = "3: Secure decoder direction"]
101    X2s = 3,
102    #[doc = "4: Auto correction mode"]
103    Autoc = 4,
104}
105impl From<Confselect> for u8 {
106    #[inline(always)]
107    fn from(variant: Confselect) -> Self {
108        variant as _
109    }
110}
111impl crate::FieldSpec for Confselect {
112    type Ux = u8;
113}
114impl crate::IsEnum for Confselect {}
115#[doc = "Field `CONF` reader - PDEC Configuration"]
116pub type ConfR = crate::FieldReader<Confselect>;
117impl ConfR {
118    #[doc = "Get enumerated values variant"]
119    #[inline(always)]
120    pub const fn variant(&self) -> Option<Confselect> {
121        match self.bits {
122            0 => Some(Confselect::X4),
123            1 => Some(Confselect::X4s),
124            2 => Some(Confselect::X2),
125            3 => Some(Confselect::X2s),
126            4 => Some(Confselect::Autoc),
127            _ => None,
128        }
129    }
130    #[doc = "Quadrature decoder direction"]
131    #[inline(always)]
132    pub fn is_x4(&self) -> bool {
133        *self == Confselect::X4
134    }
135    #[doc = "Secure Quadrature decoder direction"]
136    #[inline(always)]
137    pub fn is_x4s(&self) -> bool {
138        *self == Confselect::X4s
139    }
140    #[doc = "Decoder direction"]
141    #[inline(always)]
142    pub fn is_x2(&self) -> bool {
143        *self == Confselect::X2
144    }
145    #[doc = "Secure decoder direction"]
146    #[inline(always)]
147    pub fn is_x2s(&self) -> bool {
148        *self == Confselect::X2s
149    }
150    #[doc = "Auto correction mode"]
151    #[inline(always)]
152    pub fn is_autoc(&self) -> bool {
153        *self == Confselect::Autoc
154    }
155}
156#[doc = "Field `CONF` writer - PDEC Configuration"]
157pub type ConfW<'a, REG> = crate::FieldWriter<'a, REG, 3, Confselect>;
158impl<'a, REG> ConfW<'a, REG>
159where
160    REG: crate::Writable + crate::RegisterSpec,
161    REG::Ux: From<u8>,
162{
163    #[doc = "Quadrature decoder direction"]
164    #[inline(always)]
165    pub fn x4(self) -> &'a mut crate::W<REG> {
166        self.variant(Confselect::X4)
167    }
168    #[doc = "Secure Quadrature decoder direction"]
169    #[inline(always)]
170    pub fn x4s(self) -> &'a mut crate::W<REG> {
171        self.variant(Confselect::X4s)
172    }
173    #[doc = "Decoder direction"]
174    #[inline(always)]
175    pub fn x2(self) -> &'a mut crate::W<REG> {
176        self.variant(Confselect::X2)
177    }
178    #[doc = "Secure decoder direction"]
179    #[inline(always)]
180    pub fn x2s(self) -> &'a mut crate::W<REG> {
181        self.variant(Confselect::X2s)
182    }
183    #[doc = "Auto correction mode"]
184    #[inline(always)]
185    pub fn autoc(self) -> &'a mut crate::W<REG> {
186        self.variant(Confselect::Autoc)
187    }
188}
189#[doc = "Field `ALOCK` reader - Auto Lock"]
190pub type AlockR = crate::BitReader;
191#[doc = "Field `ALOCK` writer - Auto Lock"]
192pub type AlockW<'a, REG> = crate::BitWriter<'a, REG>;
193#[doc = "Field `SWAP` reader - PDEC Phase A and B Swap"]
194pub type SwapR = crate::BitReader;
195#[doc = "Field `SWAP` writer - PDEC Phase A and B Swap"]
196pub type SwapW<'a, REG> = crate::BitWriter<'a, REG>;
197#[doc = "Field `PEREN` reader - Period Enable"]
198pub type PerenR = crate::BitReader;
199#[doc = "Field `PEREN` writer - Period Enable"]
200pub type PerenW<'a, REG> = crate::BitWriter<'a, REG>;
201#[doc = "Field `PINEN0` reader - PDEC Input From Pin 0 Enable"]
202pub type Pinen0R = crate::BitReader;
203#[doc = "Field `PINEN0` writer - PDEC Input From Pin 0 Enable"]
204pub type Pinen0W<'a, REG> = crate::BitWriter<'a, REG>;
205#[doc = "Field `PINEN1` reader - PDEC Input From Pin 1 Enable"]
206pub type Pinen1R = crate::BitReader;
207#[doc = "Field `PINEN1` writer - PDEC Input From Pin 1 Enable"]
208pub type Pinen1W<'a, REG> = crate::BitWriter<'a, REG>;
209#[doc = "Field `PINEN2` reader - PDEC Input From Pin 2 Enable"]
210pub type Pinen2R = crate::BitReader;
211#[doc = "Field `PINEN2` writer - PDEC Input From Pin 2 Enable"]
212pub type Pinen2W<'a, REG> = crate::BitWriter<'a, REG>;
213#[doc = "Field `PINVEN0` reader - IO Pin 0 Invert Enable"]
214pub type Pinven0R = crate::BitReader;
215#[doc = "Field `PINVEN0` writer - IO Pin 0 Invert Enable"]
216pub type Pinven0W<'a, REG> = crate::BitWriter<'a, REG>;
217#[doc = "Field `PINVEN1` reader - IO Pin 1 Invert Enable"]
218pub type Pinven1R = crate::BitReader;
219#[doc = "Field `PINVEN1` writer - IO Pin 1 Invert Enable"]
220pub type Pinven1W<'a, REG> = crate::BitWriter<'a, REG>;
221#[doc = "Field `PINVEN2` reader - IO Pin 2 Invert Enable"]
222pub type Pinven2R = crate::BitReader;
223#[doc = "Field `PINVEN2` writer - IO Pin 2 Invert Enable"]
224pub type Pinven2W<'a, REG> = crate::BitWriter<'a, REG>;
225#[doc = "Field `ANGULAR` reader - Angular Counter Length"]
226pub type AngularR = crate::FieldReader;
227#[doc = "Field `ANGULAR` writer - Angular Counter Length"]
228pub type AngularW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
229#[doc = "Field `MAXCMP` reader - Maximum Consecutive Missing Pulses"]
230pub type MaxcmpR = crate::FieldReader;
231#[doc = "Field `MAXCMP` writer - Maximum Consecutive Missing Pulses"]
232pub type MaxcmpW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
233impl R {
234    #[doc = "Bit 0 - Software Reset"]
235    #[inline(always)]
236    pub fn swrst(&self) -> SwrstR {
237        SwrstR::new((self.bits & 1) != 0)
238    }
239    #[doc = "Bit 1 - Enable"]
240    #[inline(always)]
241    pub fn enable(&self) -> EnableR {
242        EnableR::new(((self.bits >> 1) & 1) != 0)
243    }
244    #[doc = "Bits 2:3 - Operation Mode"]
245    #[inline(always)]
246    pub fn mode(&self) -> ModeR {
247        ModeR::new(((self.bits >> 2) & 3) as u8)
248    }
249    #[doc = "Bit 6 - Run in Standby"]
250    #[inline(always)]
251    pub fn runstdby(&self) -> RunstdbyR {
252        RunstdbyR::new(((self.bits >> 6) & 1) != 0)
253    }
254    #[doc = "Bits 8:10 - PDEC Configuration"]
255    #[inline(always)]
256    pub fn conf(&self) -> ConfR {
257        ConfR::new(((self.bits >> 8) & 7) as u8)
258    }
259    #[doc = "Bit 11 - Auto Lock"]
260    #[inline(always)]
261    pub fn alock(&self) -> AlockR {
262        AlockR::new(((self.bits >> 11) & 1) != 0)
263    }
264    #[doc = "Bit 14 - PDEC Phase A and B Swap"]
265    #[inline(always)]
266    pub fn swap(&self) -> SwapR {
267        SwapR::new(((self.bits >> 14) & 1) != 0)
268    }
269    #[doc = "Bit 15 - Period Enable"]
270    #[inline(always)]
271    pub fn peren(&self) -> PerenR {
272        PerenR::new(((self.bits >> 15) & 1) != 0)
273    }
274    #[doc = "Bit 16 - PDEC Input From Pin 0 Enable"]
275    #[inline(always)]
276    pub fn pinen0(&self) -> Pinen0R {
277        Pinen0R::new(((self.bits >> 16) & 1) != 0)
278    }
279    #[doc = "Bit 17 - PDEC Input From Pin 1 Enable"]
280    #[inline(always)]
281    pub fn pinen1(&self) -> Pinen1R {
282        Pinen1R::new(((self.bits >> 17) & 1) != 0)
283    }
284    #[doc = "Bit 18 - PDEC Input From Pin 2 Enable"]
285    #[inline(always)]
286    pub fn pinen2(&self) -> Pinen2R {
287        Pinen2R::new(((self.bits >> 18) & 1) != 0)
288    }
289    #[doc = "Bit 20 - IO Pin 0 Invert Enable"]
290    #[inline(always)]
291    pub fn pinven0(&self) -> Pinven0R {
292        Pinven0R::new(((self.bits >> 20) & 1) != 0)
293    }
294    #[doc = "Bit 21 - IO Pin 1 Invert Enable"]
295    #[inline(always)]
296    pub fn pinven1(&self) -> Pinven1R {
297        Pinven1R::new(((self.bits >> 21) & 1) != 0)
298    }
299    #[doc = "Bit 22 - IO Pin 2 Invert Enable"]
300    #[inline(always)]
301    pub fn pinven2(&self) -> Pinven2R {
302        Pinven2R::new(((self.bits >> 22) & 1) != 0)
303    }
304    #[doc = "Bits 24:26 - Angular Counter Length"]
305    #[inline(always)]
306    pub fn angular(&self) -> AngularR {
307        AngularR::new(((self.bits >> 24) & 7) as u8)
308    }
309    #[doc = "Bits 28:31 - Maximum Consecutive Missing Pulses"]
310    #[inline(always)]
311    pub fn maxcmp(&self) -> MaxcmpR {
312        MaxcmpR::new(((self.bits >> 28) & 0x0f) as u8)
313    }
314}
315impl W {
316    #[doc = "Bit 0 - Software Reset"]
317    #[inline(always)]
318    #[must_use]
319    pub fn swrst(&mut self) -> SwrstW<CtrlaSpec> {
320        SwrstW::new(self, 0)
321    }
322    #[doc = "Bit 1 - Enable"]
323    #[inline(always)]
324    #[must_use]
325    pub fn enable(&mut self) -> EnableW<CtrlaSpec> {
326        EnableW::new(self, 1)
327    }
328    #[doc = "Bits 2:3 - Operation Mode"]
329    #[inline(always)]
330    #[must_use]
331    pub fn mode(&mut self) -> ModeW<CtrlaSpec> {
332        ModeW::new(self, 2)
333    }
334    #[doc = "Bit 6 - Run in Standby"]
335    #[inline(always)]
336    #[must_use]
337    pub fn runstdby(&mut self) -> RunstdbyW<CtrlaSpec> {
338        RunstdbyW::new(self, 6)
339    }
340    #[doc = "Bits 8:10 - PDEC Configuration"]
341    #[inline(always)]
342    #[must_use]
343    pub fn conf(&mut self) -> ConfW<CtrlaSpec> {
344        ConfW::new(self, 8)
345    }
346    #[doc = "Bit 11 - Auto Lock"]
347    #[inline(always)]
348    #[must_use]
349    pub fn alock(&mut self) -> AlockW<CtrlaSpec> {
350        AlockW::new(self, 11)
351    }
352    #[doc = "Bit 14 - PDEC Phase A and B Swap"]
353    #[inline(always)]
354    #[must_use]
355    pub fn swap(&mut self) -> SwapW<CtrlaSpec> {
356        SwapW::new(self, 14)
357    }
358    #[doc = "Bit 15 - Period Enable"]
359    #[inline(always)]
360    #[must_use]
361    pub fn peren(&mut self) -> PerenW<CtrlaSpec> {
362        PerenW::new(self, 15)
363    }
364    #[doc = "Bit 16 - PDEC Input From Pin 0 Enable"]
365    #[inline(always)]
366    #[must_use]
367    pub fn pinen0(&mut self) -> Pinen0W<CtrlaSpec> {
368        Pinen0W::new(self, 16)
369    }
370    #[doc = "Bit 17 - PDEC Input From Pin 1 Enable"]
371    #[inline(always)]
372    #[must_use]
373    pub fn pinen1(&mut self) -> Pinen1W<CtrlaSpec> {
374        Pinen1W::new(self, 17)
375    }
376    #[doc = "Bit 18 - PDEC Input From Pin 2 Enable"]
377    #[inline(always)]
378    #[must_use]
379    pub fn pinen2(&mut self) -> Pinen2W<CtrlaSpec> {
380        Pinen2W::new(self, 18)
381    }
382    #[doc = "Bit 20 - IO Pin 0 Invert Enable"]
383    #[inline(always)]
384    #[must_use]
385    pub fn pinven0(&mut self) -> Pinven0W<CtrlaSpec> {
386        Pinven0W::new(self, 20)
387    }
388    #[doc = "Bit 21 - IO Pin 1 Invert Enable"]
389    #[inline(always)]
390    #[must_use]
391    pub fn pinven1(&mut self) -> Pinven1W<CtrlaSpec> {
392        Pinven1W::new(self, 21)
393    }
394    #[doc = "Bit 22 - IO Pin 2 Invert Enable"]
395    #[inline(always)]
396    #[must_use]
397    pub fn pinven2(&mut self) -> Pinven2W<CtrlaSpec> {
398        Pinven2W::new(self, 22)
399    }
400    #[doc = "Bits 24:26 - Angular Counter Length"]
401    #[inline(always)]
402    #[must_use]
403    pub fn angular(&mut self) -> AngularW<CtrlaSpec> {
404        AngularW::new(self, 24)
405    }
406    #[doc = "Bits 28:31 - Maximum Consecutive Missing Pulses"]
407    #[inline(always)]
408    #[must_use]
409    pub fn maxcmp(&mut self) -> MaxcmpW<CtrlaSpec> {
410        MaxcmpW::new(self, 28)
411    }
412}
413#[doc = "Control A\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrla::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrla::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
414pub struct CtrlaSpec;
415impl crate::RegisterSpec for CtrlaSpec {
416    type Ux = u32;
417}
418#[doc = "`read()` method returns [`ctrla::R`](R) reader structure"]
419impl crate::Readable for CtrlaSpec {}
420#[doc = "`write(|w| ..)` method takes [`ctrla::W`](W) writer structure"]
421impl crate::Writable for CtrlaSpec {
422    type Safety = crate::Unsafe;
423    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
424    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
425}
426#[doc = "`reset()` method sets CTRLA to value 0"]
427impl crate::Resettable for CtrlaSpec {
428    const RESET_VALUE: u32 = 0;
429}
atsamd51g/pdec/ctrla.rs

atsamd51g/pdec/
ctrla.rs
