atsamd51g/adc0/
ctrla.rs

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1#[doc = "Register `CTRLA` reader"]
2pub type R = crate::R<CtrlaSpec>;
3#[doc = "Register `CTRLA` writer"]
4pub type W = crate::W<CtrlaSpec>;
5#[doc = "Field `SWRST` reader - Software Reset"]
6pub type SwrstR = crate::BitReader;
7#[doc = "Field `SWRST` writer - Software Reset"]
8pub type SwrstW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `ENABLE` reader - Enable"]
10pub type EnableR = crate::BitReader;
11#[doc = "Field `ENABLE` writer - Enable"]
12pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Dual Mode Trigger Selection\n\nValue on reset: 0"]
14#[derive(Clone, Copy, Debug, PartialEq, Eq)]
15#[repr(u8)]
16pub enum Dualselselect {
17    #[doc = "0: Start event or software trigger will start a conversion on both ADCs"]
18    Both = 0,
19    #[doc = "1: START event or software trigger will alternatingly start a conversion on ADC0 and ADC1"]
20    Interleave = 1,
21}
22impl From<Dualselselect> for u8 {
23    #[inline(always)]
24    fn from(variant: Dualselselect) -> Self {
25        variant as _
26    }
27}
28impl crate::FieldSpec for Dualselselect {
29    type Ux = u8;
30}
31impl crate::IsEnum for Dualselselect {}
32#[doc = "Field `DUALSEL` reader - Dual Mode Trigger Selection"]
33pub type DualselR = crate::FieldReader<Dualselselect>;
34impl DualselR {
35    #[doc = "Get enumerated values variant"]
36    #[inline(always)]
37    pub const fn variant(&self) -> Option<Dualselselect> {
38        match self.bits {
39            0 => Some(Dualselselect::Both),
40            1 => Some(Dualselselect::Interleave),
41            _ => None,
42        }
43    }
44    #[doc = "Start event or software trigger will start a conversion on both ADCs"]
45    #[inline(always)]
46    pub fn is_both(&self) -> bool {
47        *self == Dualselselect::Both
48    }
49    #[doc = "START event or software trigger will alternatingly start a conversion on ADC0 and ADC1"]
50    #[inline(always)]
51    pub fn is_interleave(&self) -> bool {
52        *self == Dualselselect::Interleave
53    }
54}
55#[doc = "Field `DUALSEL` writer - Dual Mode Trigger Selection"]
56pub type DualselW<'a, REG> = crate::FieldWriter<'a, REG, 2, Dualselselect>;
57impl<'a, REG> DualselW<'a, REG>
58where
59    REG: crate::Writable + crate::RegisterSpec,
60    REG::Ux: From<u8>,
61{
62    #[doc = "Start event or software trigger will start a conversion on both ADCs"]
63    #[inline(always)]
64    pub fn both(self) -> &'a mut crate::W<REG> {
65        self.variant(Dualselselect::Both)
66    }
67    #[doc = "START event or software trigger will alternatingly start a conversion on ADC0 and ADC1"]
68    #[inline(always)]
69    pub fn interleave(self) -> &'a mut crate::W<REG> {
70        self.variant(Dualselselect::Interleave)
71    }
72}
73#[doc = "Field `SLAVEEN` reader - Slave Enable"]
74pub type SlaveenR = crate::BitReader;
75#[doc = "Field `SLAVEEN` writer - Slave Enable"]
76pub type SlaveenW<'a, REG> = crate::BitWriter<'a, REG>;
77#[doc = "Field `RUNSTDBY` reader - Run in Standby"]
78pub type RunstdbyR = crate::BitReader;
79#[doc = "Field `RUNSTDBY` writer - Run in Standby"]
80pub type RunstdbyW<'a, REG> = crate::BitWriter<'a, REG>;
81#[doc = "Field `ONDEMAND` reader - On Demand Control"]
82pub type OndemandR = crate::BitReader;
83#[doc = "Field `ONDEMAND` writer - On Demand Control"]
84pub type OndemandW<'a, REG> = crate::BitWriter<'a, REG>;
85#[doc = "Prescaler Configuration\n\nValue on reset: 0"]
86#[derive(Clone, Copy, Debug, PartialEq, Eq)]
87#[repr(u8)]
88pub enum Prescalerselect {
89    #[doc = "0: Peripheral clock divided by 2"]
90    Div2 = 0,
91    #[doc = "1: Peripheral clock divided by 4"]
92    Div4 = 1,
93    #[doc = "2: Peripheral clock divided by 8"]
94    Div8 = 2,
95    #[doc = "3: Peripheral clock divided by 16"]
96    Div16 = 3,
97    #[doc = "4: Peripheral clock divided by 32"]
98    Div32 = 4,
99    #[doc = "5: Peripheral clock divided by 64"]
100    Div64 = 5,
101    #[doc = "6: Peripheral clock divided by 128"]
102    Div128 = 6,
103    #[doc = "7: Peripheral clock divided by 256"]
104    Div256 = 7,
105}
106impl From<Prescalerselect> for u8 {
107    #[inline(always)]
108    fn from(variant: Prescalerselect) -> Self {
109        variant as _
110    }
111}
112impl crate::FieldSpec for Prescalerselect {
113    type Ux = u8;
114}
115impl crate::IsEnum for Prescalerselect {}
116#[doc = "Field `PRESCALER` reader - Prescaler Configuration"]
117pub type PrescalerR = crate::FieldReader<Prescalerselect>;
118impl PrescalerR {
119    #[doc = "Get enumerated values variant"]
120    #[inline(always)]
121    pub const fn variant(&self) -> Prescalerselect {
122        match self.bits {
123            0 => Prescalerselect::Div2,
124            1 => Prescalerselect::Div4,
125            2 => Prescalerselect::Div8,
126            3 => Prescalerselect::Div16,
127            4 => Prescalerselect::Div32,
128            5 => Prescalerselect::Div64,
129            6 => Prescalerselect::Div128,
130            7 => Prescalerselect::Div256,
131            _ => unreachable!(),
132        }
133    }
134    #[doc = "Peripheral clock divided by 2"]
135    #[inline(always)]
136    pub fn is_div2(&self) -> bool {
137        *self == Prescalerselect::Div2
138    }
139    #[doc = "Peripheral clock divided by 4"]
140    #[inline(always)]
141    pub fn is_div4(&self) -> bool {
142        *self == Prescalerselect::Div4
143    }
144    #[doc = "Peripheral clock divided by 8"]
145    #[inline(always)]
146    pub fn is_div8(&self) -> bool {
147        *self == Prescalerselect::Div8
148    }
149    #[doc = "Peripheral clock divided by 16"]
150    #[inline(always)]
151    pub fn is_div16(&self) -> bool {
152        *self == Prescalerselect::Div16
153    }
154    #[doc = "Peripheral clock divided by 32"]
155    #[inline(always)]
156    pub fn is_div32(&self) -> bool {
157        *self == Prescalerselect::Div32
158    }
159    #[doc = "Peripheral clock divided by 64"]
160    #[inline(always)]
161    pub fn is_div64(&self) -> bool {
162        *self == Prescalerselect::Div64
163    }
164    #[doc = "Peripheral clock divided by 128"]
165    #[inline(always)]
166    pub fn is_div128(&self) -> bool {
167        *self == Prescalerselect::Div128
168    }
169    #[doc = "Peripheral clock divided by 256"]
170    #[inline(always)]
171    pub fn is_div256(&self) -> bool {
172        *self == Prescalerselect::Div256
173    }
174}
175#[doc = "Field `PRESCALER` writer - Prescaler Configuration"]
176pub type PrescalerW<'a, REG> = crate::FieldWriter<'a, REG, 3, Prescalerselect, crate::Safe>;
177impl<'a, REG> PrescalerW<'a, REG>
178where
179    REG: crate::Writable + crate::RegisterSpec,
180    REG::Ux: From<u8>,
181{
182    #[doc = "Peripheral clock divided by 2"]
183    #[inline(always)]
184    pub fn div2(self) -> &'a mut crate::W<REG> {
185        self.variant(Prescalerselect::Div2)
186    }
187    #[doc = "Peripheral clock divided by 4"]
188    #[inline(always)]
189    pub fn div4(self) -> &'a mut crate::W<REG> {
190        self.variant(Prescalerselect::Div4)
191    }
192    #[doc = "Peripheral clock divided by 8"]
193    #[inline(always)]
194    pub fn div8(self) -> &'a mut crate::W<REG> {
195        self.variant(Prescalerselect::Div8)
196    }
197    #[doc = "Peripheral clock divided by 16"]
198    #[inline(always)]
199    pub fn div16(self) -> &'a mut crate::W<REG> {
200        self.variant(Prescalerselect::Div16)
201    }
202    #[doc = "Peripheral clock divided by 32"]
203    #[inline(always)]
204    pub fn div32(self) -> &'a mut crate::W<REG> {
205        self.variant(Prescalerselect::Div32)
206    }
207    #[doc = "Peripheral clock divided by 64"]
208    #[inline(always)]
209    pub fn div64(self) -> &'a mut crate::W<REG> {
210        self.variant(Prescalerselect::Div64)
211    }
212    #[doc = "Peripheral clock divided by 128"]
213    #[inline(always)]
214    pub fn div128(self) -> &'a mut crate::W<REG> {
215        self.variant(Prescalerselect::Div128)
216    }
217    #[doc = "Peripheral clock divided by 256"]
218    #[inline(always)]
219    pub fn div256(self) -> &'a mut crate::W<REG> {
220        self.variant(Prescalerselect::Div256)
221    }
222}
223#[doc = "Field `R2R` reader - Rail to Rail Operation Enable"]
224pub type R2rR = crate::BitReader;
225#[doc = "Field `R2R` writer - Rail to Rail Operation Enable"]
226pub type R2rW<'a, REG> = crate::BitWriter<'a, REG>;
227impl R {
228    #[doc = "Bit 0 - Software Reset"]
229    #[inline(always)]
230    pub fn swrst(&self) -> SwrstR {
231        SwrstR::new((self.bits & 1) != 0)
232    }
233    #[doc = "Bit 1 - Enable"]
234    #[inline(always)]
235    pub fn enable(&self) -> EnableR {
236        EnableR::new(((self.bits >> 1) & 1) != 0)
237    }
238    #[doc = "Bits 3:4 - Dual Mode Trigger Selection"]
239    #[inline(always)]
240    pub fn dualsel(&self) -> DualselR {
241        DualselR::new(((self.bits >> 3) & 3) as u8)
242    }
243    #[doc = "Bit 5 - Slave Enable"]
244    #[inline(always)]
245    pub fn slaveen(&self) -> SlaveenR {
246        SlaveenR::new(((self.bits >> 5) & 1) != 0)
247    }
248    #[doc = "Bit 6 - Run in Standby"]
249    #[inline(always)]
250    pub fn runstdby(&self) -> RunstdbyR {
251        RunstdbyR::new(((self.bits >> 6) & 1) != 0)
252    }
253    #[doc = "Bit 7 - On Demand Control"]
254    #[inline(always)]
255    pub fn ondemand(&self) -> OndemandR {
256        OndemandR::new(((self.bits >> 7) & 1) != 0)
257    }
258    #[doc = "Bits 8:10 - Prescaler Configuration"]
259    #[inline(always)]
260    pub fn prescaler(&self) -> PrescalerR {
261        PrescalerR::new(((self.bits >> 8) & 7) as u8)
262    }
263    #[doc = "Bit 15 - Rail to Rail Operation Enable"]
264    #[inline(always)]
265    pub fn r2r(&self) -> R2rR {
266        R2rR::new(((self.bits >> 15) & 1) != 0)
267    }
268}
269impl W {
270    #[doc = "Bit 0 - Software Reset"]
271    #[inline(always)]
272    #[must_use]
273    pub fn swrst(&mut self) -> SwrstW<CtrlaSpec> {
274        SwrstW::new(self, 0)
275    }
276    #[doc = "Bit 1 - Enable"]
277    #[inline(always)]
278    #[must_use]
279    pub fn enable(&mut self) -> EnableW<CtrlaSpec> {
280        EnableW::new(self, 1)
281    }
282    #[doc = "Bits 3:4 - Dual Mode Trigger Selection"]
283    #[inline(always)]
284    #[must_use]
285    pub fn dualsel(&mut self) -> DualselW<CtrlaSpec> {
286        DualselW::new(self, 3)
287    }
288    #[doc = "Bit 5 - Slave Enable"]
289    #[inline(always)]
290    #[must_use]
291    pub fn slaveen(&mut self) -> SlaveenW<CtrlaSpec> {
292        SlaveenW::new(self, 5)
293    }
294    #[doc = "Bit 6 - Run in Standby"]
295    #[inline(always)]
296    #[must_use]
297    pub fn runstdby(&mut self) -> RunstdbyW<CtrlaSpec> {
298        RunstdbyW::new(self, 6)
299    }
300    #[doc = "Bit 7 - On Demand Control"]
301    #[inline(always)]
302    #[must_use]
303    pub fn ondemand(&mut self) -> OndemandW<CtrlaSpec> {
304        OndemandW::new(self, 7)
305    }
306    #[doc = "Bits 8:10 - Prescaler Configuration"]
307    #[inline(always)]
308    #[must_use]
309    pub fn prescaler(&mut self) -> PrescalerW<CtrlaSpec> {
310        PrescalerW::new(self, 8)
311    }
312    #[doc = "Bit 15 - Rail to Rail Operation Enable"]
313    #[inline(always)]
314    #[must_use]
315    pub fn r2r(&mut self) -> R2rW<CtrlaSpec> {
316        R2rW::new(self, 15)
317    }
318}
319#[doc = "Control A\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrla::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrla::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
320pub struct CtrlaSpec;
321impl crate::RegisterSpec for CtrlaSpec {
322    type Ux = u16;
323}
324#[doc = "`read()` method returns [`ctrla::R`](R) reader structure"]
325impl crate::Readable for CtrlaSpec {}
326#[doc = "`write(|w| ..)` method takes [`ctrla::W`](W) writer structure"]
327impl crate::Writable for CtrlaSpec {
328    type Safety = crate::Unsafe;
329    const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
330    const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
331}
332#[doc = "`reset()` method sets CTRLA to value 0"]
333impl crate::Resettable for CtrlaSpec {
334    const RESET_VALUE: u16 = 0;
335}
atsamd51g/adc0/ctrla.rs

atsamd51g/adc0/
ctrla.rs
