atsamd51g/system_control/
aircr.rs

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1#[doc = "Register `AIRCR` reader"]
2pub type R = crate::R<AircrSpec>;
3#[doc = "Register `AIRCR` writer"]
4pub type W = crate::W<AircrSpec>;
5#[doc = "Field `VECTRESET` reader - Must write 0"]
6pub type VectresetR = crate::BitReader;
7#[doc = "Field `VECTRESET` writer - Must write 0"]
8pub type VectresetW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `VECTCLRACTIVE` reader - Must write 0"]
10pub type VectclractiveR = crate::BitReader;
11#[doc = "Field `VECTCLRACTIVE` writer - Must write 0"]
12pub type VectclractiveW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "System Reset Request\n\nValue on reset: 0"]
14#[derive(Clone, Copy, Debug, PartialEq, Eq)]
15pub enum Sysresetreqselect {
16    #[doc = "0: No system reset request"]
17    Value0 = 0,
18    #[doc = "1: Asserts a signal to the outer system that requests a reset"]
19    Value1 = 1,
20}
21impl From<Sysresetreqselect> for bool {
22    #[inline(always)]
23    fn from(variant: Sysresetreqselect) -> Self {
24        variant as u8 != 0
25    }
26}
27#[doc = "Field `SYSRESETREQ` reader - System Reset Request"]
28pub type SysresetreqR = crate::BitReader<Sysresetreqselect>;
29impl SysresetreqR {
30    #[doc = "Get enumerated values variant"]
31    #[inline(always)]
32    pub const fn variant(&self) -> Sysresetreqselect {
33        match self.bits {
34            false => Sysresetreqselect::Value0,
35            true => Sysresetreqselect::Value1,
36        }
37    }
38    #[doc = "No system reset request"]
39    #[inline(always)]
40    pub fn is_value_0(&self) -> bool {
41        *self == Sysresetreqselect::Value0
42    }
43    #[doc = "Asserts a signal to the outer system that requests a reset"]
44    #[inline(always)]
45    pub fn is_value_1(&self) -> bool {
46        *self == Sysresetreqselect::Value1
47    }
48}
49#[doc = "Field `SYSRESETREQ` writer - System Reset Request"]
50pub type SysresetreqW<'a, REG> = crate::BitWriter<'a, REG, Sysresetreqselect>;
51impl<'a, REG> SysresetreqW<'a, REG>
52where
53    REG: crate::Writable + crate::RegisterSpec,
54{
55    #[doc = "No system reset request"]
56    #[inline(always)]
57    pub fn value_0(self) -> &'a mut crate::W<REG> {
58        self.variant(Sysresetreqselect::Value0)
59    }
60    #[doc = "Asserts a signal to the outer system that requests a reset"]
61    #[inline(always)]
62    pub fn value_1(self) -> &'a mut crate::W<REG> {
63        self.variant(Sysresetreqselect::Value1)
64    }
65}
66#[doc = "Field `PRIGROUP` reader - Interrupt priority grouping"]
67pub type PrigroupR = crate::FieldReader;
68#[doc = "Field `PRIGROUP` writer - Interrupt priority grouping"]
69pub type PrigroupW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
70#[doc = "Data endianness, 0=little, 1=big\n\nValue on reset: 0"]
71#[derive(Clone, Copy, Debug, PartialEq, Eq)]
72pub enum Endiannessselect {
73    #[doc = "0: Little-endian"]
74    Value0 = 0,
75    #[doc = "1: Big-endian"]
76    Value1 = 1,
77}
78impl From<Endiannessselect> for bool {
79    #[inline(always)]
80    fn from(variant: Endiannessselect) -> Self {
81        variant as u8 != 0
82    }
83}
84#[doc = "Field `ENDIANNESS` reader - Data endianness, 0=little, 1=big"]
85pub type EndiannessR = crate::BitReader<Endiannessselect>;
86impl EndiannessR {
87    #[doc = "Get enumerated values variant"]
88    #[inline(always)]
89    pub const fn variant(&self) -> Endiannessselect {
90        match self.bits {
91            false => Endiannessselect::Value0,
92            true => Endiannessselect::Value1,
93        }
94    }
95    #[doc = "Little-endian"]
96    #[inline(always)]
97    pub fn is_value_0(&self) -> bool {
98        *self == Endiannessselect::Value0
99    }
100    #[doc = "Big-endian"]
101    #[inline(always)]
102    pub fn is_value_1(&self) -> bool {
103        *self == Endiannessselect::Value1
104    }
105}
106#[doc = "Field `ENDIANNESS` writer - Data endianness, 0=little, 1=big"]
107pub type EndiannessW<'a, REG> = crate::BitWriter<'a, REG, Endiannessselect>;
108impl<'a, REG> EndiannessW<'a, REG>
109where
110    REG: crate::Writable + crate::RegisterSpec,
111{
112    #[doc = "Little-endian"]
113    #[inline(always)]
114    pub fn value_0(self) -> &'a mut crate::W<REG> {
115        self.variant(Endiannessselect::Value0)
116    }
117    #[doc = "Big-endian"]
118    #[inline(always)]
119    pub fn value_1(self) -> &'a mut crate::W<REG> {
120        self.variant(Endiannessselect::Value1)
121    }
122}
123#[doc = "Field `VECTKEY` reader - Register key"]
124pub type VectkeyR = crate::FieldReader<u16>;
125#[doc = "Field `VECTKEY` writer - Register key"]
126pub type VectkeyW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
127impl R {
128    #[doc = "Bit 0 - Must write 0"]
129    #[inline(always)]
130    pub fn vectreset(&self) -> VectresetR {
131        VectresetR::new((self.bits & 1) != 0)
132    }
133    #[doc = "Bit 1 - Must write 0"]
134    #[inline(always)]
135    pub fn vectclractive(&self) -> VectclractiveR {
136        VectclractiveR::new(((self.bits >> 1) & 1) != 0)
137    }
138    #[doc = "Bit 2 - System Reset Request"]
139    #[inline(always)]
140    pub fn sysresetreq(&self) -> SysresetreqR {
141        SysresetreqR::new(((self.bits >> 2) & 1) != 0)
142    }
143    #[doc = "Bits 8:10 - Interrupt priority grouping"]
144    #[inline(always)]
145    pub fn prigroup(&self) -> PrigroupR {
146        PrigroupR::new(((self.bits >> 8) & 7) as u8)
147    }
148    #[doc = "Bit 15 - Data endianness, 0=little, 1=big"]
149    #[inline(always)]
150    pub fn endianness(&self) -> EndiannessR {
151        EndiannessR::new(((self.bits >> 15) & 1) != 0)
152    }
153    #[doc = "Bits 16:31 - Register key"]
154    #[inline(always)]
155    pub fn vectkey(&self) -> VectkeyR {
156        VectkeyR::new(((self.bits >> 16) & 0xffff) as u16)
157    }
158}
159impl W {
160    #[doc = "Bit 0 - Must write 0"]
161    #[inline(always)]
162    #[must_use]
163    pub fn vectreset(&mut self) -> VectresetW<AircrSpec> {
164        VectresetW::new(self, 0)
165    }
166    #[doc = "Bit 1 - Must write 0"]
167    #[inline(always)]
168    #[must_use]
169    pub fn vectclractive(&mut self) -> VectclractiveW<AircrSpec> {
170        VectclractiveW::new(self, 1)
171    }
172    #[doc = "Bit 2 - System Reset Request"]
173    #[inline(always)]
174    #[must_use]
175    pub fn sysresetreq(&mut self) -> SysresetreqW<AircrSpec> {
176        SysresetreqW::new(self, 2)
177    }
178    #[doc = "Bits 8:10 - Interrupt priority grouping"]
179    #[inline(always)]
180    #[must_use]
181    pub fn prigroup(&mut self) -> PrigroupW<AircrSpec> {
182        PrigroupW::new(self, 8)
183    }
184    #[doc = "Bit 15 - Data endianness, 0=little, 1=big"]
185    #[inline(always)]
186    #[must_use]
187    pub fn endianness(&mut self) -> EndiannessW<AircrSpec> {
188        EndiannessW::new(self, 15)
189    }
190    #[doc = "Bits 16:31 - Register key"]
191    #[inline(always)]
192    #[must_use]
193    pub fn vectkey(&mut self) -> VectkeyW<AircrSpec> {
194        VectkeyW::new(self, 16)
195    }
196}
197#[doc = "Application Interrupt and Reset Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`aircr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aircr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
198pub struct AircrSpec;
199impl crate::RegisterSpec for AircrSpec {
200    type Ux = u32;
201}
202#[doc = "`read()` method returns [`aircr::R`](R) reader structure"]
203impl crate::Readable for AircrSpec {}
204#[doc = "`write(|w| ..)` method takes [`aircr::W`](W) writer structure"]
205impl crate::Writable for AircrSpec {
206    type Safety = crate::Unsafe;
207    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
208    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
209}
210#[doc = "`reset()` method sets AIRCR to value 0xfa05_0000"]
211impl crate::Resettable for AircrSpec {
212    const RESET_VALUE: u32 = 0xfa05_0000;
213}
atsamd51g/system_control/aircr.rs

atsamd51g/system_control/
aircr.rs
