1#[doc = "Register `INPUTCTRL` reader"]
2pub type R = crate::R<InputctrlSpec>;
3#[doc = "Register `INPUTCTRL` writer"]
4pub type W = crate::W<InputctrlSpec>;
5#[doc = "Positive Mux Input Selection\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7#[repr(u8)]
8pub enum Muxposselect {
9 #[doc = "0: ADC AIN0 Pin"]
10 Ain0 = 0,
11 #[doc = "1: ADC AIN1 Pin"]
12 Ain1 = 1,
13 #[doc = "2: ADC AIN2 Pin"]
14 Ain2 = 2,
15 #[doc = "3: ADC AIN3 Pin"]
16 Ain3 = 3,
17 #[doc = "4: ADC AIN4 Pin"]
18 Ain4 = 4,
19 #[doc = "5: ADC AIN5 Pin"]
20 Ain5 = 5,
21 #[doc = "6: ADC AIN6 Pin"]
22 Ain6 = 6,
23 #[doc = "7: ADC AIN7 Pin"]
24 Ain7 = 7,
25 #[doc = "8: ADC AIN8 Pin"]
26 Ain8 = 8,
27 #[doc = "9: ADC AIN9 Pin"]
28 Ain9 = 9,
29 #[doc = "10: ADC AIN10 Pin"]
30 Ain10 = 10,
31 #[doc = "11: ADC AIN11 Pin"]
32 Ain11 = 11,
33 #[doc = "12: ADC AIN12 Pin"]
34 Ain12 = 12,
35 #[doc = "13: ADC AIN13 Pin"]
36 Ain13 = 13,
37 #[doc = "14: ADC AIN14 Pin"]
38 Ain14 = 14,
39 #[doc = "15: ADC AIN15 Pin"]
40 Ain15 = 15,
41 #[doc = "24: 1/4 Scaled Core Supply"]
42 Scaledcorevcc = 24,
43 #[doc = "25: 1/4 Scaled VBAT Supply"]
44 Scaledvbat = 25,
45 #[doc = "26: 1/4 Scaled I/O Supply"]
46 Scalediovcc = 26,
47 #[doc = "27: Bandgap Voltage"]
48 Bandgap = 27,
49 #[doc = "28: Temperature Sensor TSENSP"]
50 Ptat = 28,
51 #[doc = "29: Temperature Sensor TSENSC"]
52 Ctat = 29,
53 #[doc = "30: DAC Output"]
54 Dac = 30,
55 #[doc = "31: PTC output (only on ADC0)"]
56 Ptc = 31,
57}
58impl From<Muxposselect> for u8 {
59 #[inline(always)]
60 fn from(variant: Muxposselect) -> Self {
61 variant as _
62 }
63}
64impl crate::FieldSpec for Muxposselect {
65 type Ux = u8;
66}
67impl crate::IsEnum for Muxposselect {}
68#[doc = "Field `MUXPOS` reader - Positive Mux Input Selection"]
69pub type MuxposR = crate::FieldReader<Muxposselect>;
70impl MuxposR {
71 #[doc = "Get enumerated values variant"]
72 #[inline(always)]
73 pub const fn variant(&self) -> Option<Muxposselect> {
74 match self.bits {
75 0 => Some(Muxposselect::Ain0),
76 1 => Some(Muxposselect::Ain1),
77 2 => Some(Muxposselect::Ain2),
78 3 => Some(Muxposselect::Ain3),
79 4 => Some(Muxposselect::Ain4),
80 5 => Some(Muxposselect::Ain5),
81 6 => Some(Muxposselect::Ain6),
82 7 => Some(Muxposselect::Ain7),
83 8 => Some(Muxposselect::Ain8),
84 9 => Some(Muxposselect::Ain9),
85 10 => Some(Muxposselect::Ain10),
86 11 => Some(Muxposselect::Ain11),
87 12 => Some(Muxposselect::Ain12),
88 13 => Some(Muxposselect::Ain13),
89 14 => Some(Muxposselect::Ain14),
90 15 => Some(Muxposselect::Ain15),
91 24 => Some(Muxposselect::Scaledcorevcc),
92 25 => Some(Muxposselect::Scaledvbat),
93 26 => Some(Muxposselect::Scalediovcc),
94 27 => Some(Muxposselect::Bandgap),
95 28 => Some(Muxposselect::Ptat),
96 29 => Some(Muxposselect::Ctat),
97 30 => Some(Muxposselect::Dac),
98 31 => Some(Muxposselect::Ptc),
99 _ => None,
100 }
101 }
102 #[doc = "ADC AIN0 Pin"]
103 #[inline(always)]
104 pub fn is_ain0(&self) -> bool {
105 *self == Muxposselect::Ain0
106 }
107 #[doc = "ADC AIN1 Pin"]
108 #[inline(always)]
109 pub fn is_ain1(&self) -> bool {
110 *self == Muxposselect::Ain1
111 }
112 #[doc = "ADC AIN2 Pin"]
113 #[inline(always)]
114 pub fn is_ain2(&self) -> bool {
115 *self == Muxposselect::Ain2
116 }
117 #[doc = "ADC AIN3 Pin"]
118 #[inline(always)]
119 pub fn is_ain3(&self) -> bool {
120 *self == Muxposselect::Ain3
121 }
122 #[doc = "ADC AIN4 Pin"]
123 #[inline(always)]
124 pub fn is_ain4(&self) -> bool {
125 *self == Muxposselect::Ain4
126 }
127 #[doc = "ADC AIN5 Pin"]
128 #[inline(always)]
129 pub fn is_ain5(&self) -> bool {
130 *self == Muxposselect::Ain5
131 }
132 #[doc = "ADC AIN6 Pin"]
133 #[inline(always)]
134 pub fn is_ain6(&self) -> bool {
135 *self == Muxposselect::Ain6
136 }
137 #[doc = "ADC AIN7 Pin"]
138 #[inline(always)]
139 pub fn is_ain7(&self) -> bool {
140 *self == Muxposselect::Ain7
141 }
142 #[doc = "ADC AIN8 Pin"]
143 #[inline(always)]
144 pub fn is_ain8(&self) -> bool {
145 *self == Muxposselect::Ain8
146 }
147 #[doc = "ADC AIN9 Pin"]
148 #[inline(always)]
149 pub fn is_ain9(&self) -> bool {
150 *self == Muxposselect::Ain9
151 }
152 #[doc = "ADC AIN10 Pin"]
153 #[inline(always)]
154 pub fn is_ain10(&self) -> bool {
155 *self == Muxposselect::Ain10
156 }
157 #[doc = "ADC AIN11 Pin"]
158 #[inline(always)]
159 pub fn is_ain11(&self) -> bool {
160 *self == Muxposselect::Ain11
161 }
162 #[doc = "ADC AIN12 Pin"]
163 #[inline(always)]
164 pub fn is_ain12(&self) -> bool {
165 *self == Muxposselect::Ain12
166 }
167 #[doc = "ADC AIN13 Pin"]
168 #[inline(always)]
169 pub fn is_ain13(&self) -> bool {
170 *self == Muxposselect::Ain13
171 }
172 #[doc = "ADC AIN14 Pin"]
173 #[inline(always)]
174 pub fn is_ain14(&self) -> bool {
175 *self == Muxposselect::Ain14
176 }
177 #[doc = "ADC AIN15 Pin"]
178 #[inline(always)]
179 pub fn is_ain15(&self) -> bool {
180 *self == Muxposselect::Ain15
181 }
182 #[doc = "1/4 Scaled Core Supply"]
183 #[inline(always)]
184 pub fn is_scaledcorevcc(&self) -> bool {
185 *self == Muxposselect::Scaledcorevcc
186 }
187 #[doc = "1/4 Scaled VBAT Supply"]
188 #[inline(always)]
189 pub fn is_scaledvbat(&self) -> bool {
190 *self == Muxposselect::Scaledvbat
191 }
192 #[doc = "1/4 Scaled I/O Supply"]
193 #[inline(always)]
194 pub fn is_scalediovcc(&self) -> bool {
195 *self == Muxposselect::Scalediovcc
196 }
197 #[doc = "Bandgap Voltage"]
198 #[inline(always)]
199 pub fn is_bandgap(&self) -> bool {
200 *self == Muxposselect::Bandgap
201 }
202 #[doc = "Temperature Sensor TSENSP"]
203 #[inline(always)]
204 pub fn is_ptat(&self) -> bool {
205 *self == Muxposselect::Ptat
206 }
207 #[doc = "Temperature Sensor TSENSC"]
208 #[inline(always)]
209 pub fn is_ctat(&self) -> bool {
210 *self == Muxposselect::Ctat
211 }
212 #[doc = "DAC Output"]
213 #[inline(always)]
214 pub fn is_dac(&self) -> bool {
215 *self == Muxposselect::Dac
216 }
217 #[doc = "PTC output (only on ADC0)"]
218 #[inline(always)]
219 pub fn is_ptc(&self) -> bool {
220 *self == Muxposselect::Ptc
221 }
222}
223#[doc = "Field `MUXPOS` writer - Positive Mux Input Selection"]
224pub type MuxposW<'a, REG> = crate::FieldWriter<'a, REG, 5, Muxposselect>;
225impl<'a, REG> MuxposW<'a, REG>
226where
227 REG: crate::Writable + crate::RegisterSpec,
228 REG::Ux: From<u8>,
229{
230 #[doc = "ADC AIN0 Pin"]
231 #[inline(always)]
232 pub fn ain0(self) -> &'a mut crate::W<REG> {
233 self.variant(Muxposselect::Ain0)
234 }
235 #[doc = "ADC AIN1 Pin"]
236 #[inline(always)]
237 pub fn ain1(self) -> &'a mut crate::W<REG> {
238 self.variant(Muxposselect::Ain1)
239 }
240 #[doc = "ADC AIN2 Pin"]
241 #[inline(always)]
242 pub fn ain2(self) -> &'a mut crate::W<REG> {
243 self.variant(Muxposselect::Ain2)
244 }
245 #[doc = "ADC AIN3 Pin"]
246 #[inline(always)]
247 pub fn ain3(self) -> &'a mut crate::W<REG> {
248 self.variant(Muxposselect::Ain3)
249 }
250 #[doc = "ADC AIN4 Pin"]
251 #[inline(always)]
252 pub fn ain4(self) -> &'a mut crate::W<REG> {
253 self.variant(Muxposselect::Ain4)
254 }
255 #[doc = "ADC AIN5 Pin"]
256 #[inline(always)]
257 pub fn ain5(self) -> &'a mut crate::W<REG> {
258 self.variant(Muxposselect::Ain5)
259 }
260 #[doc = "ADC AIN6 Pin"]
261 #[inline(always)]
262 pub fn ain6(self) -> &'a mut crate::W<REG> {
263 self.variant(Muxposselect::Ain6)
264 }
265 #[doc = "ADC AIN7 Pin"]
266 #[inline(always)]
267 pub fn ain7(self) -> &'a mut crate::W<REG> {
268 self.variant(Muxposselect::Ain7)
269 }
270 #[doc = "ADC AIN8 Pin"]
271 #[inline(always)]
272 pub fn ain8(self) -> &'a mut crate::W<REG> {
273 self.variant(Muxposselect::Ain8)
274 }
275 #[doc = "ADC AIN9 Pin"]
276 #[inline(always)]
277 pub fn ain9(self) -> &'a mut crate::W<REG> {
278 self.variant(Muxposselect::Ain9)
279 }
280 #[doc = "ADC AIN10 Pin"]
281 #[inline(always)]
282 pub fn ain10(self) -> &'a mut crate::W<REG> {
283 self.variant(Muxposselect::Ain10)
284 }
285 #[doc = "ADC AIN11 Pin"]
286 #[inline(always)]
287 pub fn ain11(self) -> &'a mut crate::W<REG> {
288 self.variant(Muxposselect::Ain11)
289 }
290 #[doc = "ADC AIN12 Pin"]
291 #[inline(always)]
292 pub fn ain12(self) -> &'a mut crate::W<REG> {
293 self.variant(Muxposselect::Ain12)
294 }
295 #[doc = "ADC AIN13 Pin"]
296 #[inline(always)]
297 pub fn ain13(self) -> &'a mut crate::W<REG> {
298 self.variant(Muxposselect::Ain13)
299 }
300 #[doc = "ADC AIN14 Pin"]
301 #[inline(always)]
302 pub fn ain14(self) -> &'a mut crate::W<REG> {
303 self.variant(Muxposselect::Ain14)
304 }
305 #[doc = "ADC AIN15 Pin"]
306 #[inline(always)]
307 pub fn ain15(self) -> &'a mut crate::W<REG> {
308 self.variant(Muxposselect::Ain15)
309 }
310 #[doc = "1/4 Scaled Core Supply"]
311 #[inline(always)]
312 pub fn scaledcorevcc(self) -> &'a mut crate::W<REG> {
313 self.variant(Muxposselect::Scaledcorevcc)
314 }
315 #[doc = "1/4 Scaled VBAT Supply"]
316 #[inline(always)]
317 pub fn scaledvbat(self) -> &'a mut crate::W<REG> {
318 self.variant(Muxposselect::Scaledvbat)
319 }
320 #[doc = "1/4 Scaled I/O Supply"]
321 #[inline(always)]
322 pub fn scalediovcc(self) -> &'a mut crate::W<REG> {
323 self.variant(Muxposselect::Scalediovcc)
324 }
325 #[doc = "Bandgap Voltage"]
326 #[inline(always)]
327 pub fn bandgap(self) -> &'a mut crate::W<REG> {
328 self.variant(Muxposselect::Bandgap)
329 }
330 #[doc = "Temperature Sensor TSENSP"]
331 #[inline(always)]
332 pub fn ptat(self) -> &'a mut crate::W<REG> {
333 self.variant(Muxposselect::Ptat)
334 }
335 #[doc = "Temperature Sensor TSENSC"]
336 #[inline(always)]
337 pub fn ctat(self) -> &'a mut crate::W<REG> {
338 self.variant(Muxposselect::Ctat)
339 }
340 #[doc = "DAC Output"]
341 #[inline(always)]
342 pub fn dac(self) -> &'a mut crate::W<REG> {
343 self.variant(Muxposselect::Dac)
344 }
345 #[doc = "PTC output (only on ADC0)"]
346 #[inline(always)]
347 pub fn ptc(self) -> &'a mut crate::W<REG> {
348 self.variant(Muxposselect::Ptc)
349 }
350}
351#[doc = "Field `DIFFMODE` reader - Differential Mode"]
352pub type DiffmodeR = crate::BitReader;
353#[doc = "Field `DIFFMODE` writer - Differential Mode"]
354pub type DiffmodeW<'a, REG> = crate::BitWriter<'a, REG>;
355#[doc = "Negative Mux Input Selection\n\nValue on reset: 0"]
356#[derive(Clone, Copy, Debug, PartialEq, Eq)]
357#[repr(u8)]
358pub enum Muxnegselect {
359 #[doc = "0: ADC AIN0 Pin"]
360 Ain0 = 0,
361 #[doc = "1: ADC AIN1 Pin"]
362 Ain1 = 1,
363 #[doc = "2: ADC AIN2 Pin"]
364 Ain2 = 2,
365 #[doc = "3: ADC AIN3 Pin"]
366 Ain3 = 3,
367 #[doc = "4: ADC AIN4 Pin"]
368 Ain4 = 4,
369 #[doc = "5: ADC AIN5 Pin"]
370 Ain5 = 5,
371 #[doc = "6: ADC AIN6 Pin"]
372 Ain6 = 6,
373 #[doc = "7: ADC AIN7 Pin"]
374 Ain7 = 7,
375 #[doc = "24: Internal Ground"]
376 Gnd = 24,
377}
378impl From<Muxnegselect> for u8 {
379 #[inline(always)]
380 fn from(variant: Muxnegselect) -> Self {
381 variant as _
382 }
383}
384impl crate::FieldSpec for Muxnegselect {
385 type Ux = u8;
386}
387impl crate::IsEnum for Muxnegselect {}
388#[doc = "Field `MUXNEG` reader - Negative Mux Input Selection"]
389pub type MuxnegR = crate::FieldReader<Muxnegselect>;
390impl MuxnegR {
391 #[doc = "Get enumerated values variant"]
392 #[inline(always)]
393 pub const fn variant(&self) -> Option<Muxnegselect> {
394 match self.bits {
395 0 => Some(Muxnegselect::Ain0),
396 1 => Some(Muxnegselect::Ain1),
397 2 => Some(Muxnegselect::Ain2),
398 3 => Some(Muxnegselect::Ain3),
399 4 => Some(Muxnegselect::Ain4),
400 5 => Some(Muxnegselect::Ain5),
401 6 => Some(Muxnegselect::Ain6),
402 7 => Some(Muxnegselect::Ain7),
403 24 => Some(Muxnegselect::Gnd),
404 _ => None,
405 }
406 }
407 #[doc = "ADC AIN0 Pin"]
408 #[inline(always)]
409 pub fn is_ain0(&self) -> bool {
410 *self == Muxnegselect::Ain0
411 }
412 #[doc = "ADC AIN1 Pin"]
413 #[inline(always)]
414 pub fn is_ain1(&self) -> bool {
415 *self == Muxnegselect::Ain1
416 }
417 #[doc = "ADC AIN2 Pin"]
418 #[inline(always)]
419 pub fn is_ain2(&self) -> bool {
420 *self == Muxnegselect::Ain2
421 }
422 #[doc = "ADC AIN3 Pin"]
423 #[inline(always)]
424 pub fn is_ain3(&self) -> bool {
425 *self == Muxnegselect::Ain3
426 }
427 #[doc = "ADC AIN4 Pin"]
428 #[inline(always)]
429 pub fn is_ain4(&self) -> bool {
430 *self == Muxnegselect::Ain4
431 }
432 #[doc = "ADC AIN5 Pin"]
433 #[inline(always)]
434 pub fn is_ain5(&self) -> bool {
435 *self == Muxnegselect::Ain5
436 }
437 #[doc = "ADC AIN6 Pin"]
438 #[inline(always)]
439 pub fn is_ain6(&self) -> bool {
440 *self == Muxnegselect::Ain6
441 }
442 #[doc = "ADC AIN7 Pin"]
443 #[inline(always)]
444 pub fn is_ain7(&self) -> bool {
445 *self == Muxnegselect::Ain7
446 }
447 #[doc = "Internal Ground"]
448 #[inline(always)]
449 pub fn is_gnd(&self) -> bool {
450 *self == Muxnegselect::Gnd
451 }
452}
453#[doc = "Field `MUXNEG` writer - Negative Mux Input Selection"]
454pub type MuxnegW<'a, REG> = crate::FieldWriter<'a, REG, 5, Muxnegselect>;
455impl<'a, REG> MuxnegW<'a, REG>
456where
457 REG: crate::Writable + crate::RegisterSpec,
458 REG::Ux: From<u8>,
459{
460 #[doc = "ADC AIN0 Pin"]
461 #[inline(always)]
462 pub fn ain0(self) -> &'a mut crate::W<REG> {
463 self.variant(Muxnegselect::Ain0)
464 }
465 #[doc = "ADC AIN1 Pin"]
466 #[inline(always)]
467 pub fn ain1(self) -> &'a mut crate::W<REG> {
468 self.variant(Muxnegselect::Ain1)
469 }
470 #[doc = "ADC AIN2 Pin"]
471 #[inline(always)]
472 pub fn ain2(self) -> &'a mut crate::W<REG> {
473 self.variant(Muxnegselect::Ain2)
474 }
475 #[doc = "ADC AIN3 Pin"]
476 #[inline(always)]
477 pub fn ain3(self) -> &'a mut crate::W<REG> {
478 self.variant(Muxnegselect::Ain3)
479 }
480 #[doc = "ADC AIN4 Pin"]
481 #[inline(always)]
482 pub fn ain4(self) -> &'a mut crate::W<REG> {
483 self.variant(Muxnegselect::Ain4)
484 }
485 #[doc = "ADC AIN5 Pin"]
486 #[inline(always)]
487 pub fn ain5(self) -> &'a mut crate::W<REG> {
488 self.variant(Muxnegselect::Ain5)
489 }
490 #[doc = "ADC AIN6 Pin"]
491 #[inline(always)]
492 pub fn ain6(self) -> &'a mut crate::W<REG> {
493 self.variant(Muxnegselect::Ain6)
494 }
495 #[doc = "ADC AIN7 Pin"]
496 #[inline(always)]
497 pub fn ain7(self) -> &'a mut crate::W<REG> {
498 self.variant(Muxnegselect::Ain7)
499 }
500 #[doc = "Internal Ground"]
501 #[inline(always)]
502 pub fn gnd(self) -> &'a mut crate::W<REG> {
503 self.variant(Muxnegselect::Gnd)
504 }
505}
506#[doc = "Field `DSEQSTOP` reader - Stop DMA Sequencing"]
507pub type DseqstopR = crate::BitReader;
508#[doc = "Field `DSEQSTOP` writer - Stop DMA Sequencing"]
509pub type DseqstopW<'a, REG> = crate::BitWriter<'a, REG>;
510impl R {
511 #[doc = "Bits 0:4 - Positive Mux Input Selection"]
512 #[inline(always)]
513 pub fn muxpos(&self) -> MuxposR {
514 MuxposR::new((self.bits & 0x1f) as u8)
515 }
516 #[doc = "Bit 7 - Differential Mode"]
517 #[inline(always)]
518 pub fn diffmode(&self) -> DiffmodeR {
519 DiffmodeR::new(((self.bits >> 7) & 1) != 0)
520 }
521 #[doc = "Bits 8:12 - Negative Mux Input Selection"]
522 #[inline(always)]
523 pub fn muxneg(&self) -> MuxnegR {
524 MuxnegR::new(((self.bits >> 8) & 0x1f) as u8)
525 }
526 #[doc = "Bit 15 - Stop DMA Sequencing"]
527 #[inline(always)]
528 pub fn dseqstop(&self) -> DseqstopR {
529 DseqstopR::new(((self.bits >> 15) & 1) != 0)
530 }
531}
532impl W {
533 #[doc = "Bits 0:4 - Positive Mux Input Selection"]
534 #[inline(always)]
535 #[must_use]
536 pub fn muxpos(&mut self) -> MuxposW<InputctrlSpec> {
537 MuxposW::new(self, 0)
538 }
539 #[doc = "Bit 7 - Differential Mode"]
540 #[inline(always)]
541 #[must_use]
542 pub fn diffmode(&mut self) -> DiffmodeW<InputctrlSpec> {
543 DiffmodeW::new(self, 7)
544 }
545 #[doc = "Bits 8:12 - Negative Mux Input Selection"]
546 #[inline(always)]
547 #[must_use]
548 pub fn muxneg(&mut self) -> MuxnegW<InputctrlSpec> {
549 MuxnegW::new(self, 8)
550 }
551 #[doc = "Bit 15 - Stop DMA Sequencing"]
552 #[inline(always)]
553 #[must_use]
554 pub fn dseqstop(&mut self) -> DseqstopW<InputctrlSpec> {
555 DseqstopW::new(self, 15)
556 }
557}
558#[doc = "Input Control\n\nYou can [`read`](crate::Reg::read) this register and get [`inputctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inputctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
559pub struct InputctrlSpec;
560impl crate::RegisterSpec for InputctrlSpec {
561 type Ux = u16;
562}
563#[doc = "`read()` method returns [`inputctrl::R`](R) reader structure"]
564impl crate::Readable for InputctrlSpec {}
565#[doc = "`write(|w| ..)` method takes [`inputctrl::W`](W) writer structure"]
566impl crate::Writable for InputctrlSpec {
567 type Safety = crate::Unsafe;
568 const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
569 const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
570}
571#[doc = "`reset()` method sets INPUTCTRL to value 0"]
572impl crate::Resettable for InputctrlSpec {
573 const RESET_VALUE: u16 = 0;
574}