atsamd51g/core_debug/
demcr.rs

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1#[doc = "Register `DEMCR` reader"]
2pub type R = crate::R<DemcrSpec>;
3#[doc = "Register `DEMCR` writer"]
4pub type W = crate::W<DemcrSpec>;
5#[doc = "Field `VC_CORERESET` reader - "]
6pub type VcCoreresetR = crate::BitReader;
7#[doc = "Field `VC_CORERESET` writer - "]
8pub type VcCoreresetW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `VC_MMERR` reader - "]
10pub type VcMmerrR = crate::BitReader;
11#[doc = "Field `VC_MMERR` writer - "]
12pub type VcMmerrW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `VC_NOCPERR` reader - "]
14pub type VcNocperrR = crate::BitReader;
15#[doc = "Field `VC_NOCPERR` writer - "]
16pub type VcNocperrW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `VC_CHKERR` reader - "]
18pub type VcChkerrR = crate::BitReader;
19#[doc = "Field `VC_CHKERR` writer - "]
20pub type VcChkerrW<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `VC_STATERR` reader - "]
22pub type VcStaterrR = crate::BitReader;
23#[doc = "Field `VC_STATERR` writer - "]
24pub type VcStaterrW<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `VC_BUSERR` reader - "]
26pub type VcBuserrR = crate::BitReader;
27#[doc = "Field `VC_BUSERR` writer - "]
28pub type VcBuserrW<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `VC_INTERR` reader - "]
30pub type VcInterrR = crate::BitReader;
31#[doc = "Field `VC_INTERR` writer - "]
32pub type VcInterrW<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `VC_HARDERR` reader - "]
34pub type VcHarderrR = crate::BitReader;
35#[doc = "Field `VC_HARDERR` writer - "]
36pub type VcHarderrW<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `MON_EN` reader - "]
38pub type MonEnR = crate::BitReader;
39#[doc = "Field `MON_EN` writer - "]
40pub type MonEnW<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `MON_PEND` reader - "]
42pub type MonPendR = crate::BitReader;
43#[doc = "Field `MON_PEND` writer - "]
44pub type MonPendW<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `MON_STEP` reader - "]
46pub type MonStepR = crate::BitReader;
47#[doc = "Field `MON_STEP` writer - "]
48pub type MonStepW<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `MON_REQ` reader - "]
50pub type MonReqR = crate::BitReader;
51#[doc = "Field `MON_REQ` writer - "]
52pub type MonReqW<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `TRCENA` reader - "]
54pub type TrcenaR = crate::BitReader;
55#[doc = "Field `TRCENA` writer - "]
56pub type TrcenaW<'a, REG> = crate::BitWriter<'a, REG>;
57impl R {
58    #[doc = "Bit 0"]
59    #[inline(always)]
60    pub fn vc_corereset(&self) -> VcCoreresetR {
61        VcCoreresetR::new((self.bits & 1) != 0)
62    }
63    #[doc = "Bit 4"]
64    #[inline(always)]
65    pub fn vc_mmerr(&self) -> VcMmerrR {
66        VcMmerrR::new(((self.bits >> 4) & 1) != 0)
67    }
68    #[doc = "Bit 5"]
69    #[inline(always)]
70    pub fn vc_nocperr(&self) -> VcNocperrR {
71        VcNocperrR::new(((self.bits >> 5) & 1) != 0)
72    }
73    #[doc = "Bit 6"]
74    #[inline(always)]
75    pub fn vc_chkerr(&self) -> VcChkerrR {
76        VcChkerrR::new(((self.bits >> 6) & 1) != 0)
77    }
78    #[doc = "Bit 7"]
79    #[inline(always)]
80    pub fn vc_staterr(&self) -> VcStaterrR {
81        VcStaterrR::new(((self.bits >> 7) & 1) != 0)
82    }
83    #[doc = "Bit 8"]
84    #[inline(always)]
85    pub fn vc_buserr(&self) -> VcBuserrR {
86        VcBuserrR::new(((self.bits >> 8) & 1) != 0)
87    }
88    #[doc = "Bit 9"]
89    #[inline(always)]
90    pub fn vc_interr(&self) -> VcInterrR {
91        VcInterrR::new(((self.bits >> 9) & 1) != 0)
92    }
93    #[doc = "Bit 10"]
94    #[inline(always)]
95    pub fn vc_harderr(&self) -> VcHarderrR {
96        VcHarderrR::new(((self.bits >> 10) & 1) != 0)
97    }
98    #[doc = "Bit 16"]
99    #[inline(always)]
100    pub fn mon_en(&self) -> MonEnR {
101        MonEnR::new(((self.bits >> 16) & 1) != 0)
102    }
103    #[doc = "Bit 17"]
104    #[inline(always)]
105    pub fn mon_pend(&self) -> MonPendR {
106        MonPendR::new(((self.bits >> 17) & 1) != 0)
107    }
108    #[doc = "Bit 18"]
109    #[inline(always)]
110    pub fn mon_step(&self) -> MonStepR {
111        MonStepR::new(((self.bits >> 18) & 1) != 0)
112    }
113    #[doc = "Bit 19"]
114    #[inline(always)]
115    pub fn mon_req(&self) -> MonReqR {
116        MonReqR::new(((self.bits >> 19) & 1) != 0)
117    }
118    #[doc = "Bit 24"]
119    #[inline(always)]
120    pub fn trcena(&self) -> TrcenaR {
121        TrcenaR::new(((self.bits >> 24) & 1) != 0)
122    }
123}
124impl W {
125    #[doc = "Bit 0"]
126    #[inline(always)]
127    #[must_use]
128    pub fn vc_corereset(&mut self) -> VcCoreresetW<DemcrSpec> {
129        VcCoreresetW::new(self, 0)
130    }
131    #[doc = "Bit 4"]
132    #[inline(always)]
133    #[must_use]
134    pub fn vc_mmerr(&mut self) -> VcMmerrW<DemcrSpec> {
135        VcMmerrW::new(self, 4)
136    }
137    #[doc = "Bit 5"]
138    #[inline(always)]
139    #[must_use]
140    pub fn vc_nocperr(&mut self) -> VcNocperrW<DemcrSpec> {
141        VcNocperrW::new(self, 5)
142    }
143    #[doc = "Bit 6"]
144    #[inline(always)]
145    #[must_use]
146    pub fn vc_chkerr(&mut self) -> VcChkerrW<DemcrSpec> {
147        VcChkerrW::new(self, 6)
148    }
149    #[doc = "Bit 7"]
150    #[inline(always)]
151    #[must_use]
152    pub fn vc_staterr(&mut self) -> VcStaterrW<DemcrSpec> {
153        VcStaterrW::new(self, 7)
154    }
155    #[doc = "Bit 8"]
156    #[inline(always)]
157    #[must_use]
158    pub fn vc_buserr(&mut self) -> VcBuserrW<DemcrSpec> {
159        VcBuserrW::new(self, 8)
160    }
161    #[doc = "Bit 9"]
162    #[inline(always)]
163    #[must_use]
164    pub fn vc_interr(&mut self) -> VcInterrW<DemcrSpec> {
165        VcInterrW::new(self, 9)
166    }
167    #[doc = "Bit 10"]
168    #[inline(always)]
169    #[must_use]
170    pub fn vc_harderr(&mut self) -> VcHarderrW<DemcrSpec> {
171        VcHarderrW::new(self, 10)
172    }
173    #[doc = "Bit 16"]
174    #[inline(always)]
175    #[must_use]
176    pub fn mon_en(&mut self) -> MonEnW<DemcrSpec> {
177        MonEnW::new(self, 16)
178    }
179    #[doc = "Bit 17"]
180    #[inline(always)]
181    #[must_use]
182    pub fn mon_pend(&mut self) -> MonPendW<DemcrSpec> {
183        MonPendW::new(self, 17)
184    }
185    #[doc = "Bit 18"]
186    #[inline(always)]
187    #[must_use]
188    pub fn mon_step(&mut self) -> MonStepW<DemcrSpec> {
189        MonStepW::new(self, 18)
190    }
191    #[doc = "Bit 19"]
192    #[inline(always)]
193    #[must_use]
194    pub fn mon_req(&mut self) -> MonReqW<DemcrSpec> {
195        MonReqW::new(self, 19)
196    }
197    #[doc = "Bit 24"]
198    #[inline(always)]
199    #[must_use]
200    pub fn trcena(&mut self) -> TrcenaW<DemcrSpec> {
201        TrcenaW::new(self, 24)
202    }
203}
204#[doc = "Debug Exception and Monitor Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`demcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`demcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
205pub struct DemcrSpec;
206impl crate::RegisterSpec for DemcrSpec {
207    type Ux = u32;
208}
209#[doc = "`read()` method returns [`demcr::R`](R) reader structure"]
210impl crate::Readable for DemcrSpec {}
211#[doc = "`write(|w| ..)` method takes [`demcr::W`](W) writer structure"]
212impl crate::Writable for DemcrSpec {
213    type Safety = crate::Unsafe;
214    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
215    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
216}
217#[doc = "`reset()` method sets DEMCR to value 0"]
218impl crate::Resettable for DemcrSpec {
219    const RESET_VALUE: u32 = 0;
220}
atsamd51g/core_debug/demcr.rs

atsamd51g/core_debug/
demcr.rs
