atsamd51g/qspi/
instrframe.rs

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1#[doc = "Register `INSTRFRAME` reader"]
2pub type R = crate::R<InstrframeSpec>;
3#[doc = "Register `INSTRFRAME` writer"]
4pub type W = crate::W<InstrframeSpec>;
5#[doc = "Instruction Code, Address, Option Code and Data Width\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7#[repr(u8)]
8pub enum Widthselect {
9    #[doc = "0: Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI"]
10    SingleBitSpi = 0,
11    #[doc = "1: Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI"]
12    DualOutput = 1,
13    #[doc = "2: Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI"]
14    QuadOutput = 2,
15    #[doc = "3: Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI"]
16    DualIo = 3,
17    #[doc = "4: Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI"]
18    QuadIo = 4,
19    #[doc = "5: Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI"]
20    DualCmd = 5,
21    #[doc = "6: Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI"]
22    QuadCmd = 6,
23}
24impl From<Widthselect> for u8 {
25    #[inline(always)]
26    fn from(variant: Widthselect) -> Self {
27        variant as _
28    }
29}
30impl crate::FieldSpec for Widthselect {
31    type Ux = u8;
32}
33impl crate::IsEnum for Widthselect {}
34#[doc = "Field `WIDTH` reader - Instruction Code, Address, Option Code and Data Width"]
35pub type WidthR = crate::FieldReader<Widthselect>;
36impl WidthR {
37    #[doc = "Get enumerated values variant"]
38    #[inline(always)]
39    pub const fn variant(&self) -> Option<Widthselect> {
40        match self.bits {
41            0 => Some(Widthselect::SingleBitSpi),
42            1 => Some(Widthselect::DualOutput),
43            2 => Some(Widthselect::QuadOutput),
44            3 => Some(Widthselect::DualIo),
45            4 => Some(Widthselect::QuadIo),
46            5 => Some(Widthselect::DualCmd),
47            6 => Some(Widthselect::QuadCmd),
48            _ => None,
49        }
50    }
51    #[doc = "Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI"]
52    #[inline(always)]
53    pub fn is_single_bit_spi(&self) -> bool {
54        *self == Widthselect::SingleBitSpi
55    }
56    #[doc = "Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI"]
57    #[inline(always)]
58    pub fn is_dual_output(&self) -> bool {
59        *self == Widthselect::DualOutput
60    }
61    #[doc = "Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI"]
62    #[inline(always)]
63    pub fn is_quad_output(&self) -> bool {
64        *self == Widthselect::QuadOutput
65    }
66    #[doc = "Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI"]
67    #[inline(always)]
68    pub fn is_dual_io(&self) -> bool {
69        *self == Widthselect::DualIo
70    }
71    #[doc = "Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI"]
72    #[inline(always)]
73    pub fn is_quad_io(&self) -> bool {
74        *self == Widthselect::QuadIo
75    }
76    #[doc = "Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI"]
77    #[inline(always)]
78    pub fn is_dual_cmd(&self) -> bool {
79        *self == Widthselect::DualCmd
80    }
81    #[doc = "Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI"]
82    #[inline(always)]
83    pub fn is_quad_cmd(&self) -> bool {
84        *self == Widthselect::QuadCmd
85    }
86}
87#[doc = "Field `WIDTH` writer - Instruction Code, Address, Option Code and Data Width"]
88pub type WidthW<'a, REG> = crate::FieldWriter<'a, REG, 3, Widthselect>;
89impl<'a, REG> WidthW<'a, REG>
90where
91    REG: crate::Writable + crate::RegisterSpec,
92    REG::Ux: From<u8>,
93{
94    #[doc = "Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI"]
95    #[inline(always)]
96    pub fn single_bit_spi(self) -> &'a mut crate::W<REG> {
97        self.variant(Widthselect::SingleBitSpi)
98    }
99    #[doc = "Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI"]
100    #[inline(always)]
101    pub fn dual_output(self) -> &'a mut crate::W<REG> {
102        self.variant(Widthselect::DualOutput)
103    }
104    #[doc = "Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI"]
105    #[inline(always)]
106    pub fn quad_output(self) -> &'a mut crate::W<REG> {
107        self.variant(Widthselect::QuadOutput)
108    }
109    #[doc = "Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI"]
110    #[inline(always)]
111    pub fn dual_io(self) -> &'a mut crate::W<REG> {
112        self.variant(Widthselect::DualIo)
113    }
114    #[doc = "Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI"]
115    #[inline(always)]
116    pub fn quad_io(self) -> &'a mut crate::W<REG> {
117        self.variant(Widthselect::QuadIo)
118    }
119    #[doc = "Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI"]
120    #[inline(always)]
121    pub fn dual_cmd(self) -> &'a mut crate::W<REG> {
122        self.variant(Widthselect::DualCmd)
123    }
124    #[doc = "Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI"]
125    #[inline(always)]
126    pub fn quad_cmd(self) -> &'a mut crate::W<REG> {
127        self.variant(Widthselect::QuadCmd)
128    }
129}
130#[doc = "Field `INSTREN` reader - Instruction Enable"]
131pub type InstrenR = crate::BitReader;
132#[doc = "Field `INSTREN` writer - Instruction Enable"]
133pub type InstrenW<'a, REG> = crate::BitWriter<'a, REG>;
134#[doc = "Field `ADDREN` reader - Address Enable"]
135pub type AddrenR = crate::BitReader;
136#[doc = "Field `ADDREN` writer - Address Enable"]
137pub type AddrenW<'a, REG> = crate::BitWriter<'a, REG>;
138#[doc = "Field `OPTCODEEN` reader - Option Enable"]
139pub type OptcodeenR = crate::BitReader;
140#[doc = "Field `OPTCODEEN` writer - Option Enable"]
141pub type OptcodeenW<'a, REG> = crate::BitWriter<'a, REG>;
142#[doc = "Field `DATAEN` reader - Data Enable"]
143pub type DataenR = crate::BitReader;
144#[doc = "Field `DATAEN` writer - Data Enable"]
145pub type DataenW<'a, REG> = crate::BitWriter<'a, REG>;
146#[doc = "Option Code Length\n\nValue on reset: 0"]
147#[derive(Clone, Copy, Debug, PartialEq, Eq)]
148#[repr(u8)]
149pub enum Optcodelenselect {
150    #[doc = "0: 1-bit length option code"]
151    _1bit = 0,
152    #[doc = "1: 2-bits length option code"]
153    _2bits = 1,
154    #[doc = "2: 4-bits length option code"]
155    _4bits = 2,
156    #[doc = "3: 8-bits length option code"]
157    _8bits = 3,
158}
159impl From<Optcodelenselect> for u8 {
160    #[inline(always)]
161    fn from(variant: Optcodelenselect) -> Self {
162        variant as _
163    }
164}
165impl crate::FieldSpec for Optcodelenselect {
166    type Ux = u8;
167}
168impl crate::IsEnum for Optcodelenselect {}
169#[doc = "Field `OPTCODELEN` reader - Option Code Length"]
170pub type OptcodelenR = crate::FieldReader<Optcodelenselect>;
171impl OptcodelenR {
172    #[doc = "Get enumerated values variant"]
173    #[inline(always)]
174    pub const fn variant(&self) -> Optcodelenselect {
175        match self.bits {
176            0 => Optcodelenselect::_1bit,
177            1 => Optcodelenselect::_2bits,
178            2 => Optcodelenselect::_4bits,
179            3 => Optcodelenselect::_8bits,
180            _ => unreachable!(),
181        }
182    }
183    #[doc = "1-bit length option code"]
184    #[inline(always)]
185    pub fn is_1bit(&self) -> bool {
186        *self == Optcodelenselect::_1bit
187    }
188    #[doc = "2-bits length option code"]
189    #[inline(always)]
190    pub fn is_2bits(&self) -> bool {
191        *self == Optcodelenselect::_2bits
192    }
193    #[doc = "4-bits length option code"]
194    #[inline(always)]
195    pub fn is_4bits(&self) -> bool {
196        *self == Optcodelenselect::_4bits
197    }
198    #[doc = "8-bits length option code"]
199    #[inline(always)]
200    pub fn is_8bits(&self) -> bool {
201        *self == Optcodelenselect::_8bits
202    }
203}
204#[doc = "Field `OPTCODELEN` writer - Option Code Length"]
205pub type OptcodelenW<'a, REG> = crate::FieldWriter<'a, REG, 2, Optcodelenselect, crate::Safe>;
206impl<'a, REG> OptcodelenW<'a, REG>
207where
208    REG: crate::Writable + crate::RegisterSpec,
209    REG::Ux: From<u8>,
210{
211    #[doc = "1-bit length option code"]
212    #[inline(always)]
213    pub fn _1bit(self) -> &'a mut crate::W<REG> {
214        self.variant(Optcodelenselect::_1bit)
215    }
216    #[doc = "2-bits length option code"]
217    #[inline(always)]
218    pub fn _2bits(self) -> &'a mut crate::W<REG> {
219        self.variant(Optcodelenselect::_2bits)
220    }
221    #[doc = "4-bits length option code"]
222    #[inline(always)]
223    pub fn _4bits(self) -> &'a mut crate::W<REG> {
224        self.variant(Optcodelenselect::_4bits)
225    }
226    #[doc = "8-bits length option code"]
227    #[inline(always)]
228    pub fn _8bits(self) -> &'a mut crate::W<REG> {
229        self.variant(Optcodelenselect::_8bits)
230    }
231}
232#[doc = "Address Length\n\nValue on reset: 0"]
233#[derive(Clone, Copy, Debug, PartialEq, Eq)]
234pub enum Addrlenselect {
235    #[doc = "0: 24-bits address length"]
236    _24bits = 0,
237    #[doc = "1: 32-bits address length"]
238    _32bits = 1,
239}
240impl From<Addrlenselect> for bool {
241    #[inline(always)]
242    fn from(variant: Addrlenselect) -> Self {
243        variant as u8 != 0
244    }
245}
246#[doc = "Field `ADDRLEN` reader - Address Length"]
247pub type AddrlenR = crate::BitReader<Addrlenselect>;
248impl AddrlenR {
249    #[doc = "Get enumerated values variant"]
250    #[inline(always)]
251    pub const fn variant(&self) -> Addrlenselect {
252        match self.bits {
253            false => Addrlenselect::_24bits,
254            true => Addrlenselect::_32bits,
255        }
256    }
257    #[doc = "24-bits address length"]
258    #[inline(always)]
259    pub fn is_24bits(&self) -> bool {
260        *self == Addrlenselect::_24bits
261    }
262    #[doc = "32-bits address length"]
263    #[inline(always)]
264    pub fn is_32bits(&self) -> bool {
265        *self == Addrlenselect::_32bits
266    }
267}
268#[doc = "Field `ADDRLEN` writer - Address Length"]
269pub type AddrlenW<'a, REG> = crate::BitWriter<'a, REG, Addrlenselect>;
270impl<'a, REG> AddrlenW<'a, REG>
271where
272    REG: crate::Writable + crate::RegisterSpec,
273{
274    #[doc = "24-bits address length"]
275    #[inline(always)]
276    pub fn _24bits(self) -> &'a mut crate::W<REG> {
277        self.variant(Addrlenselect::_24bits)
278    }
279    #[doc = "32-bits address length"]
280    #[inline(always)]
281    pub fn _32bits(self) -> &'a mut crate::W<REG> {
282        self.variant(Addrlenselect::_32bits)
283    }
284}
285#[doc = "Data Transfer Type\n\nValue on reset: 0"]
286#[derive(Clone, Copy, Debug, PartialEq, Eq)]
287#[repr(u8)]
288pub enum Tfrtypeselect {
289    #[doc = "0: Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial flash memory is not possible."]
290    Read = 0,
291    #[doc = "1: Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial flash memory is possible."]
292    Readmemory = 1,
293    #[doc = "2: Write transfer into the serial memory.Scrambling is not performed."]
294    Write = 2,
295    #[doc = "3: Write data transfer into the serial memory.If enabled, scrambling is performed."]
296    Writememory = 3,
297}
298impl From<Tfrtypeselect> for u8 {
299    #[inline(always)]
300    fn from(variant: Tfrtypeselect) -> Self {
301        variant as _
302    }
303}
304impl crate::FieldSpec for Tfrtypeselect {
305    type Ux = u8;
306}
307impl crate::IsEnum for Tfrtypeselect {}
308#[doc = "Field `TFRTYPE` reader - Data Transfer Type"]
309pub type TfrtypeR = crate::FieldReader<Tfrtypeselect>;
310impl TfrtypeR {
311    #[doc = "Get enumerated values variant"]
312    #[inline(always)]
313    pub const fn variant(&self) -> Tfrtypeselect {
314        match self.bits {
315            0 => Tfrtypeselect::Read,
316            1 => Tfrtypeselect::Readmemory,
317            2 => Tfrtypeselect::Write,
318            3 => Tfrtypeselect::Writememory,
319            _ => unreachable!(),
320        }
321    }
322    #[doc = "Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial flash memory is not possible."]
323    #[inline(always)]
324    pub fn is_read(&self) -> bool {
325        *self == Tfrtypeselect::Read
326    }
327    #[doc = "Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial flash memory is possible."]
328    #[inline(always)]
329    pub fn is_readmemory(&self) -> bool {
330        *self == Tfrtypeselect::Readmemory
331    }
332    #[doc = "Write transfer into the serial memory.Scrambling is not performed."]
333    #[inline(always)]
334    pub fn is_write(&self) -> bool {
335        *self == Tfrtypeselect::Write
336    }
337    #[doc = "Write data transfer into the serial memory.If enabled, scrambling is performed."]
338    #[inline(always)]
339    pub fn is_writememory(&self) -> bool {
340        *self == Tfrtypeselect::Writememory
341    }
342}
343#[doc = "Field `TFRTYPE` writer - Data Transfer Type"]
344pub type TfrtypeW<'a, REG> = crate::FieldWriter<'a, REG, 2, Tfrtypeselect, crate::Safe>;
345impl<'a, REG> TfrtypeW<'a, REG>
346where
347    REG: crate::Writable + crate::RegisterSpec,
348    REG::Ux: From<u8>,
349{
350    #[doc = "Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial flash memory is not possible."]
351    #[inline(always)]
352    pub fn read(self) -> &'a mut crate::W<REG> {
353        self.variant(Tfrtypeselect::Read)
354    }
355    #[doc = "Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial flash memory is possible."]
356    #[inline(always)]
357    pub fn readmemory(self) -> &'a mut crate::W<REG> {
358        self.variant(Tfrtypeselect::Readmemory)
359    }
360    #[doc = "Write transfer into the serial memory.Scrambling is not performed."]
361    #[inline(always)]
362    pub fn write(self) -> &'a mut crate::W<REG> {
363        self.variant(Tfrtypeselect::Write)
364    }
365    #[doc = "Write data transfer into the serial memory.If enabled, scrambling is performed."]
366    #[inline(always)]
367    pub fn writememory(self) -> &'a mut crate::W<REG> {
368        self.variant(Tfrtypeselect::Writememory)
369    }
370}
371#[doc = "Field `CRMODE` reader - Continuous Read Mode"]
372pub type CrmodeR = crate::BitReader;
373#[doc = "Field `CRMODE` writer - Continuous Read Mode"]
374pub type CrmodeW<'a, REG> = crate::BitWriter<'a, REG>;
375#[doc = "Field `DDREN` reader - Double Data Rate Enable"]
376pub type DdrenR = crate::BitReader;
377#[doc = "Field `DDREN` writer - Double Data Rate Enable"]
378pub type DdrenW<'a, REG> = crate::BitWriter<'a, REG>;
379#[doc = "Field `DUMMYLEN` reader - Dummy Cycles Length"]
380pub type DummylenR = crate::FieldReader;
381#[doc = "Field `DUMMYLEN` writer - Dummy Cycles Length"]
382pub type DummylenW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
383impl R {
384    #[doc = "Bits 0:2 - Instruction Code, Address, Option Code and Data Width"]
385    #[inline(always)]
386    pub fn width(&self) -> WidthR {
387        WidthR::new((self.bits & 7) as u8)
388    }
389    #[doc = "Bit 4 - Instruction Enable"]
390    #[inline(always)]
391    pub fn instren(&self) -> InstrenR {
392        InstrenR::new(((self.bits >> 4) & 1) != 0)
393    }
394    #[doc = "Bit 5 - Address Enable"]
395    #[inline(always)]
396    pub fn addren(&self) -> AddrenR {
397        AddrenR::new(((self.bits >> 5) & 1) != 0)
398    }
399    #[doc = "Bit 6 - Option Enable"]
400    #[inline(always)]
401    pub fn optcodeen(&self) -> OptcodeenR {
402        OptcodeenR::new(((self.bits >> 6) & 1) != 0)
403    }
404    #[doc = "Bit 7 - Data Enable"]
405    #[inline(always)]
406    pub fn dataen(&self) -> DataenR {
407        DataenR::new(((self.bits >> 7) & 1) != 0)
408    }
409    #[doc = "Bits 8:9 - Option Code Length"]
410    #[inline(always)]
411    pub fn optcodelen(&self) -> OptcodelenR {
412        OptcodelenR::new(((self.bits >> 8) & 3) as u8)
413    }
414    #[doc = "Bit 10 - Address Length"]
415    #[inline(always)]
416    pub fn addrlen(&self) -> AddrlenR {
417        AddrlenR::new(((self.bits >> 10) & 1) != 0)
418    }
419    #[doc = "Bits 12:13 - Data Transfer Type"]
420    #[inline(always)]
421    pub fn tfrtype(&self) -> TfrtypeR {
422        TfrtypeR::new(((self.bits >> 12) & 3) as u8)
423    }
424    #[doc = "Bit 14 - Continuous Read Mode"]
425    #[inline(always)]
426    pub fn crmode(&self) -> CrmodeR {
427        CrmodeR::new(((self.bits >> 14) & 1) != 0)
428    }
429    #[doc = "Bit 15 - Double Data Rate Enable"]
430    #[inline(always)]
431    pub fn ddren(&self) -> DdrenR {
432        DdrenR::new(((self.bits >> 15) & 1) != 0)
433    }
434    #[doc = "Bits 16:20 - Dummy Cycles Length"]
435    #[inline(always)]
436    pub fn dummylen(&self) -> DummylenR {
437        DummylenR::new(((self.bits >> 16) & 0x1f) as u8)
438    }
439}
440impl W {
441    #[doc = "Bits 0:2 - Instruction Code, Address, Option Code and Data Width"]
442    #[inline(always)]
443    #[must_use]
444    pub fn width(&mut self) -> WidthW<InstrframeSpec> {
445        WidthW::new(self, 0)
446    }
447    #[doc = "Bit 4 - Instruction Enable"]
448    #[inline(always)]
449    #[must_use]
450    pub fn instren(&mut self) -> InstrenW<InstrframeSpec> {
451        InstrenW::new(self, 4)
452    }
453    #[doc = "Bit 5 - Address Enable"]
454    #[inline(always)]
455    #[must_use]
456    pub fn addren(&mut self) -> AddrenW<InstrframeSpec> {
457        AddrenW::new(self, 5)
458    }
459    #[doc = "Bit 6 - Option Enable"]
460    #[inline(always)]
461    #[must_use]
462    pub fn optcodeen(&mut self) -> OptcodeenW<InstrframeSpec> {
463        OptcodeenW::new(self, 6)
464    }
465    #[doc = "Bit 7 - Data Enable"]
466    #[inline(always)]
467    #[must_use]
468    pub fn dataen(&mut self) -> DataenW<InstrframeSpec> {
469        DataenW::new(self, 7)
470    }
471    #[doc = "Bits 8:9 - Option Code Length"]
472    #[inline(always)]
473    #[must_use]
474    pub fn optcodelen(&mut self) -> OptcodelenW<InstrframeSpec> {
475        OptcodelenW::new(self, 8)
476    }
477    #[doc = "Bit 10 - Address Length"]
478    #[inline(always)]
479    #[must_use]
480    pub fn addrlen(&mut self) -> AddrlenW<InstrframeSpec> {
481        AddrlenW::new(self, 10)
482    }
483    #[doc = "Bits 12:13 - Data Transfer Type"]
484    #[inline(always)]
485    #[must_use]
486    pub fn tfrtype(&mut self) -> TfrtypeW<InstrframeSpec> {
487        TfrtypeW::new(self, 12)
488    }
489    #[doc = "Bit 14 - Continuous Read Mode"]
490    #[inline(always)]
491    #[must_use]
492    pub fn crmode(&mut self) -> CrmodeW<InstrframeSpec> {
493        CrmodeW::new(self, 14)
494    }
495    #[doc = "Bit 15 - Double Data Rate Enable"]
496    #[inline(always)]
497    #[must_use]
498    pub fn ddren(&mut self) -> DdrenW<InstrframeSpec> {
499        DdrenW::new(self, 15)
500    }
501    #[doc = "Bits 16:20 - Dummy Cycles Length"]
502    #[inline(always)]
503    #[must_use]
504    pub fn dummylen(&mut self) -> DummylenW<InstrframeSpec> {
505        DummylenW::new(self, 16)
506    }
507}
508#[doc = "Instruction Frame\n\nYou can [`read`](crate::Reg::read) this register and get [`instrframe::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`instrframe::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
509pub struct InstrframeSpec;
510impl crate::RegisterSpec for InstrframeSpec {
511    type Ux = u32;
512}
513#[doc = "`read()` method returns [`instrframe::R`](R) reader structure"]
514impl crate::Readable for InstrframeSpec {}
515#[doc = "`write(|w| ..)` method takes [`instrframe::W`](W) writer structure"]
516impl crate::Writable for InstrframeSpec {
517    type Safety = crate::Unsafe;
518    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
519    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
520}
521#[doc = "`reset()` method sets INSTRFRAME to value 0"]
522impl crate::Resettable for InstrframeSpec {
523    const RESET_VALUE: u32 = 0;
524}
atsamd51g/qspi/instrframe.rs

atsamd51g/qspi/
instrframe.rs
