atsamd51g/dmac/
crcctrl.rs

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1#[doc = "Register `CRCCTRL` reader"]
2pub type R = crate::R<CrcctrlSpec>;
3#[doc = "Register `CRCCTRL` writer"]
4pub type W = crate::W<CrcctrlSpec>;
5#[doc = "CRC Beat Size\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7#[repr(u8)]
8pub enum Crcbeatsizeselect {
9    #[doc = "0: 8-bit bus transfer"]
10    Byte = 0,
11    #[doc = "1: 16-bit bus transfer"]
12    Hword = 1,
13    #[doc = "2: 32-bit bus transfer"]
14    Word = 2,
15}
16impl From<Crcbeatsizeselect> for u8 {
17    #[inline(always)]
18    fn from(variant: Crcbeatsizeselect) -> Self {
19        variant as _
20    }
21}
22impl crate::FieldSpec for Crcbeatsizeselect {
23    type Ux = u8;
24}
25impl crate::IsEnum for Crcbeatsizeselect {}
26#[doc = "Field `CRCBEATSIZE` reader - CRC Beat Size"]
27pub type CrcbeatsizeR = crate::FieldReader<Crcbeatsizeselect>;
28impl CrcbeatsizeR {
29    #[doc = "Get enumerated values variant"]
30    #[inline(always)]
31    pub const fn variant(&self) -> Option<Crcbeatsizeselect> {
32        match self.bits {
33            0 => Some(Crcbeatsizeselect::Byte),
34            1 => Some(Crcbeatsizeselect::Hword),
35            2 => Some(Crcbeatsizeselect::Word),
36            _ => None,
37        }
38    }
39    #[doc = "8-bit bus transfer"]
40    #[inline(always)]
41    pub fn is_byte(&self) -> bool {
42        *self == Crcbeatsizeselect::Byte
43    }
44    #[doc = "16-bit bus transfer"]
45    #[inline(always)]
46    pub fn is_hword(&self) -> bool {
47        *self == Crcbeatsizeselect::Hword
48    }
49    #[doc = "32-bit bus transfer"]
50    #[inline(always)]
51    pub fn is_word(&self) -> bool {
52        *self == Crcbeatsizeselect::Word
53    }
54}
55#[doc = "Field `CRCBEATSIZE` writer - CRC Beat Size"]
56pub type CrcbeatsizeW<'a, REG> = crate::FieldWriter<'a, REG, 2, Crcbeatsizeselect>;
57impl<'a, REG> CrcbeatsizeW<'a, REG>
58where
59    REG: crate::Writable + crate::RegisterSpec,
60    REG::Ux: From<u8>,
61{
62    #[doc = "8-bit bus transfer"]
63    #[inline(always)]
64    pub fn byte(self) -> &'a mut crate::W<REG> {
65        self.variant(Crcbeatsizeselect::Byte)
66    }
67    #[doc = "16-bit bus transfer"]
68    #[inline(always)]
69    pub fn hword(self) -> &'a mut crate::W<REG> {
70        self.variant(Crcbeatsizeselect::Hword)
71    }
72    #[doc = "32-bit bus transfer"]
73    #[inline(always)]
74    pub fn word(self) -> &'a mut crate::W<REG> {
75        self.variant(Crcbeatsizeselect::Word)
76    }
77}
78#[doc = "CRC Polynomial Type\n\nValue on reset: 0"]
79#[derive(Clone, Copy, Debug, PartialEq, Eq)]
80#[repr(u8)]
81pub enum Crcpolyselect {
82    #[doc = "0: CRC-16 (CRC-CCITT)"]
83    Crc16 = 0,
84    #[doc = "1: CRC32 (IEEE 802.3)"]
85    Crc32 = 1,
86}
87impl From<Crcpolyselect> for u8 {
88    #[inline(always)]
89    fn from(variant: Crcpolyselect) -> Self {
90        variant as _
91    }
92}
93impl crate::FieldSpec for Crcpolyselect {
94    type Ux = u8;
95}
96impl crate::IsEnum for Crcpolyselect {}
97#[doc = "Field `CRCPOLY` reader - CRC Polynomial Type"]
98pub type CrcpolyR = crate::FieldReader<Crcpolyselect>;
99impl CrcpolyR {
100    #[doc = "Get enumerated values variant"]
101    #[inline(always)]
102    pub const fn variant(&self) -> Option<Crcpolyselect> {
103        match self.bits {
104            0 => Some(Crcpolyselect::Crc16),
105            1 => Some(Crcpolyselect::Crc32),
106            _ => None,
107        }
108    }
109    #[doc = "CRC-16 (CRC-CCITT)"]
110    #[inline(always)]
111    pub fn is_crc16(&self) -> bool {
112        *self == Crcpolyselect::Crc16
113    }
114    #[doc = "CRC32 (IEEE 802.3)"]
115    #[inline(always)]
116    pub fn is_crc32(&self) -> bool {
117        *self == Crcpolyselect::Crc32
118    }
119}
120#[doc = "Field `CRCPOLY` writer - CRC Polynomial Type"]
121pub type CrcpolyW<'a, REG> = crate::FieldWriter<'a, REG, 2, Crcpolyselect>;
122impl<'a, REG> CrcpolyW<'a, REG>
123where
124    REG: crate::Writable + crate::RegisterSpec,
125    REG::Ux: From<u8>,
126{
127    #[doc = "CRC-16 (CRC-CCITT)"]
128    #[inline(always)]
129    pub fn crc16(self) -> &'a mut crate::W<REG> {
130        self.variant(Crcpolyselect::Crc16)
131    }
132    #[doc = "CRC32 (IEEE 802.3)"]
133    #[inline(always)]
134    pub fn crc32(self) -> &'a mut crate::W<REG> {
135        self.variant(Crcpolyselect::Crc32)
136    }
137}
138#[doc = "CRC Input Source\n\nValue on reset: 0"]
139#[derive(Clone, Copy, Debug, PartialEq, Eq)]
140#[repr(u8)]
141pub enum Crcsrcselect {
142    #[doc = "0: CRC Disabled"]
143    Disable = 0,
144    #[doc = "1: I/O interface"]
145    Io = 1,
146    #[doc = "32: DMA Channel 0"]
147    Chn0 = 32,
148    #[doc = "33: DMA Channel 1"]
149    Chn1 = 33,
150    #[doc = "34: DMA Channel 2"]
151    Chn2 = 34,
152    #[doc = "35: DMA Channel 3"]
153    Chn3 = 35,
154    #[doc = "36: DMA Channel 4"]
155    Chn4 = 36,
156    #[doc = "37: DMA Channel 5"]
157    Chn5 = 37,
158    #[doc = "38: DMA Channel 6"]
159    Chn6 = 38,
160    #[doc = "39: DMA Channel 7"]
161    Chn7 = 39,
162    #[doc = "40: DMA Channel 8"]
163    Chn8 = 40,
164    #[doc = "41: DMA Channel 9"]
165    Chn9 = 41,
166    #[doc = "42: DMA Channel 10"]
167    Chn10 = 42,
168    #[doc = "43: DMA Channel 11"]
169    Chn11 = 43,
170    #[doc = "44: DMA Channel 12"]
171    Chn12 = 44,
172    #[doc = "45: DMA Channel 13"]
173    Chn13 = 45,
174    #[doc = "46: DMA Channel 14"]
175    Chn14 = 46,
176    #[doc = "47: DMA Channel 15"]
177    Chn15 = 47,
178    #[doc = "48: DMA Channel 16"]
179    Chn16 = 48,
180    #[doc = "49: DMA Channel 17"]
181    Chn17 = 49,
182    #[doc = "50: DMA Channel 18"]
183    Chn18 = 50,
184    #[doc = "51: DMA Channel 19"]
185    Chn19 = 51,
186    #[doc = "52: DMA Channel 20"]
187    Chn20 = 52,
188    #[doc = "53: DMA Channel 21"]
189    Chn21 = 53,
190    #[doc = "54: DMA Channel 22"]
191    Chn22 = 54,
192    #[doc = "55: DMA Channel 23"]
193    Chn23 = 55,
194    #[doc = "56: DMA Channel 24"]
195    Chn24 = 56,
196    #[doc = "57: DMA Channel 25"]
197    Chn25 = 57,
198    #[doc = "58: DMA Channel 26"]
199    Chn26 = 58,
200    #[doc = "59: DMA Channel 27"]
201    Chn27 = 59,
202    #[doc = "60: DMA Channel 28"]
203    Chn28 = 60,
204    #[doc = "61: DMA Channel 29"]
205    Chn29 = 61,
206    #[doc = "62: DMA Channel 30"]
207    Chn30 = 62,
208    #[doc = "63: DMA Channel 31"]
209    Chn31 = 63,
210}
211impl From<Crcsrcselect> for u8 {
212    #[inline(always)]
213    fn from(variant: Crcsrcselect) -> Self {
214        variant as _
215    }
216}
217impl crate::FieldSpec for Crcsrcselect {
218    type Ux = u8;
219}
220impl crate::IsEnum for Crcsrcselect {}
221#[doc = "Field `CRCSRC` reader - CRC Input Source"]
222pub type CrcsrcR = crate::FieldReader<Crcsrcselect>;
223impl CrcsrcR {
224    #[doc = "Get enumerated values variant"]
225    #[inline(always)]
226    pub const fn variant(&self) -> Option<Crcsrcselect> {
227        match self.bits {
228            0 => Some(Crcsrcselect::Disable),
229            1 => Some(Crcsrcselect::Io),
230            32 => Some(Crcsrcselect::Chn0),
231            33 => Some(Crcsrcselect::Chn1),
232            34 => Some(Crcsrcselect::Chn2),
233            35 => Some(Crcsrcselect::Chn3),
234            36 => Some(Crcsrcselect::Chn4),
235            37 => Some(Crcsrcselect::Chn5),
236            38 => Some(Crcsrcselect::Chn6),
237            39 => Some(Crcsrcselect::Chn7),
238            40 => Some(Crcsrcselect::Chn8),
239            41 => Some(Crcsrcselect::Chn9),
240            42 => Some(Crcsrcselect::Chn10),
241            43 => Some(Crcsrcselect::Chn11),
242            44 => Some(Crcsrcselect::Chn12),
243            45 => Some(Crcsrcselect::Chn13),
244            46 => Some(Crcsrcselect::Chn14),
245            47 => Some(Crcsrcselect::Chn15),
246            48 => Some(Crcsrcselect::Chn16),
247            49 => Some(Crcsrcselect::Chn17),
248            50 => Some(Crcsrcselect::Chn18),
249            51 => Some(Crcsrcselect::Chn19),
250            52 => Some(Crcsrcselect::Chn20),
251            53 => Some(Crcsrcselect::Chn21),
252            54 => Some(Crcsrcselect::Chn22),
253            55 => Some(Crcsrcselect::Chn23),
254            56 => Some(Crcsrcselect::Chn24),
255            57 => Some(Crcsrcselect::Chn25),
256            58 => Some(Crcsrcselect::Chn26),
257            59 => Some(Crcsrcselect::Chn27),
258            60 => Some(Crcsrcselect::Chn28),
259            61 => Some(Crcsrcselect::Chn29),
260            62 => Some(Crcsrcselect::Chn30),
261            63 => Some(Crcsrcselect::Chn31),
262            _ => None,
263        }
264    }
265    #[doc = "CRC Disabled"]
266    #[inline(always)]
267    pub fn is_disable(&self) -> bool {
268        *self == Crcsrcselect::Disable
269    }
270    #[doc = "I/O interface"]
271    #[inline(always)]
272    pub fn is_io(&self) -> bool {
273        *self == Crcsrcselect::Io
274    }
275    #[doc = "DMA Channel 0"]
276    #[inline(always)]
277    pub fn is_chn0(&self) -> bool {
278        *self == Crcsrcselect::Chn0
279    }
280    #[doc = "DMA Channel 1"]
281    #[inline(always)]
282    pub fn is_chn1(&self) -> bool {
283        *self == Crcsrcselect::Chn1
284    }
285    #[doc = "DMA Channel 2"]
286    #[inline(always)]
287    pub fn is_chn2(&self) -> bool {
288        *self == Crcsrcselect::Chn2
289    }
290    #[doc = "DMA Channel 3"]
291    #[inline(always)]
292    pub fn is_chn3(&self) -> bool {
293        *self == Crcsrcselect::Chn3
294    }
295    #[doc = "DMA Channel 4"]
296    #[inline(always)]
297    pub fn is_chn4(&self) -> bool {
298        *self == Crcsrcselect::Chn4
299    }
300    #[doc = "DMA Channel 5"]
301    #[inline(always)]
302    pub fn is_chn5(&self) -> bool {
303        *self == Crcsrcselect::Chn5
304    }
305    #[doc = "DMA Channel 6"]
306    #[inline(always)]
307    pub fn is_chn6(&self) -> bool {
308        *self == Crcsrcselect::Chn6
309    }
310    #[doc = "DMA Channel 7"]
311    #[inline(always)]
312    pub fn is_chn7(&self) -> bool {
313        *self == Crcsrcselect::Chn7
314    }
315    #[doc = "DMA Channel 8"]
316    #[inline(always)]
317    pub fn is_chn8(&self) -> bool {
318        *self == Crcsrcselect::Chn8
319    }
320    #[doc = "DMA Channel 9"]
321    #[inline(always)]
322    pub fn is_chn9(&self) -> bool {
323        *self == Crcsrcselect::Chn9
324    }
325    #[doc = "DMA Channel 10"]
326    #[inline(always)]
327    pub fn is_chn10(&self) -> bool {
328        *self == Crcsrcselect::Chn10
329    }
330    #[doc = "DMA Channel 11"]
331    #[inline(always)]
332    pub fn is_chn11(&self) -> bool {
333        *self == Crcsrcselect::Chn11
334    }
335    #[doc = "DMA Channel 12"]
336    #[inline(always)]
337    pub fn is_chn12(&self) -> bool {
338        *self == Crcsrcselect::Chn12
339    }
340    #[doc = "DMA Channel 13"]
341    #[inline(always)]
342    pub fn is_chn13(&self) -> bool {
343        *self == Crcsrcselect::Chn13
344    }
345    #[doc = "DMA Channel 14"]
346    #[inline(always)]
347    pub fn is_chn14(&self) -> bool {
348        *self == Crcsrcselect::Chn14
349    }
350    #[doc = "DMA Channel 15"]
351    #[inline(always)]
352    pub fn is_chn15(&self) -> bool {
353        *self == Crcsrcselect::Chn15
354    }
355    #[doc = "DMA Channel 16"]
356    #[inline(always)]
357    pub fn is_chn16(&self) -> bool {
358        *self == Crcsrcselect::Chn16
359    }
360    #[doc = "DMA Channel 17"]
361    #[inline(always)]
362    pub fn is_chn17(&self) -> bool {
363        *self == Crcsrcselect::Chn17
364    }
365    #[doc = "DMA Channel 18"]
366    #[inline(always)]
367    pub fn is_chn18(&self) -> bool {
368        *self == Crcsrcselect::Chn18
369    }
370    #[doc = "DMA Channel 19"]
371    #[inline(always)]
372    pub fn is_chn19(&self) -> bool {
373        *self == Crcsrcselect::Chn19
374    }
375    #[doc = "DMA Channel 20"]
376    #[inline(always)]
377    pub fn is_chn20(&self) -> bool {
378        *self == Crcsrcselect::Chn20
379    }
380    #[doc = "DMA Channel 21"]
381    #[inline(always)]
382    pub fn is_chn21(&self) -> bool {
383        *self == Crcsrcselect::Chn21
384    }
385    #[doc = "DMA Channel 22"]
386    #[inline(always)]
387    pub fn is_chn22(&self) -> bool {
388        *self == Crcsrcselect::Chn22
389    }
390    #[doc = "DMA Channel 23"]
391    #[inline(always)]
392    pub fn is_chn23(&self) -> bool {
393        *self == Crcsrcselect::Chn23
394    }
395    #[doc = "DMA Channel 24"]
396    #[inline(always)]
397    pub fn is_chn24(&self) -> bool {
398        *self == Crcsrcselect::Chn24
399    }
400    #[doc = "DMA Channel 25"]
401    #[inline(always)]
402    pub fn is_chn25(&self) -> bool {
403        *self == Crcsrcselect::Chn25
404    }
405    #[doc = "DMA Channel 26"]
406    #[inline(always)]
407    pub fn is_chn26(&self) -> bool {
408        *self == Crcsrcselect::Chn26
409    }
410    #[doc = "DMA Channel 27"]
411    #[inline(always)]
412    pub fn is_chn27(&self) -> bool {
413        *self == Crcsrcselect::Chn27
414    }
415    #[doc = "DMA Channel 28"]
416    #[inline(always)]
417    pub fn is_chn28(&self) -> bool {
418        *self == Crcsrcselect::Chn28
419    }
420    #[doc = "DMA Channel 29"]
421    #[inline(always)]
422    pub fn is_chn29(&self) -> bool {
423        *self == Crcsrcselect::Chn29
424    }
425    #[doc = "DMA Channel 30"]
426    #[inline(always)]
427    pub fn is_chn30(&self) -> bool {
428        *self == Crcsrcselect::Chn30
429    }
430    #[doc = "DMA Channel 31"]
431    #[inline(always)]
432    pub fn is_chn31(&self) -> bool {
433        *self == Crcsrcselect::Chn31
434    }
435}
436#[doc = "Field `CRCSRC` writer - CRC Input Source"]
437pub type CrcsrcW<'a, REG> = crate::FieldWriter<'a, REG, 6, Crcsrcselect>;
438impl<'a, REG> CrcsrcW<'a, REG>
439where
440    REG: crate::Writable + crate::RegisterSpec,
441    REG::Ux: From<u8>,
442{
443    #[doc = "CRC Disabled"]
444    #[inline(always)]
445    pub fn disable(self) -> &'a mut crate::W<REG> {
446        self.variant(Crcsrcselect::Disable)
447    }
448    #[doc = "I/O interface"]
449    #[inline(always)]
450    pub fn io(self) -> &'a mut crate::W<REG> {
451        self.variant(Crcsrcselect::Io)
452    }
453    #[doc = "DMA Channel 0"]
454    #[inline(always)]
455    pub fn chn0(self) -> &'a mut crate::W<REG> {
456        self.variant(Crcsrcselect::Chn0)
457    }
458    #[doc = "DMA Channel 1"]
459    #[inline(always)]
460    pub fn chn1(self) -> &'a mut crate::W<REG> {
461        self.variant(Crcsrcselect::Chn1)
462    }
463    #[doc = "DMA Channel 2"]
464    #[inline(always)]
465    pub fn chn2(self) -> &'a mut crate::W<REG> {
466        self.variant(Crcsrcselect::Chn2)
467    }
468    #[doc = "DMA Channel 3"]
469    #[inline(always)]
470    pub fn chn3(self) -> &'a mut crate::W<REG> {
471        self.variant(Crcsrcselect::Chn3)
472    }
473    #[doc = "DMA Channel 4"]
474    #[inline(always)]
475    pub fn chn4(self) -> &'a mut crate::W<REG> {
476        self.variant(Crcsrcselect::Chn4)
477    }
478    #[doc = "DMA Channel 5"]
479    #[inline(always)]
480    pub fn chn5(self) -> &'a mut crate::W<REG> {
481        self.variant(Crcsrcselect::Chn5)
482    }
483    #[doc = "DMA Channel 6"]
484    #[inline(always)]
485    pub fn chn6(self) -> &'a mut crate::W<REG> {
486        self.variant(Crcsrcselect::Chn6)
487    }
488    #[doc = "DMA Channel 7"]
489    #[inline(always)]
490    pub fn chn7(self) -> &'a mut crate::W<REG> {
491        self.variant(Crcsrcselect::Chn7)
492    }
493    #[doc = "DMA Channel 8"]
494    #[inline(always)]
495    pub fn chn8(self) -> &'a mut crate::W<REG> {
496        self.variant(Crcsrcselect::Chn8)
497    }
498    #[doc = "DMA Channel 9"]
499    #[inline(always)]
500    pub fn chn9(self) -> &'a mut crate::W<REG> {
501        self.variant(Crcsrcselect::Chn9)
502    }
503    #[doc = "DMA Channel 10"]
504    #[inline(always)]
505    pub fn chn10(self) -> &'a mut crate::W<REG> {
506        self.variant(Crcsrcselect::Chn10)
507    }
508    #[doc = "DMA Channel 11"]
509    #[inline(always)]
510    pub fn chn11(self) -> &'a mut crate::W<REG> {
511        self.variant(Crcsrcselect::Chn11)
512    }
513    #[doc = "DMA Channel 12"]
514    #[inline(always)]
515    pub fn chn12(self) -> &'a mut crate::W<REG> {
516        self.variant(Crcsrcselect::Chn12)
517    }
518    #[doc = "DMA Channel 13"]
519    #[inline(always)]
520    pub fn chn13(self) -> &'a mut crate::W<REG> {
521        self.variant(Crcsrcselect::Chn13)
522    }
523    #[doc = "DMA Channel 14"]
524    #[inline(always)]
525    pub fn chn14(self) -> &'a mut crate::W<REG> {
526        self.variant(Crcsrcselect::Chn14)
527    }
528    #[doc = "DMA Channel 15"]
529    #[inline(always)]
530    pub fn chn15(self) -> &'a mut crate::W<REG> {
531        self.variant(Crcsrcselect::Chn15)
532    }
533    #[doc = "DMA Channel 16"]
534    #[inline(always)]
535    pub fn chn16(self) -> &'a mut crate::W<REG> {
536        self.variant(Crcsrcselect::Chn16)
537    }
538    #[doc = "DMA Channel 17"]
539    #[inline(always)]
540    pub fn chn17(self) -> &'a mut crate::W<REG> {
541        self.variant(Crcsrcselect::Chn17)
542    }
543    #[doc = "DMA Channel 18"]
544    #[inline(always)]
545    pub fn chn18(self) -> &'a mut crate::W<REG> {
546        self.variant(Crcsrcselect::Chn18)
547    }
548    #[doc = "DMA Channel 19"]
549    #[inline(always)]
550    pub fn chn19(self) -> &'a mut crate::W<REG> {
551        self.variant(Crcsrcselect::Chn19)
552    }
553    #[doc = "DMA Channel 20"]
554    #[inline(always)]
555    pub fn chn20(self) -> &'a mut crate::W<REG> {
556        self.variant(Crcsrcselect::Chn20)
557    }
558    #[doc = "DMA Channel 21"]
559    #[inline(always)]
560    pub fn chn21(self) -> &'a mut crate::W<REG> {
561        self.variant(Crcsrcselect::Chn21)
562    }
563    #[doc = "DMA Channel 22"]
564    #[inline(always)]
565    pub fn chn22(self) -> &'a mut crate::W<REG> {
566        self.variant(Crcsrcselect::Chn22)
567    }
568    #[doc = "DMA Channel 23"]
569    #[inline(always)]
570    pub fn chn23(self) -> &'a mut crate::W<REG> {
571        self.variant(Crcsrcselect::Chn23)
572    }
573    #[doc = "DMA Channel 24"]
574    #[inline(always)]
575    pub fn chn24(self) -> &'a mut crate::W<REG> {
576        self.variant(Crcsrcselect::Chn24)
577    }
578    #[doc = "DMA Channel 25"]
579    #[inline(always)]
580    pub fn chn25(self) -> &'a mut crate::W<REG> {
581        self.variant(Crcsrcselect::Chn25)
582    }
583    #[doc = "DMA Channel 26"]
584    #[inline(always)]
585    pub fn chn26(self) -> &'a mut crate::W<REG> {
586        self.variant(Crcsrcselect::Chn26)
587    }
588    #[doc = "DMA Channel 27"]
589    #[inline(always)]
590    pub fn chn27(self) -> &'a mut crate::W<REG> {
591        self.variant(Crcsrcselect::Chn27)
592    }
593    #[doc = "DMA Channel 28"]
594    #[inline(always)]
595    pub fn chn28(self) -> &'a mut crate::W<REG> {
596        self.variant(Crcsrcselect::Chn28)
597    }
598    #[doc = "DMA Channel 29"]
599    #[inline(always)]
600    pub fn chn29(self) -> &'a mut crate::W<REG> {
601        self.variant(Crcsrcselect::Chn29)
602    }
603    #[doc = "DMA Channel 30"]
604    #[inline(always)]
605    pub fn chn30(self) -> &'a mut crate::W<REG> {
606        self.variant(Crcsrcselect::Chn30)
607    }
608    #[doc = "DMA Channel 31"]
609    #[inline(always)]
610    pub fn chn31(self) -> &'a mut crate::W<REG> {
611        self.variant(Crcsrcselect::Chn31)
612    }
613}
614#[doc = "CRC Operating Mode\n\nValue on reset: 0"]
615#[derive(Clone, Copy, Debug, PartialEq, Eq)]
616#[repr(u8)]
617pub enum Crcmodeselect {
618    #[doc = "0: Default operating mode"]
619    Default = 0,
620    #[doc = "2: Memory CRC monitor operating mode"]
621    Crcmon = 2,
622    #[doc = "3: Memory CRC generation operating mode"]
623    Crcgen = 3,
624}
625impl From<Crcmodeselect> for u8 {
626    #[inline(always)]
627    fn from(variant: Crcmodeselect) -> Self {
628        variant as _
629    }
630}
631impl crate::FieldSpec for Crcmodeselect {
632    type Ux = u8;
633}
634impl crate::IsEnum for Crcmodeselect {}
635#[doc = "Field `CRCMODE` reader - CRC Operating Mode"]
636pub type CrcmodeR = crate::FieldReader<Crcmodeselect>;
637impl CrcmodeR {
638    #[doc = "Get enumerated values variant"]
639    #[inline(always)]
640    pub const fn variant(&self) -> Option<Crcmodeselect> {
641        match self.bits {
642            0 => Some(Crcmodeselect::Default),
643            2 => Some(Crcmodeselect::Crcmon),
644            3 => Some(Crcmodeselect::Crcgen),
645            _ => None,
646        }
647    }
648    #[doc = "Default operating mode"]
649    #[inline(always)]
650    pub fn is_default(&self) -> bool {
651        *self == Crcmodeselect::Default
652    }
653    #[doc = "Memory CRC monitor operating mode"]
654    #[inline(always)]
655    pub fn is_crcmon(&self) -> bool {
656        *self == Crcmodeselect::Crcmon
657    }
658    #[doc = "Memory CRC generation operating mode"]
659    #[inline(always)]
660    pub fn is_crcgen(&self) -> bool {
661        *self == Crcmodeselect::Crcgen
662    }
663}
664#[doc = "Field `CRCMODE` writer - CRC Operating Mode"]
665pub type CrcmodeW<'a, REG> = crate::FieldWriter<'a, REG, 2, Crcmodeselect>;
666impl<'a, REG> CrcmodeW<'a, REG>
667where
668    REG: crate::Writable + crate::RegisterSpec,
669    REG::Ux: From<u8>,
670{
671    #[doc = "Default operating mode"]
672    #[inline(always)]
673    pub fn default(self) -> &'a mut crate::W<REG> {
674        self.variant(Crcmodeselect::Default)
675    }
676    #[doc = "Memory CRC monitor operating mode"]
677    #[inline(always)]
678    pub fn crcmon(self) -> &'a mut crate::W<REG> {
679        self.variant(Crcmodeselect::Crcmon)
680    }
681    #[doc = "Memory CRC generation operating mode"]
682    #[inline(always)]
683    pub fn crcgen(self) -> &'a mut crate::W<REG> {
684        self.variant(Crcmodeselect::Crcgen)
685    }
686}
687impl R {
688    #[doc = "Bits 0:1 - CRC Beat Size"]
689    #[inline(always)]
690    pub fn crcbeatsize(&self) -> CrcbeatsizeR {
691        CrcbeatsizeR::new((self.bits & 3) as u8)
692    }
693    #[doc = "Bits 2:3 - CRC Polynomial Type"]
694    #[inline(always)]
695    pub fn crcpoly(&self) -> CrcpolyR {
696        CrcpolyR::new(((self.bits >> 2) & 3) as u8)
697    }
698    #[doc = "Bits 8:13 - CRC Input Source"]
699    #[inline(always)]
700    pub fn crcsrc(&self) -> CrcsrcR {
701        CrcsrcR::new(((self.bits >> 8) & 0x3f) as u8)
702    }
703    #[doc = "Bits 14:15 - CRC Operating Mode"]
704    #[inline(always)]
705    pub fn crcmode(&self) -> CrcmodeR {
706        CrcmodeR::new(((self.bits >> 14) & 3) as u8)
707    }
708}
709impl W {
710    #[doc = "Bits 0:1 - CRC Beat Size"]
711    #[inline(always)]
712    #[must_use]
713    pub fn crcbeatsize(&mut self) -> CrcbeatsizeW<CrcctrlSpec> {
714        CrcbeatsizeW::new(self, 0)
715    }
716    #[doc = "Bits 2:3 - CRC Polynomial Type"]
717    #[inline(always)]
718    #[must_use]
719    pub fn crcpoly(&mut self) -> CrcpolyW<CrcctrlSpec> {
720        CrcpolyW::new(self, 2)
721    }
722    #[doc = "Bits 8:13 - CRC Input Source"]
723    #[inline(always)]
724    #[must_use]
725    pub fn crcsrc(&mut self) -> CrcsrcW<CrcctrlSpec> {
726        CrcsrcW::new(self, 8)
727    }
728    #[doc = "Bits 14:15 - CRC Operating Mode"]
729    #[inline(always)]
730    #[must_use]
731    pub fn crcmode(&mut self) -> CrcmodeW<CrcctrlSpec> {
732        CrcmodeW::new(self, 14)
733    }
734}
735#[doc = "CRC Control\n\nYou can [`read`](crate::Reg::read) this register and get [`crcctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crcctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
736pub struct CrcctrlSpec;
737impl crate::RegisterSpec for CrcctrlSpec {
738    type Ux = u16;
739}
740#[doc = "`read()` method returns [`crcctrl::R`](R) reader structure"]
741impl crate::Readable for CrcctrlSpec {}
742#[doc = "`write(|w| ..)` method takes [`crcctrl::W`](W) writer structure"]
743impl crate::Writable for CrcctrlSpec {
744    type Safety = crate::Unsafe;
745    const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
746    const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
747}
748#[doc = "`reset()` method sets CRCCTRL to value 0"]
749impl crate::Resettable for CrcctrlSpec {
750    const RESET_VALUE: u16 = 0;
751}
atsamd51g/dmac/crcctrl.rs

atsamd51g/dmac/
crcctrl.rs
