atsamd51p/usb/device/
intenclr.rs

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1#[doc = "Register `INTENCLR` reader"]
2pub type R = crate::R<IntenclrSpec>;
3#[doc = "Register `INTENCLR` writer"]
4pub type W = crate::W<IntenclrSpec>;
5#[doc = "Field `SUSPEND` reader - Suspend Interrupt Enable"]
6pub type SuspendR = crate::BitReader;
7#[doc = "Field `SUSPEND` writer - Suspend Interrupt Enable"]
8pub type SuspendW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `SOF` reader - Start Of Frame Interrupt Enable"]
10pub type SofR = crate::BitReader;
11#[doc = "Field `SOF` writer - Start Of Frame Interrupt Enable"]
12pub type SofW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `EORST` reader - End of Reset Interrupt Enable"]
14pub type EorstR = crate::BitReader;
15#[doc = "Field `EORST` writer - End of Reset Interrupt Enable"]
16pub type EorstW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `WAKEUP` reader - Wake Up Interrupt Enable"]
18pub type WakeupR = crate::BitReader;
19#[doc = "Field `WAKEUP` writer - Wake Up Interrupt Enable"]
20pub type WakeupW<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `EORSM` reader - End Of Resume Interrupt Enable"]
22pub type EorsmR = crate::BitReader;
23#[doc = "Field `EORSM` writer - End Of Resume Interrupt Enable"]
24pub type EorsmW<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `UPRSM` reader - Upstream Resume Interrupt Enable"]
26pub type UprsmR = crate::BitReader;
27#[doc = "Field `UPRSM` writer - Upstream Resume Interrupt Enable"]
28pub type UprsmW<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `RAMACER` reader - Ram Access Interrupt Enable"]
30pub type RamacerR = crate::BitReader;
31#[doc = "Field `RAMACER` writer - Ram Access Interrupt Enable"]
32pub type RamacerW<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `LPMNYET` reader - Link Power Management Not Yet Interrupt Enable"]
34pub type LpmnyetR = crate::BitReader;
35#[doc = "Field `LPMNYET` writer - Link Power Management Not Yet Interrupt Enable"]
36pub type LpmnyetW<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `LPMSUSP` reader - Link Power Management Suspend Interrupt Enable"]
38pub type LpmsuspR = crate::BitReader;
39#[doc = "Field `LPMSUSP` writer - Link Power Management Suspend Interrupt Enable"]
40pub type LpmsuspW<'a, REG> = crate::BitWriter<'a, REG>;
41impl R {
42    #[doc = "Bit 0 - Suspend Interrupt Enable"]
43    #[inline(always)]
44    pub fn suspend(&self) -> SuspendR {
45        SuspendR::new((self.bits & 1) != 0)
46    }
47    #[doc = "Bit 2 - Start Of Frame Interrupt Enable"]
48    #[inline(always)]
49    pub fn sof(&self) -> SofR {
50        SofR::new(((self.bits >> 2) & 1) != 0)
51    }
52    #[doc = "Bit 3 - End of Reset Interrupt Enable"]
53    #[inline(always)]
54    pub fn eorst(&self) -> EorstR {
55        EorstR::new(((self.bits >> 3) & 1) != 0)
56    }
57    #[doc = "Bit 4 - Wake Up Interrupt Enable"]
58    #[inline(always)]
59    pub fn wakeup(&self) -> WakeupR {
60        WakeupR::new(((self.bits >> 4) & 1) != 0)
61    }
62    #[doc = "Bit 5 - End Of Resume Interrupt Enable"]
63    #[inline(always)]
64    pub fn eorsm(&self) -> EorsmR {
65        EorsmR::new(((self.bits >> 5) & 1) != 0)
66    }
67    #[doc = "Bit 6 - Upstream Resume Interrupt Enable"]
68    #[inline(always)]
69    pub fn uprsm(&self) -> UprsmR {
70        UprsmR::new(((self.bits >> 6) & 1) != 0)
71    }
72    #[doc = "Bit 7 - Ram Access Interrupt Enable"]
73    #[inline(always)]
74    pub fn ramacer(&self) -> RamacerR {
75        RamacerR::new(((self.bits >> 7) & 1) != 0)
76    }
77    #[doc = "Bit 8 - Link Power Management Not Yet Interrupt Enable"]
78    #[inline(always)]
79    pub fn lpmnyet(&self) -> LpmnyetR {
80        LpmnyetR::new(((self.bits >> 8) & 1) != 0)
81    }
82    #[doc = "Bit 9 - Link Power Management Suspend Interrupt Enable"]
83    #[inline(always)]
84    pub fn lpmsusp(&self) -> LpmsuspR {
85        LpmsuspR::new(((self.bits >> 9) & 1) != 0)
86    }
87}
88impl W {
89    #[doc = "Bit 0 - Suspend Interrupt Enable"]
90    #[inline(always)]
91    #[must_use]
92    pub fn suspend(&mut self) -> SuspendW<IntenclrSpec> {
93        SuspendW::new(self, 0)
94    }
95    #[doc = "Bit 2 - Start Of Frame Interrupt Enable"]
96    #[inline(always)]
97    #[must_use]
98    pub fn sof(&mut self) -> SofW<IntenclrSpec> {
99        SofW::new(self, 2)
100    }
101    #[doc = "Bit 3 - End of Reset Interrupt Enable"]
102    #[inline(always)]
103    #[must_use]
104    pub fn eorst(&mut self) -> EorstW<IntenclrSpec> {
105        EorstW::new(self, 3)
106    }
107    #[doc = "Bit 4 - Wake Up Interrupt Enable"]
108    #[inline(always)]
109    #[must_use]
110    pub fn wakeup(&mut self) -> WakeupW<IntenclrSpec> {
111        WakeupW::new(self, 4)
112    }
113    #[doc = "Bit 5 - End Of Resume Interrupt Enable"]
114    #[inline(always)]
115    #[must_use]
116    pub fn eorsm(&mut self) -> EorsmW<IntenclrSpec> {
117        EorsmW::new(self, 5)
118    }
119    #[doc = "Bit 6 - Upstream Resume Interrupt Enable"]
120    #[inline(always)]
121    #[must_use]
122    pub fn uprsm(&mut self) -> UprsmW<IntenclrSpec> {
123        UprsmW::new(self, 6)
124    }
125    #[doc = "Bit 7 - Ram Access Interrupt Enable"]
126    #[inline(always)]
127    #[must_use]
128    pub fn ramacer(&mut self) -> RamacerW<IntenclrSpec> {
129        RamacerW::new(self, 7)
130    }
131    #[doc = "Bit 8 - Link Power Management Not Yet Interrupt Enable"]
132    #[inline(always)]
133    #[must_use]
134    pub fn lpmnyet(&mut self) -> LpmnyetW<IntenclrSpec> {
135        LpmnyetW::new(self, 8)
136    }
137    #[doc = "Bit 9 - Link Power Management Suspend Interrupt Enable"]
138    #[inline(always)]
139    #[must_use]
140    pub fn lpmsusp(&mut self) -> LpmsuspW<IntenclrSpec> {
141        LpmsuspW::new(self, 9)
142    }
143}
144#[doc = "DEVICE Device Interrupt Enable Clear\n\nYou can [`read`](crate::Reg::read) this register and get [`intenclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intenclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
145pub struct IntenclrSpec;
146impl crate::RegisterSpec for IntenclrSpec {
147    type Ux = u16;
148}
149#[doc = "`read()` method returns [`intenclr::R`](R) reader structure"]
150impl crate::Readable for IntenclrSpec {}
151#[doc = "`write(|w| ..)` method takes [`intenclr::W`](W) writer structure"]
152impl crate::Writable for IntenclrSpec {
153    type Safety = crate::Unsafe;
154    const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
155    const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
156}
157#[doc = "`reset()` method sets INTENCLR to value 0"]
158impl crate::Resettable for IntenclrSpec {
159    const RESET_VALUE: u16 = 0;
160}
atsamd51p/usb/device/intenclr.rs

atsamd51p/usb/device/
intenclr.rs
