atsamd51p/
sdhc0.rs

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1#[repr(C)]
2#[doc = "Register block"]
3pub struct RegisterBlock {
4    _reserved_0_ssar: [u8; 0x04],
5    bsr: Bsr,
6    bcr: Bcr,
7    arg1r: Arg1r,
8    tmr: Tmr,
9    cr: Cr,
10    rr: [Rr; 4],
11    bdpr: Bdpr,
12    psr: Psr,
13    _reserved_9_hc1: [u8; 0x01],
14    pcr: Pcr,
15    _reserved_11_bgcr: [u8; 0x01],
16    wcr: Wcr,
17    ccr: Ccr,
18    tcr: Tcr,
19    srr: Srr,
20    _reserved_16_nistr: [u8; 0x02],
21    _reserved_17_eistr: [u8; 0x02],
22    _reserved_18_nister: [u8; 0x02],
23    _reserved_19_eister: [u8; 0x02],
24    _reserved_20_nisier: [u8; 0x02],
25    _reserved_21_eisier: [u8; 0x02],
26    acesr: Acesr,
27    _reserved_23_hc2: [u8; 0x02],
28    ca0r: Ca0r,
29    ca1r: Ca1r,
30    mccar: Mccar,
31    _reserved27: [u8; 0x04],
32    feraces: Feraces,
33    fereis: Fereis,
34    aesr: Aesr,
35    _reserved30: [u8; 0x03],
36    asar: [Asar; 1],
37    _reserved31: [u8; 0x04],
38    pvr: [Pvr; 8],
39    _reserved32: [u8; 0x8c],
40    sisr: Sisr,
41    hcvr: Hcvr,
42    _reserved34: [u8; 0x0100],
43    apsr: Apsr,
44    mc1r: Mc1r,
45    mc2r: Mc2r,
46    _reserved37: [u8; 0x02],
47    acr: Acr,
48    cc2r: Cc2r,
49    _reserved39: [u8; 0x20],
50    cacr: Cacr,
51    dbgr: Dbgr,
52}
53impl RegisterBlock {
54    #[doc = "0x00 - SDMA System Address / Argument 2"]
55    #[inline(always)]
56    pub const fn ssar_cmd23_mode(&self) -> &SsarCmd23Mode {
57        unsafe { &*(self as *const Self).cast::<u8>().add(0).cast() }
58    }
59    #[doc = "0x00 - SDMA System Address / Argument 2"]
60    #[inline(always)]
61    pub const fn ssar(&self) -> &Ssar {
62        unsafe { &*(self as *const Self).cast::<u8>().add(0).cast() }
63    }
64    #[doc = "0x04 - Block Size"]
65    #[inline(always)]
66    pub const fn bsr(&self) -> &Bsr {
67        &self.bsr
68    }
69    #[doc = "0x06 - Block Count"]
70    #[inline(always)]
71    pub const fn bcr(&self) -> &Bcr {
72        &self.bcr
73    }
74    #[doc = "0x08 - Argument 1"]
75    #[inline(always)]
76    pub const fn arg1r(&self) -> &Arg1r {
77        &self.arg1r
78    }
79    #[doc = "0x0c - Transfer Mode"]
80    #[inline(always)]
81    pub const fn tmr(&self) -> &Tmr {
82        &self.tmr
83    }
84    #[doc = "0x0e - Command"]
85    #[inline(always)]
86    pub const fn cr(&self) -> &Cr {
87        &self.cr
88    }
89    #[doc = "0x10..0x20 - Response"]
90    #[inline(always)]
91    pub const fn rr(&self, n: usize) -> &Rr {
92        &self.rr[n]
93    }
94    #[doc = "Iterator for array of:"]
95    #[doc = "0x10..0x20 - Response"]
96    #[inline(always)]
97    pub fn rr_iter(&self) -> impl Iterator<Item = &Rr> {
98        self.rr.iter()
99    }
100    #[doc = "0x20 - Buffer Data Port"]
101    #[inline(always)]
102    pub const fn bdpr(&self) -> &Bdpr {
103        &self.bdpr
104    }
105    #[doc = "0x24 - Present State"]
106    #[inline(always)]
107    pub const fn psr(&self) -> &Psr {
108        &self.psr
109    }
110    #[doc = "0x28 - Host Control 1"]
111    #[inline(always)]
112    pub const fn hc1r_emmc_mode(&self) -> &Hc1rEmmcMode {
113        unsafe { &*(self as *const Self).cast::<u8>().add(40).cast() }
114    }
115    #[doc = "0x28 - Host Control 1"]
116    #[inline(always)]
117    pub const fn hc1r(&self) -> &Hc1r {
118        unsafe { &*(self as *const Self).cast::<u8>().add(40).cast() }
119    }
120    #[doc = "0x29 - Power Control"]
121    #[inline(always)]
122    pub const fn pcr(&self) -> &Pcr {
123        &self.pcr
124    }
125    #[doc = "0x2a - Block Gap Control"]
126    #[inline(always)]
127    pub const fn bgcr_emmc_mode(&self) -> &BgcrEmmcMode {
128        unsafe { &*(self as *const Self).cast::<u8>().add(42).cast() }
129    }
130    #[doc = "0x2a - Block Gap Control"]
131    #[inline(always)]
132    pub const fn bgcr(&self) -> &Bgcr {
133        unsafe { &*(self as *const Self).cast::<u8>().add(42).cast() }
134    }
135    #[doc = "0x2b - Wakeup Control"]
136    #[inline(always)]
137    pub const fn wcr(&self) -> &Wcr {
138        &self.wcr
139    }
140    #[doc = "0x2c - Clock Control"]
141    #[inline(always)]
142    pub const fn ccr(&self) -> &Ccr {
143        &self.ccr
144    }
145    #[doc = "0x2e - Timeout Control"]
146    #[inline(always)]
147    pub const fn tcr(&self) -> &Tcr {
148        &self.tcr
149    }
150    #[doc = "0x2f - Software Reset"]
151    #[inline(always)]
152    pub const fn srr(&self) -> &Srr {
153        &self.srr
154    }
155    #[doc = "0x30 - Normal Interrupt Status"]
156    #[inline(always)]
157    pub const fn nistr_emmc_mode(&self) -> &NistrEmmcMode {
158        unsafe { &*(self as *const Self).cast::<u8>().add(48).cast() }
159    }
160    #[doc = "0x30 - Normal Interrupt Status"]
161    #[inline(always)]
162    pub const fn nistr(&self) -> &Nistr {
163        unsafe { &*(self as *const Self).cast::<u8>().add(48).cast() }
164    }
165    #[doc = "0x32 - Error Interrupt Status"]
166    #[inline(always)]
167    pub const fn eistr_emmc_mode(&self) -> &EistrEmmcMode {
168        unsafe { &*(self as *const Self).cast::<u8>().add(50).cast() }
169    }
170    #[doc = "0x32 - Error Interrupt Status"]
171    #[inline(always)]
172    pub const fn eistr(&self) -> &Eistr {
173        unsafe { &*(self as *const Self).cast::<u8>().add(50).cast() }
174    }
175    #[doc = "0x34 - Normal Interrupt Status Enable"]
176    #[inline(always)]
177    pub const fn nister_emmc_mode(&self) -> &NisterEmmcMode {
178        unsafe { &*(self as *const Self).cast::<u8>().add(52).cast() }
179    }
180    #[doc = "0x34 - Normal Interrupt Status Enable"]
181    #[inline(always)]
182    pub const fn nister(&self) -> &Nister {
183        unsafe { &*(self as *const Self).cast::<u8>().add(52).cast() }
184    }
185    #[doc = "0x36 - Error Interrupt Status Enable"]
186    #[inline(always)]
187    pub const fn eister_emmc_mode(&self) -> &EisterEmmcMode {
188        unsafe { &*(self as *const Self).cast::<u8>().add(54).cast() }
189    }
190    #[doc = "0x36 - Error Interrupt Status Enable"]
191    #[inline(always)]
192    pub const fn eister(&self) -> &Eister {
193        unsafe { &*(self as *const Self).cast::<u8>().add(54).cast() }
194    }
195    #[doc = "0x38 - Normal Interrupt Signal Enable"]
196    #[inline(always)]
197    pub const fn nisier_emmc_mode(&self) -> &NisierEmmcMode {
198        unsafe { &*(self as *const Self).cast::<u8>().add(56).cast() }
199    }
200    #[doc = "0x38 - Normal Interrupt Signal Enable"]
201    #[inline(always)]
202    pub const fn nisier(&self) -> &Nisier {
203        unsafe { &*(self as *const Self).cast::<u8>().add(56).cast() }
204    }
205    #[doc = "0x3a - Error Interrupt Signal Enable"]
206    #[inline(always)]
207    pub const fn eisier_emmc_mode(&self) -> &EisierEmmcMode {
208        unsafe { &*(self as *const Self).cast::<u8>().add(58).cast() }
209    }
210    #[doc = "0x3a - Error Interrupt Signal Enable"]
211    #[inline(always)]
212    pub const fn eisier(&self) -> &Eisier {
213        unsafe { &*(self as *const Self).cast::<u8>().add(58).cast() }
214    }
215    #[doc = "0x3c - Auto CMD Error Status"]
216    #[inline(always)]
217    pub const fn acesr(&self) -> &Acesr {
218        &self.acesr
219    }
220    #[doc = "0x3e - Host Control 2"]
221    #[inline(always)]
222    pub const fn hc2r_emmc_mode(&self) -> &Hc2rEmmcMode {
223        unsafe { &*(self as *const Self).cast::<u8>().add(62).cast() }
224    }
225    #[doc = "0x3e - Host Control 2"]
226    #[inline(always)]
227    pub const fn hc2r(&self) -> &Hc2r {
228        unsafe { &*(self as *const Self).cast::<u8>().add(62).cast() }
229    }
230    #[doc = "0x40 - Capabilities 0"]
231    #[inline(always)]
232    pub const fn ca0r(&self) -> &Ca0r {
233        &self.ca0r
234    }
235    #[doc = "0x44 - Capabilities 1"]
236    #[inline(always)]
237    pub const fn ca1r(&self) -> &Ca1r {
238        &self.ca1r
239    }
240    #[doc = "0x48 - Maximum Current Capabilities"]
241    #[inline(always)]
242    pub const fn mccar(&self) -> &Mccar {
243        &self.mccar
244    }
245    #[doc = "0x50 - Force Event for Auto CMD Error Status"]
246    #[inline(always)]
247    pub const fn feraces(&self) -> &Feraces {
248        &self.feraces
249    }
250    #[doc = "0x52 - Force Event for Error Interrupt Status"]
251    #[inline(always)]
252    pub const fn fereis(&self) -> &Fereis {
253        &self.fereis
254    }
255    #[doc = "0x54 - ADMA Error Status"]
256    #[inline(always)]
257    pub const fn aesr(&self) -> &Aesr {
258        &self.aesr
259    }
260    #[doc = "0x58 - ADMA System Address"]
261    #[inline(always)]
262    pub const fn asar(&self, n: usize) -> &Asar {
263        &self.asar[n]
264    }
265    #[doc = "Iterator for array of:"]
266    #[doc = "0x58 - ADMA System Address"]
267    #[inline(always)]
268    pub fn asar_iter(&self) -> impl Iterator<Item = &Asar> {
269        self.asar.iter()
270    }
271    #[doc = "0x60..0x70 - Preset Value n"]
272    #[inline(always)]
273    pub const fn pvr(&self, n: usize) -> &Pvr {
274        &self.pvr[n]
275    }
276    #[doc = "Iterator for array of:"]
277    #[doc = "0x60..0x70 - Preset Value n"]
278    #[inline(always)]
279    pub fn pvr_iter(&self) -> impl Iterator<Item = &Pvr> {
280        self.pvr.iter()
281    }
282    #[doc = "0xfc - Slot Interrupt Status"]
283    #[inline(always)]
284    pub const fn sisr(&self) -> &Sisr {
285        &self.sisr
286    }
287    #[doc = "0xfe - Host Controller Version"]
288    #[inline(always)]
289    pub const fn hcvr(&self) -> &Hcvr {
290        &self.hcvr
291    }
292    #[doc = "0x200 - Additional Present State Register"]
293    #[inline(always)]
294    pub const fn apsr(&self) -> &Apsr {
295        &self.apsr
296    }
297    #[doc = "0x204 - MMC Control 1"]
298    #[inline(always)]
299    pub const fn mc1r(&self) -> &Mc1r {
300        &self.mc1r
301    }
302    #[doc = "0x205 - MMC Control 2"]
303    #[inline(always)]
304    pub const fn mc2r(&self) -> &Mc2r {
305        &self.mc2r
306    }
307    #[doc = "0x208 - AHB Control"]
308    #[inline(always)]
309    pub const fn acr(&self) -> &Acr {
310        &self.acr
311    }
312    #[doc = "0x20c - Clock Control 2"]
313    #[inline(always)]
314    pub const fn cc2r(&self) -> &Cc2r {
315        &self.cc2r
316    }
317    #[doc = "0x230 - Capabilities Control"]
318    #[inline(always)]
319    pub const fn cacr(&self) -> &Cacr {
320        &self.cacr
321    }
322    #[doc = "0x234 - Debug"]
323    #[inline(always)]
324    pub const fn dbgr(&self) -> &Dbgr {
325        &self.dbgr
326    }
327}
328#[doc = "SSAR (rw) register accessor: SDMA System Address / Argument 2\n\nYou can [`read`](crate::Reg::read) this register and get [`ssar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ssar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssar`]
329module"]
330#[doc(alias = "SSAR")]
331pub type Ssar = crate::Reg<ssar::SsarSpec>;
332#[doc = "SDMA System Address / Argument 2"]
333pub mod ssar;
334#[doc = "SSAR_CMD23_MODE (rw) register accessor: SDMA System Address / Argument 2\n\nYou can [`read`](crate::Reg::read) this register and get [`ssar_cmd23_mode::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ssar_cmd23_mode::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssar_cmd23_mode`]
335module"]
336#[doc(alias = "SSAR_CMD23_MODE")]
337pub type SsarCmd23Mode = crate::Reg<ssar_cmd23_mode::SsarCmd23ModeSpec>;
338#[doc = "SDMA System Address / Argument 2"]
339pub mod ssar_cmd23_mode;
340#[doc = "BSR (rw) register accessor: Block Size\n\nYou can [`read`](crate::Reg::read) this register and get [`bsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bsr`]
341module"]
342#[doc(alias = "BSR")]
343pub type Bsr = crate::Reg<bsr::BsrSpec>;
344#[doc = "Block Size"]
345pub mod bsr;
346#[doc = "BCR (rw) register accessor: Block Count\n\nYou can [`read`](crate::Reg::read) this register and get [`bcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bcr`]
347module"]
348#[doc(alias = "BCR")]
349pub type Bcr = crate::Reg<bcr::BcrSpec>;
350#[doc = "Block Count"]
351pub mod bcr;
352#[doc = "ARG1R (rw) register accessor: Argument 1\n\nYou can [`read`](crate::Reg::read) this register and get [`arg1r::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`arg1r::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@arg1r`]
353module"]
354#[doc(alias = "ARG1R")]
355pub type Arg1r = crate::Reg<arg1r::Arg1rSpec>;
356#[doc = "Argument 1"]
357pub mod arg1r;
358#[doc = "TMR (rw) register accessor: Transfer Mode\n\nYou can [`read`](crate::Reg::read) this register and get [`tmr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tmr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tmr`]
359module"]
360#[doc(alias = "TMR")]
361pub type Tmr = crate::Reg<tmr::TmrSpec>;
362#[doc = "Transfer Mode"]
363pub mod tmr;
364#[doc = "CR (rw) register accessor: Command\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr`]
365module"]
366#[doc(alias = "CR")]
367pub type Cr = crate::Reg<cr::CrSpec>;
368#[doc = "Command"]
369pub mod cr;
370#[doc = "RR (r) register accessor: Response\n\nYou can [`read`](crate::Reg::read) this register and get [`rr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rr`]
371module"]
372#[doc(alias = "RR")]
373pub type Rr = crate::Reg<rr::RrSpec>;
374#[doc = "Response"]
375pub mod rr;
376#[doc = "BDPR (rw) register accessor: Buffer Data Port\n\nYou can [`read`](crate::Reg::read) this register and get [`bdpr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bdpr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bdpr`]
377module"]
378#[doc(alias = "BDPR")]
379pub type Bdpr = crate::Reg<bdpr::BdprSpec>;
380#[doc = "Buffer Data Port"]
381pub mod bdpr;
382#[doc = "PSR (r) register accessor: Present State\n\nYou can [`read`](crate::Reg::read) this register and get [`psr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@psr`]
383module"]
384#[doc(alias = "PSR")]
385pub type Psr = crate::Reg<psr::PsrSpec>;
386#[doc = "Present State"]
387pub mod psr;
388#[doc = "HC1R (rw) register accessor: Host Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`hc1r::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hc1r::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hc1r`]
389module"]
390#[doc(alias = "HC1R")]
391pub type Hc1r = crate::Reg<hc1r::Hc1rSpec>;
392#[doc = "Host Control 1"]
393pub mod hc1r;
394#[doc = "HC1R_EMMC_MODE (rw) register accessor: Host Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`hc1r_emmc_mode::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hc1r_emmc_mode::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hc1r_emmc_mode`]
395module"]
396#[doc(alias = "HC1R_EMMC_MODE")]
397pub type Hc1rEmmcMode = crate::Reg<hc1r_emmc_mode::Hc1rEmmcModeSpec>;
398#[doc = "Host Control 1"]
399pub mod hc1r_emmc_mode;
400#[doc = "PCR (rw) register accessor: Power Control\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr`]
401module"]
402#[doc(alias = "PCR")]
403pub type Pcr = crate::Reg<pcr::PcrSpec>;
404#[doc = "Power Control"]
405pub mod pcr;
406#[doc = "BGCR (rw) register accessor: Block Gap Control\n\nYou can [`read`](crate::Reg::read) this register and get [`bgcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bgcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bgcr`]
407module"]
408#[doc(alias = "BGCR")]
409pub type Bgcr = crate::Reg<bgcr::BgcrSpec>;
410#[doc = "Block Gap Control"]
411pub mod bgcr;
412#[doc = "BGCR_EMMC_MODE (rw) register accessor: Block Gap Control\n\nYou can [`read`](crate::Reg::read) this register and get [`bgcr_emmc_mode::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bgcr_emmc_mode::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bgcr_emmc_mode`]
413module"]
414#[doc(alias = "BGCR_EMMC_MODE")]
415pub type BgcrEmmcMode = crate::Reg<bgcr_emmc_mode::BgcrEmmcModeSpec>;
416#[doc = "Block Gap Control"]
417pub mod bgcr_emmc_mode;
418#[doc = "WCR (rw) register accessor: Wakeup Control\n\nYou can [`read`](crate::Reg::read) this register and get [`wcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wcr`]
419module"]
420#[doc(alias = "WCR")]
421pub type Wcr = crate::Reg<wcr::WcrSpec>;
422#[doc = "Wakeup Control"]
423pub mod wcr;
424#[doc = "CCR (rw) register accessor: Clock Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ccr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccr`]
425module"]
426#[doc(alias = "CCR")]
427pub type Ccr = crate::Reg<ccr::CcrSpec>;
428#[doc = "Clock Control"]
429pub mod ccr;
430#[doc = "TCR (rw) register accessor: Timeout Control\n\nYou can [`read`](crate::Reg::read) this register and get [`tcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcr`]
431module"]
432#[doc(alias = "TCR")]
433pub type Tcr = crate::Reg<tcr::TcrSpec>;
434#[doc = "Timeout Control"]
435pub mod tcr;
436#[doc = "SRR (rw) register accessor: Software Reset\n\nYou can [`read`](crate::Reg::read) this register and get [`srr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`srr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srr`]
437module"]
438#[doc(alias = "SRR")]
439pub type Srr = crate::Reg<srr::SrrSpec>;
440#[doc = "Software Reset"]
441pub mod srr;
442#[doc = "NISTR (rw) register accessor: Normal Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`nistr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nistr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@nistr`]
443module"]
444#[doc(alias = "NISTR")]
445pub type Nistr = crate::Reg<nistr::NistrSpec>;
446#[doc = "Normal Interrupt Status"]
447pub mod nistr;
448#[doc = "NISTR_EMMC_MODE (rw) register accessor: Normal Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`nistr_emmc_mode::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nistr_emmc_mode::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@nistr_emmc_mode`]
449module"]
450#[doc(alias = "NISTR_EMMC_MODE")]
451pub type NistrEmmcMode = crate::Reg<nistr_emmc_mode::NistrEmmcModeSpec>;
452#[doc = "Normal Interrupt Status"]
453pub mod nistr_emmc_mode;
454#[doc = "EISTR (rw) register accessor: Error Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`eistr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eistr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eistr`]
455module"]
456#[doc(alias = "EISTR")]
457pub type Eistr = crate::Reg<eistr::EistrSpec>;
458#[doc = "Error Interrupt Status"]
459pub mod eistr;
460#[doc = "EISTR_EMMC_MODE (rw) register accessor: Error Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`eistr_emmc_mode::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eistr_emmc_mode::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eistr_emmc_mode`]
461module"]
462#[doc(alias = "EISTR_EMMC_MODE")]
463pub type EistrEmmcMode = crate::Reg<eistr_emmc_mode::EistrEmmcModeSpec>;
464#[doc = "Error Interrupt Status"]
465pub mod eistr_emmc_mode;
466#[doc = "NISTER (rw) register accessor: Normal Interrupt Status Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`nister::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nister::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@nister`]
467module"]
468#[doc(alias = "NISTER")]
469pub type Nister = crate::Reg<nister::NisterSpec>;
470#[doc = "Normal Interrupt Status Enable"]
471pub mod nister;
472#[doc = "NISTER_EMMC_MODE (rw) register accessor: Normal Interrupt Status Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`nister_emmc_mode::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nister_emmc_mode::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@nister_emmc_mode`]
473module"]
474#[doc(alias = "NISTER_EMMC_MODE")]
475pub type NisterEmmcMode = crate::Reg<nister_emmc_mode::NisterEmmcModeSpec>;
476#[doc = "Normal Interrupt Status Enable"]
477pub mod nister_emmc_mode;
478#[doc = "EISTER (rw) register accessor: Error Interrupt Status Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`eister::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eister::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eister`]
479module"]
480#[doc(alias = "EISTER")]
481pub type Eister = crate::Reg<eister::EisterSpec>;
482#[doc = "Error Interrupt Status Enable"]
483pub mod eister;
484#[doc = "EISTER_EMMC_MODE (rw) register accessor: Error Interrupt Status Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`eister_emmc_mode::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eister_emmc_mode::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eister_emmc_mode`]
485module"]
486#[doc(alias = "EISTER_EMMC_MODE")]
487pub type EisterEmmcMode = crate::Reg<eister_emmc_mode::EisterEmmcModeSpec>;
488#[doc = "Error Interrupt Status Enable"]
489pub mod eister_emmc_mode;
490#[doc = "NISIER (rw) register accessor: Normal Interrupt Signal Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`nisier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nisier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@nisier`]
491module"]
492#[doc(alias = "NISIER")]
493pub type Nisier = crate::Reg<nisier::NisierSpec>;
494#[doc = "Normal Interrupt Signal Enable"]
495pub mod nisier;
496#[doc = "NISIER_EMMC_MODE (rw) register accessor: Normal Interrupt Signal Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`nisier_emmc_mode::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nisier_emmc_mode::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@nisier_emmc_mode`]
497module"]
498#[doc(alias = "NISIER_EMMC_MODE")]
499pub type NisierEmmcMode = crate::Reg<nisier_emmc_mode::NisierEmmcModeSpec>;
500#[doc = "Normal Interrupt Signal Enable"]
501pub mod nisier_emmc_mode;
502#[doc = "EISIER (rw) register accessor: Error Interrupt Signal Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`eisier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eisier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eisier`]
503module"]
504#[doc(alias = "EISIER")]
505pub type Eisier = crate::Reg<eisier::EisierSpec>;
506#[doc = "Error Interrupt Signal Enable"]
507pub mod eisier;
508#[doc = "EISIER_EMMC_MODE (rw) register accessor: Error Interrupt Signal Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`eisier_emmc_mode::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eisier_emmc_mode::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eisier_emmc_mode`]
509module"]
510#[doc(alias = "EISIER_EMMC_MODE")]
511pub type EisierEmmcMode = crate::Reg<eisier_emmc_mode::EisierEmmcModeSpec>;
512#[doc = "Error Interrupt Signal Enable"]
513pub mod eisier_emmc_mode;
514#[doc = "ACESR (r) register accessor: Auto CMD Error Status\n\nYou can [`read`](crate::Reg::read) this register and get [`acesr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@acesr`]
515module"]
516#[doc(alias = "ACESR")]
517pub type Acesr = crate::Reg<acesr::AcesrSpec>;
518#[doc = "Auto CMD Error Status"]
519pub mod acesr;
520#[doc = "HC2R (rw) register accessor: Host Control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`hc2r::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hc2r::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hc2r`]
521module"]
522#[doc(alias = "HC2R")]
523pub type Hc2r = crate::Reg<hc2r::Hc2rSpec>;
524#[doc = "Host Control 2"]
525pub mod hc2r;
526#[doc = "HC2R_EMMC_MODE (rw) register accessor: Host Control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`hc2r_emmc_mode::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hc2r_emmc_mode::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hc2r_emmc_mode`]
527module"]
528#[doc(alias = "HC2R_EMMC_MODE")]
529pub type Hc2rEmmcMode = crate::Reg<hc2r_emmc_mode::Hc2rEmmcModeSpec>;
530#[doc = "Host Control 2"]
531pub mod hc2r_emmc_mode;
532#[doc = "CA0R (r) register accessor: Capabilities 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ca0r::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ca0r`]
533module"]
534#[doc(alias = "CA0R")]
535pub type Ca0r = crate::Reg<ca0r::Ca0rSpec>;
536#[doc = "Capabilities 0"]
537pub mod ca0r;
538#[doc = "CA1R (r) register accessor: Capabilities 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ca1r::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ca1r`]
539module"]
540#[doc(alias = "CA1R")]
541pub type Ca1r = crate::Reg<ca1r::Ca1rSpec>;
542#[doc = "Capabilities 1"]
543pub mod ca1r;
544#[doc = "MCCAR (r) register accessor: Maximum Current Capabilities\n\nYou can [`read`](crate::Reg::read) this register and get [`mccar::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mccar`]
545module"]
546#[doc(alias = "MCCAR")]
547pub type Mccar = crate::Reg<mccar::MccarSpec>;
548#[doc = "Maximum Current Capabilities"]
549pub mod mccar;
550#[doc = "FERACES (w) register accessor: Force Event for Auto CMD Error Status\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`feraces::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@feraces`]
551module"]
552#[doc(alias = "FERACES")]
553pub type Feraces = crate::Reg<feraces::FeracesSpec>;
554#[doc = "Force Event for Auto CMD Error Status"]
555pub mod feraces;
556#[doc = "FEREIS (w) register accessor: Force Event for Error Interrupt Status\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fereis::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fereis`]
557module"]
558#[doc(alias = "FEREIS")]
559pub type Fereis = crate::Reg<fereis::FereisSpec>;
560#[doc = "Force Event for Error Interrupt Status"]
561pub mod fereis;
562#[doc = "AESR (r) register accessor: ADMA Error Status\n\nYou can [`read`](crate::Reg::read) this register and get [`aesr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aesr`]
563module"]
564#[doc(alias = "AESR")]
565pub type Aesr = crate::Reg<aesr::AesrSpec>;
566#[doc = "ADMA Error Status"]
567pub mod aesr;
568#[doc = "ASAR (rw) register accessor: ADMA System Address\n\nYou can [`read`](crate::Reg::read) this register and get [`asar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`asar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@asar`]
569module"]
570#[doc(alias = "ASAR")]
571pub type Asar = crate::Reg<asar::AsarSpec>;
572#[doc = "ADMA System Address"]
573pub mod asar;
574#[doc = "PVR (rw) register accessor: Preset Value n\n\nYou can [`read`](crate::Reg::read) this register and get [`pvr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pvr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pvr`]
575module"]
576#[doc(alias = "PVR")]
577pub type Pvr = crate::Reg<pvr::PvrSpec>;
578#[doc = "Preset Value n"]
579pub mod pvr;
580#[doc = "SISR (r) register accessor: Slot Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`sisr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sisr`]
581module"]
582#[doc(alias = "SISR")]
583pub type Sisr = crate::Reg<sisr::SisrSpec>;
584#[doc = "Slot Interrupt Status"]
585pub mod sisr;
586#[doc = "HCVR (r) register accessor: Host Controller Version\n\nYou can [`read`](crate::Reg::read) this register and get [`hcvr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hcvr`]
587module"]
588#[doc(alias = "HCVR")]
589pub type Hcvr = crate::Reg<hcvr::HcvrSpec>;
590#[doc = "Host Controller Version"]
591pub mod hcvr;
592#[doc = "APSR (r) register accessor: Additional Present State Register\n\nYou can [`read`](crate::Reg::read) this register and get [`apsr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apsr`]
593module"]
594#[doc(alias = "APSR")]
595pub type Apsr = crate::Reg<apsr::ApsrSpec>;
596#[doc = "Additional Present State Register"]
597pub mod apsr;
598#[doc = "MC1R (rw) register accessor: MMC Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`mc1r::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mc1r::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mc1r`]
599module"]
600#[doc(alias = "MC1R")]
601pub type Mc1r = crate::Reg<mc1r::Mc1rSpec>;
602#[doc = "MMC Control 1"]
603pub mod mc1r;
604#[doc = "MC2R (w) register accessor: MMC Control 2\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mc2r::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mc2r`]
605module"]
606#[doc(alias = "MC2R")]
607pub type Mc2r = crate::Reg<mc2r::Mc2rSpec>;
608#[doc = "MMC Control 2"]
609pub mod mc2r;
610#[doc = "ACR (rw) register accessor: AHB Control\n\nYou can [`read`](crate::Reg::read) this register and get [`acr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`acr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@acr`]
611module"]
612#[doc(alias = "ACR")]
613pub type Acr = crate::Reg<acr::AcrSpec>;
614#[doc = "AHB Control"]
615pub mod acr;
616#[doc = "CC2R (rw) register accessor: Clock Control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`cc2r::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cc2r::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cc2r`]
617module"]
618#[doc(alias = "CC2R")]
619pub type Cc2r = crate::Reg<cc2r::Cc2rSpec>;
620#[doc = "Clock Control 2"]
621pub mod cc2r;
622#[doc = "CACR (rw) register accessor: Capabilities Control\n\nYou can [`read`](crate::Reg::read) this register and get [`cacr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cacr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cacr`]
623module"]
624#[doc(alias = "CACR")]
625pub type Cacr = crate::Reg<cacr::CacrSpec>;
626#[doc = "Capabilities Control"]
627pub mod cacr;
628#[doc = "DBGR (rw) register accessor: Debug\n\nYou can [`read`](crate::Reg::read) this register and get [`dbgr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dbgr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbgr`]
629module"]
630#[doc(alias = "DBGR")]
631pub type Dbgr = crate::Reg<dbgr::DbgrSpec>;
632#[doc = "Debug"]
633pub mod dbgr;
atsamd51p/sdhc0.rs

atsamd51p/
sdhc0.rs
