atsamd51p/ac/
compctrl.rs

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1#[doc = "Register `COMPCTRL[%s]` reader"]
2pub type R = crate::R<CompctrlSpec>;
3#[doc = "Register `COMPCTRL[%s]` writer"]
4pub type W = crate::W<CompctrlSpec>;
5#[doc = "Field `ENABLE` reader - Enable"]
6pub type EnableR = crate::BitReader;
7#[doc = "Field `ENABLE` writer - Enable"]
8pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `SINGLE` reader - Single-Shot Mode"]
10pub type SingleR = crate::BitReader;
11#[doc = "Field `SINGLE` writer - Single-Shot Mode"]
12pub type SingleW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Interrupt Selection\n\nValue on reset: 0"]
14#[derive(Clone, Copy, Debug, PartialEq, Eq)]
15#[repr(u8)]
16pub enum Intselselect {
17    #[doc = "0: Interrupt on comparator output toggle"]
18    Toggle = 0,
19    #[doc = "1: Interrupt on comparator output rising"]
20    Rising = 1,
21    #[doc = "2: Interrupt on comparator output falling"]
22    Falling = 2,
23    #[doc = "3: Interrupt on end of comparison (single-shot mode only)"]
24    Eoc = 3,
25}
26impl From<Intselselect> for u8 {
27    #[inline(always)]
28    fn from(variant: Intselselect) -> Self {
29        variant as _
30    }
31}
32impl crate::FieldSpec for Intselselect {
33    type Ux = u8;
34}
35impl crate::IsEnum for Intselselect {}
36#[doc = "Field `INTSEL` reader - Interrupt Selection"]
37pub type IntselR = crate::FieldReader<Intselselect>;
38impl IntselR {
39    #[doc = "Get enumerated values variant"]
40    #[inline(always)]
41    pub const fn variant(&self) -> Intselselect {
42        match self.bits {
43            0 => Intselselect::Toggle,
44            1 => Intselselect::Rising,
45            2 => Intselselect::Falling,
46            3 => Intselselect::Eoc,
47            _ => unreachable!(),
48        }
49    }
50    #[doc = "Interrupt on comparator output toggle"]
51    #[inline(always)]
52    pub fn is_toggle(&self) -> bool {
53        *self == Intselselect::Toggle
54    }
55    #[doc = "Interrupt on comparator output rising"]
56    #[inline(always)]
57    pub fn is_rising(&self) -> bool {
58        *self == Intselselect::Rising
59    }
60    #[doc = "Interrupt on comparator output falling"]
61    #[inline(always)]
62    pub fn is_falling(&self) -> bool {
63        *self == Intselselect::Falling
64    }
65    #[doc = "Interrupt on end of comparison (single-shot mode only)"]
66    #[inline(always)]
67    pub fn is_eoc(&self) -> bool {
68        *self == Intselselect::Eoc
69    }
70}
71#[doc = "Field `INTSEL` writer - Interrupt Selection"]
72pub type IntselW<'a, REG> = crate::FieldWriter<'a, REG, 2, Intselselect, crate::Safe>;
73impl<'a, REG> IntselW<'a, REG>
74where
75    REG: crate::Writable + crate::RegisterSpec,
76    REG::Ux: From<u8>,
77{
78    #[doc = "Interrupt on comparator output toggle"]
79    #[inline(always)]
80    pub fn toggle(self) -> &'a mut crate::W<REG> {
81        self.variant(Intselselect::Toggle)
82    }
83    #[doc = "Interrupt on comparator output rising"]
84    #[inline(always)]
85    pub fn rising(self) -> &'a mut crate::W<REG> {
86        self.variant(Intselselect::Rising)
87    }
88    #[doc = "Interrupt on comparator output falling"]
89    #[inline(always)]
90    pub fn falling(self) -> &'a mut crate::W<REG> {
91        self.variant(Intselselect::Falling)
92    }
93    #[doc = "Interrupt on end of comparison (single-shot mode only)"]
94    #[inline(always)]
95    pub fn eoc(self) -> &'a mut crate::W<REG> {
96        self.variant(Intselselect::Eoc)
97    }
98}
99#[doc = "Field `RUNSTDBY` reader - Run in Standby"]
100pub type RunstdbyR = crate::BitReader;
101#[doc = "Field `RUNSTDBY` writer - Run in Standby"]
102pub type RunstdbyW<'a, REG> = crate::BitWriter<'a, REG>;
103#[doc = "Negative Input Mux Selection\n\nValue on reset: 0"]
104#[derive(Clone, Copy, Debug, PartialEq, Eq)]
105#[repr(u8)]
106pub enum Muxnegselect {
107    #[doc = "0: I/O pin 0"]
108    Pin0 = 0,
109    #[doc = "1: I/O pin 1"]
110    Pin1 = 1,
111    #[doc = "2: I/O pin 2"]
112    Pin2 = 2,
113    #[doc = "3: I/O pin 3"]
114    Pin3 = 3,
115    #[doc = "4: Ground"]
116    Gnd = 4,
117    #[doc = "5: VDD scaler"]
118    Vscale = 5,
119    #[doc = "6: Internal bandgap voltage"]
120    Bandgap = 6,
121    #[doc = "7: DAC output"]
122    Dac = 7,
123}
124impl From<Muxnegselect> for u8 {
125    #[inline(always)]
126    fn from(variant: Muxnegselect) -> Self {
127        variant as _
128    }
129}
130impl crate::FieldSpec for Muxnegselect {
131    type Ux = u8;
132}
133impl crate::IsEnum for Muxnegselect {}
134#[doc = "Field `MUXNEG` reader - Negative Input Mux Selection"]
135pub type MuxnegR = crate::FieldReader<Muxnegselect>;
136impl MuxnegR {
137    #[doc = "Get enumerated values variant"]
138    #[inline(always)]
139    pub const fn variant(&self) -> Muxnegselect {
140        match self.bits {
141            0 => Muxnegselect::Pin0,
142            1 => Muxnegselect::Pin1,
143            2 => Muxnegselect::Pin2,
144            3 => Muxnegselect::Pin3,
145            4 => Muxnegselect::Gnd,
146            5 => Muxnegselect::Vscale,
147            6 => Muxnegselect::Bandgap,
148            7 => Muxnegselect::Dac,
149            _ => unreachable!(),
150        }
151    }
152    #[doc = "I/O pin 0"]
153    #[inline(always)]
154    pub fn is_pin0(&self) -> bool {
155        *self == Muxnegselect::Pin0
156    }
157    #[doc = "I/O pin 1"]
158    #[inline(always)]
159    pub fn is_pin1(&self) -> bool {
160        *self == Muxnegselect::Pin1
161    }
162    #[doc = "I/O pin 2"]
163    #[inline(always)]
164    pub fn is_pin2(&self) -> bool {
165        *self == Muxnegselect::Pin2
166    }
167    #[doc = "I/O pin 3"]
168    #[inline(always)]
169    pub fn is_pin3(&self) -> bool {
170        *self == Muxnegselect::Pin3
171    }
172    #[doc = "Ground"]
173    #[inline(always)]
174    pub fn is_gnd(&self) -> bool {
175        *self == Muxnegselect::Gnd
176    }
177    #[doc = "VDD scaler"]
178    #[inline(always)]
179    pub fn is_vscale(&self) -> bool {
180        *self == Muxnegselect::Vscale
181    }
182    #[doc = "Internal bandgap voltage"]
183    #[inline(always)]
184    pub fn is_bandgap(&self) -> bool {
185        *self == Muxnegselect::Bandgap
186    }
187    #[doc = "DAC output"]
188    #[inline(always)]
189    pub fn is_dac(&self) -> bool {
190        *self == Muxnegselect::Dac
191    }
192}
193#[doc = "Field `MUXNEG` writer - Negative Input Mux Selection"]
194pub type MuxnegW<'a, REG> = crate::FieldWriter<'a, REG, 3, Muxnegselect, crate::Safe>;
195impl<'a, REG> MuxnegW<'a, REG>
196where
197    REG: crate::Writable + crate::RegisterSpec,
198    REG::Ux: From<u8>,
199{
200    #[doc = "I/O pin 0"]
201    #[inline(always)]
202    pub fn pin0(self) -> &'a mut crate::W<REG> {
203        self.variant(Muxnegselect::Pin0)
204    }
205    #[doc = "I/O pin 1"]
206    #[inline(always)]
207    pub fn pin1(self) -> &'a mut crate::W<REG> {
208        self.variant(Muxnegselect::Pin1)
209    }
210    #[doc = "I/O pin 2"]
211    #[inline(always)]
212    pub fn pin2(self) -> &'a mut crate::W<REG> {
213        self.variant(Muxnegselect::Pin2)
214    }
215    #[doc = "I/O pin 3"]
216    #[inline(always)]
217    pub fn pin3(self) -> &'a mut crate::W<REG> {
218        self.variant(Muxnegselect::Pin3)
219    }
220    #[doc = "Ground"]
221    #[inline(always)]
222    pub fn gnd(self) -> &'a mut crate::W<REG> {
223        self.variant(Muxnegselect::Gnd)
224    }
225    #[doc = "VDD scaler"]
226    #[inline(always)]
227    pub fn vscale(self) -> &'a mut crate::W<REG> {
228        self.variant(Muxnegselect::Vscale)
229    }
230    #[doc = "Internal bandgap voltage"]
231    #[inline(always)]
232    pub fn bandgap(self) -> &'a mut crate::W<REG> {
233        self.variant(Muxnegselect::Bandgap)
234    }
235    #[doc = "DAC output"]
236    #[inline(always)]
237    pub fn dac(self) -> &'a mut crate::W<REG> {
238        self.variant(Muxnegselect::Dac)
239    }
240}
241#[doc = "Positive Input Mux Selection\n\nValue on reset: 0"]
242#[derive(Clone, Copy, Debug, PartialEq, Eq)]
243#[repr(u8)]
244pub enum Muxposselect {
245    #[doc = "0: I/O pin 0"]
246    Pin0 = 0,
247    #[doc = "1: I/O pin 1"]
248    Pin1 = 1,
249    #[doc = "2: I/O pin 2"]
250    Pin2 = 2,
251    #[doc = "3: I/O pin 3"]
252    Pin3 = 3,
253    #[doc = "4: VDD Scaler"]
254    Vscale = 4,
255}
256impl From<Muxposselect> for u8 {
257    #[inline(always)]
258    fn from(variant: Muxposselect) -> Self {
259        variant as _
260    }
261}
262impl crate::FieldSpec for Muxposselect {
263    type Ux = u8;
264}
265impl crate::IsEnum for Muxposselect {}
266#[doc = "Field `MUXPOS` reader - Positive Input Mux Selection"]
267pub type MuxposR = crate::FieldReader<Muxposselect>;
268impl MuxposR {
269    #[doc = "Get enumerated values variant"]
270    #[inline(always)]
271    pub const fn variant(&self) -> Option<Muxposselect> {
272        match self.bits {
273            0 => Some(Muxposselect::Pin0),
274            1 => Some(Muxposselect::Pin1),
275            2 => Some(Muxposselect::Pin2),
276            3 => Some(Muxposselect::Pin3),
277            4 => Some(Muxposselect::Vscale),
278            _ => None,
279        }
280    }
281    #[doc = "I/O pin 0"]
282    #[inline(always)]
283    pub fn is_pin0(&self) -> bool {
284        *self == Muxposselect::Pin0
285    }
286    #[doc = "I/O pin 1"]
287    #[inline(always)]
288    pub fn is_pin1(&self) -> bool {
289        *self == Muxposselect::Pin1
290    }
291    #[doc = "I/O pin 2"]
292    #[inline(always)]
293    pub fn is_pin2(&self) -> bool {
294        *self == Muxposselect::Pin2
295    }
296    #[doc = "I/O pin 3"]
297    #[inline(always)]
298    pub fn is_pin3(&self) -> bool {
299        *self == Muxposselect::Pin3
300    }
301    #[doc = "VDD Scaler"]
302    #[inline(always)]
303    pub fn is_vscale(&self) -> bool {
304        *self == Muxposselect::Vscale
305    }
306}
307#[doc = "Field `MUXPOS` writer - Positive Input Mux Selection"]
308pub type MuxposW<'a, REG> = crate::FieldWriter<'a, REG, 3, Muxposselect>;
309impl<'a, REG> MuxposW<'a, REG>
310where
311    REG: crate::Writable + crate::RegisterSpec,
312    REG::Ux: From<u8>,
313{
314    #[doc = "I/O pin 0"]
315    #[inline(always)]
316    pub fn pin0(self) -> &'a mut crate::W<REG> {
317        self.variant(Muxposselect::Pin0)
318    }
319    #[doc = "I/O pin 1"]
320    #[inline(always)]
321    pub fn pin1(self) -> &'a mut crate::W<REG> {
322        self.variant(Muxposselect::Pin1)
323    }
324    #[doc = "I/O pin 2"]
325    #[inline(always)]
326    pub fn pin2(self) -> &'a mut crate::W<REG> {
327        self.variant(Muxposselect::Pin2)
328    }
329    #[doc = "I/O pin 3"]
330    #[inline(always)]
331    pub fn pin3(self) -> &'a mut crate::W<REG> {
332        self.variant(Muxposselect::Pin3)
333    }
334    #[doc = "VDD Scaler"]
335    #[inline(always)]
336    pub fn vscale(self) -> &'a mut crate::W<REG> {
337        self.variant(Muxposselect::Vscale)
338    }
339}
340#[doc = "Field `SWAP` reader - Swap Inputs and Invert"]
341pub type SwapR = crate::BitReader;
342#[doc = "Field `SWAP` writer - Swap Inputs and Invert"]
343pub type SwapW<'a, REG> = crate::BitWriter<'a, REG>;
344#[doc = "Speed Selection\n\nValue on reset: 0"]
345#[derive(Clone, Copy, Debug, PartialEq, Eq)]
346#[repr(u8)]
347pub enum Speedselect {
348    #[doc = "3: High speed"]
349    High = 3,
350}
351impl From<Speedselect> for u8 {
352    #[inline(always)]
353    fn from(variant: Speedselect) -> Self {
354        variant as _
355    }
356}
357impl crate::FieldSpec for Speedselect {
358    type Ux = u8;
359}
360impl crate::IsEnum for Speedselect {}
361#[doc = "Field `SPEED` reader - Speed Selection"]
362pub type SpeedR = crate::FieldReader<Speedselect>;
363impl SpeedR {
364    #[doc = "Get enumerated values variant"]
365    #[inline(always)]
366    pub const fn variant(&self) -> Option<Speedselect> {
367        match self.bits {
368            3 => Some(Speedselect::High),
369            _ => None,
370        }
371    }
372    #[doc = "High speed"]
373    #[inline(always)]
374    pub fn is_high(&self) -> bool {
375        *self == Speedselect::High
376    }
377}
378#[doc = "Field `SPEED` writer - Speed Selection"]
379pub type SpeedW<'a, REG> = crate::FieldWriter<'a, REG, 2, Speedselect>;
380impl<'a, REG> SpeedW<'a, REG>
381where
382    REG: crate::Writable + crate::RegisterSpec,
383    REG::Ux: From<u8>,
384{
385    #[doc = "High speed"]
386    #[inline(always)]
387    pub fn high(self) -> &'a mut crate::W<REG> {
388        self.variant(Speedselect::High)
389    }
390}
391#[doc = "Field `HYSTEN` reader - Hysteresis Enable"]
392pub type HystenR = crate::BitReader;
393#[doc = "Field `HYSTEN` writer - Hysteresis Enable"]
394pub type HystenW<'a, REG> = crate::BitWriter<'a, REG>;
395#[doc = "Hysteresis Level\n\nValue on reset: 0"]
396#[derive(Clone, Copy, Debug, PartialEq, Eq)]
397#[repr(u8)]
398pub enum Hystselect {
399    #[doc = "0: 25mV"]
400    Hyst25 = 0,
401    #[doc = "1: 50mV"]
402    Hyst50 = 1,
403    #[doc = "2: 75mV"]
404    Hyst75 = 2,
405    #[doc = "3: 100mV"]
406    Hyst100 = 3,
407}
408impl From<Hystselect> for u8 {
409    #[inline(always)]
410    fn from(variant: Hystselect) -> Self {
411        variant as _
412    }
413}
414impl crate::FieldSpec for Hystselect {
415    type Ux = u8;
416}
417impl crate::IsEnum for Hystselect {}
418#[doc = "Field `HYST` reader - Hysteresis Level"]
419pub type HystR = crate::FieldReader<Hystselect>;
420impl HystR {
421    #[doc = "Get enumerated values variant"]
422    #[inline(always)]
423    pub const fn variant(&self) -> Hystselect {
424        match self.bits {
425            0 => Hystselect::Hyst25,
426            1 => Hystselect::Hyst50,
427            2 => Hystselect::Hyst75,
428            3 => Hystselect::Hyst100,
429            _ => unreachable!(),
430        }
431    }
432    #[doc = "25mV"]
433    #[inline(always)]
434    pub fn is_hyst25(&self) -> bool {
435        *self == Hystselect::Hyst25
436    }
437    #[doc = "50mV"]
438    #[inline(always)]
439    pub fn is_hyst50(&self) -> bool {
440        *self == Hystselect::Hyst50
441    }
442    #[doc = "75mV"]
443    #[inline(always)]
444    pub fn is_hyst75(&self) -> bool {
445        *self == Hystselect::Hyst75
446    }
447    #[doc = "100mV"]
448    #[inline(always)]
449    pub fn is_hyst100(&self) -> bool {
450        *self == Hystselect::Hyst100
451    }
452}
453#[doc = "Field `HYST` writer - Hysteresis Level"]
454pub type HystW<'a, REG> = crate::FieldWriter<'a, REG, 2, Hystselect, crate::Safe>;
455impl<'a, REG> HystW<'a, REG>
456where
457    REG: crate::Writable + crate::RegisterSpec,
458    REG::Ux: From<u8>,
459{
460    #[doc = "25mV"]
461    #[inline(always)]
462    pub fn hyst25(self) -> &'a mut crate::W<REG> {
463        self.variant(Hystselect::Hyst25)
464    }
465    #[doc = "50mV"]
466    #[inline(always)]
467    pub fn hyst50(self) -> &'a mut crate::W<REG> {
468        self.variant(Hystselect::Hyst50)
469    }
470    #[doc = "75mV"]
471    #[inline(always)]
472    pub fn hyst75(self) -> &'a mut crate::W<REG> {
473        self.variant(Hystselect::Hyst75)
474    }
475    #[doc = "100mV"]
476    #[inline(always)]
477    pub fn hyst100(self) -> &'a mut crate::W<REG> {
478        self.variant(Hystselect::Hyst100)
479    }
480}
481#[doc = "Filter Length\n\nValue on reset: 0"]
482#[derive(Clone, Copy, Debug, PartialEq, Eq)]
483#[repr(u8)]
484pub enum Flenselect {
485    #[doc = "0: No filtering"]
486    Off = 0,
487    #[doc = "1: 3-bit majority function (2 of 3)"]
488    Maj3 = 1,
489    #[doc = "2: 5-bit majority function (3 of 5)"]
490    Maj5 = 2,
491}
492impl From<Flenselect> for u8 {
493    #[inline(always)]
494    fn from(variant: Flenselect) -> Self {
495        variant as _
496    }
497}
498impl crate::FieldSpec for Flenselect {
499    type Ux = u8;
500}
501impl crate::IsEnum for Flenselect {}
502#[doc = "Field `FLEN` reader - Filter Length"]
503pub type FlenR = crate::FieldReader<Flenselect>;
504impl FlenR {
505    #[doc = "Get enumerated values variant"]
506    #[inline(always)]
507    pub const fn variant(&self) -> Option<Flenselect> {
508        match self.bits {
509            0 => Some(Flenselect::Off),
510            1 => Some(Flenselect::Maj3),
511            2 => Some(Flenselect::Maj5),
512            _ => None,
513        }
514    }
515    #[doc = "No filtering"]
516    #[inline(always)]
517    pub fn is_off(&self) -> bool {
518        *self == Flenselect::Off
519    }
520    #[doc = "3-bit majority function (2 of 3)"]
521    #[inline(always)]
522    pub fn is_maj3(&self) -> bool {
523        *self == Flenselect::Maj3
524    }
525    #[doc = "5-bit majority function (3 of 5)"]
526    #[inline(always)]
527    pub fn is_maj5(&self) -> bool {
528        *self == Flenselect::Maj5
529    }
530}
531#[doc = "Field `FLEN` writer - Filter Length"]
532pub type FlenW<'a, REG> = crate::FieldWriter<'a, REG, 3, Flenselect>;
533impl<'a, REG> FlenW<'a, REG>
534where
535    REG: crate::Writable + crate::RegisterSpec,
536    REG::Ux: From<u8>,
537{
538    #[doc = "No filtering"]
539    #[inline(always)]
540    pub fn off(self) -> &'a mut crate::W<REG> {
541        self.variant(Flenselect::Off)
542    }
543    #[doc = "3-bit majority function (2 of 3)"]
544    #[inline(always)]
545    pub fn maj3(self) -> &'a mut crate::W<REG> {
546        self.variant(Flenselect::Maj3)
547    }
548    #[doc = "5-bit majority function (3 of 5)"]
549    #[inline(always)]
550    pub fn maj5(self) -> &'a mut crate::W<REG> {
551        self.variant(Flenselect::Maj5)
552    }
553}
554#[doc = "Output\n\nValue on reset: 0"]
555#[derive(Clone, Copy, Debug, PartialEq, Eq)]
556#[repr(u8)]
557pub enum Outselect {
558    #[doc = "0: The output of COMPn is not routed to the COMPn I/O port"]
559    Off = 0,
560    #[doc = "1: The asynchronous output of COMPn is routed to the COMPn I/O port"]
561    Async = 1,
562    #[doc = "2: The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port"]
563    Sync = 2,
564}
565impl From<Outselect> for u8 {
566    #[inline(always)]
567    fn from(variant: Outselect) -> Self {
568        variant as _
569    }
570}
571impl crate::FieldSpec for Outselect {
572    type Ux = u8;
573}
574impl crate::IsEnum for Outselect {}
575#[doc = "Field `OUT` reader - Output"]
576pub type OutR = crate::FieldReader<Outselect>;
577impl OutR {
578    #[doc = "Get enumerated values variant"]
579    #[inline(always)]
580    pub const fn variant(&self) -> Option<Outselect> {
581        match self.bits {
582            0 => Some(Outselect::Off),
583            1 => Some(Outselect::Async),
584            2 => Some(Outselect::Sync),
585            _ => None,
586        }
587    }
588    #[doc = "The output of COMPn is not routed to the COMPn I/O port"]
589    #[inline(always)]
590    pub fn is_off(&self) -> bool {
591        *self == Outselect::Off
592    }
593    #[doc = "The asynchronous output of COMPn is routed to the COMPn I/O port"]
594    #[inline(always)]
595    pub fn is_async(&self) -> bool {
596        *self == Outselect::Async
597    }
598    #[doc = "The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port"]
599    #[inline(always)]
600    pub fn is_sync(&self) -> bool {
601        *self == Outselect::Sync
602    }
603}
604#[doc = "Field `OUT` writer - Output"]
605pub type OutW<'a, REG> = crate::FieldWriter<'a, REG, 2, Outselect>;
606impl<'a, REG> OutW<'a, REG>
607where
608    REG: crate::Writable + crate::RegisterSpec,
609    REG::Ux: From<u8>,
610{
611    #[doc = "The output of COMPn is not routed to the COMPn I/O port"]
612    #[inline(always)]
613    pub fn off(self) -> &'a mut crate::W<REG> {
614        self.variant(Outselect::Off)
615    }
616    #[doc = "The asynchronous output of COMPn is routed to the COMPn I/O port"]
617    #[inline(always)]
618    pub fn async_(self) -> &'a mut crate::W<REG> {
619        self.variant(Outselect::Async)
620    }
621    #[doc = "The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port"]
622    #[inline(always)]
623    pub fn sync(self) -> &'a mut crate::W<REG> {
624        self.variant(Outselect::Sync)
625    }
626}
627impl R {
628    #[doc = "Bit 1 - Enable"]
629    #[inline(always)]
630    pub fn enable(&self) -> EnableR {
631        EnableR::new(((self.bits >> 1) & 1) != 0)
632    }
633    #[doc = "Bit 2 - Single-Shot Mode"]
634    #[inline(always)]
635    pub fn single(&self) -> SingleR {
636        SingleR::new(((self.bits >> 2) & 1) != 0)
637    }
638    #[doc = "Bits 3:4 - Interrupt Selection"]
639    #[inline(always)]
640    pub fn intsel(&self) -> IntselR {
641        IntselR::new(((self.bits >> 3) & 3) as u8)
642    }
643    #[doc = "Bit 6 - Run in Standby"]
644    #[inline(always)]
645    pub fn runstdby(&self) -> RunstdbyR {
646        RunstdbyR::new(((self.bits >> 6) & 1) != 0)
647    }
648    #[doc = "Bits 8:10 - Negative Input Mux Selection"]
649    #[inline(always)]
650    pub fn muxneg(&self) -> MuxnegR {
651        MuxnegR::new(((self.bits >> 8) & 7) as u8)
652    }
653    #[doc = "Bits 12:14 - Positive Input Mux Selection"]
654    #[inline(always)]
655    pub fn muxpos(&self) -> MuxposR {
656        MuxposR::new(((self.bits >> 12) & 7) as u8)
657    }
658    #[doc = "Bit 15 - Swap Inputs and Invert"]
659    #[inline(always)]
660    pub fn swap(&self) -> SwapR {
661        SwapR::new(((self.bits >> 15) & 1) != 0)
662    }
663    #[doc = "Bits 16:17 - Speed Selection"]
664    #[inline(always)]
665    pub fn speed(&self) -> SpeedR {
666        SpeedR::new(((self.bits >> 16) & 3) as u8)
667    }
668    #[doc = "Bit 19 - Hysteresis Enable"]
669    #[inline(always)]
670    pub fn hysten(&self) -> HystenR {
671        HystenR::new(((self.bits >> 19) & 1) != 0)
672    }
673    #[doc = "Bits 20:21 - Hysteresis Level"]
674    #[inline(always)]
675    pub fn hyst(&self) -> HystR {
676        HystR::new(((self.bits >> 20) & 3) as u8)
677    }
678    #[doc = "Bits 24:26 - Filter Length"]
679    #[inline(always)]
680    pub fn flen(&self) -> FlenR {
681        FlenR::new(((self.bits >> 24) & 7) as u8)
682    }
683    #[doc = "Bits 28:29 - Output"]
684    #[inline(always)]
685    pub fn out(&self) -> OutR {
686        OutR::new(((self.bits >> 28) & 3) as u8)
687    }
688}
689impl W {
690    #[doc = "Bit 1 - Enable"]
691    #[inline(always)]
692    #[must_use]
693    pub fn enable(&mut self) -> EnableW<CompctrlSpec> {
694        EnableW::new(self, 1)
695    }
696    #[doc = "Bit 2 - Single-Shot Mode"]
697    #[inline(always)]
698    #[must_use]
699    pub fn single(&mut self) -> SingleW<CompctrlSpec> {
700        SingleW::new(self, 2)
701    }
702    #[doc = "Bits 3:4 - Interrupt Selection"]
703    #[inline(always)]
704    #[must_use]
705    pub fn intsel(&mut self) -> IntselW<CompctrlSpec> {
706        IntselW::new(self, 3)
707    }
708    #[doc = "Bit 6 - Run in Standby"]
709    #[inline(always)]
710    #[must_use]
711    pub fn runstdby(&mut self) -> RunstdbyW<CompctrlSpec> {
712        RunstdbyW::new(self, 6)
713    }
714    #[doc = "Bits 8:10 - Negative Input Mux Selection"]
715    #[inline(always)]
716    #[must_use]
717    pub fn muxneg(&mut self) -> MuxnegW<CompctrlSpec> {
718        MuxnegW::new(self, 8)
719    }
720    #[doc = "Bits 12:14 - Positive Input Mux Selection"]
721    #[inline(always)]
722    #[must_use]
723    pub fn muxpos(&mut self) -> MuxposW<CompctrlSpec> {
724        MuxposW::new(self, 12)
725    }
726    #[doc = "Bit 15 - Swap Inputs and Invert"]
727    #[inline(always)]
728    #[must_use]
729    pub fn swap(&mut self) -> SwapW<CompctrlSpec> {
730        SwapW::new(self, 15)
731    }
732    #[doc = "Bits 16:17 - Speed Selection"]
733    #[inline(always)]
734    #[must_use]
735    pub fn speed(&mut self) -> SpeedW<CompctrlSpec> {
736        SpeedW::new(self, 16)
737    }
738    #[doc = "Bit 19 - Hysteresis Enable"]
739    #[inline(always)]
740    #[must_use]
741    pub fn hysten(&mut self) -> HystenW<CompctrlSpec> {
742        HystenW::new(self, 19)
743    }
744    #[doc = "Bits 20:21 - Hysteresis Level"]
745    #[inline(always)]
746    #[must_use]
747    pub fn hyst(&mut self) -> HystW<CompctrlSpec> {
748        HystW::new(self, 20)
749    }
750    #[doc = "Bits 24:26 - Filter Length"]
751    #[inline(always)]
752    #[must_use]
753    pub fn flen(&mut self) -> FlenW<CompctrlSpec> {
754        FlenW::new(self, 24)
755    }
756    #[doc = "Bits 28:29 - Output"]
757    #[inline(always)]
758    #[must_use]
759    pub fn out(&mut self) -> OutW<CompctrlSpec> {
760        OutW::new(self, 28)
761    }
762}
763#[doc = "Comparator Control n\n\nYou can [`read`](crate::Reg::read) this register and get [`compctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`compctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
764pub struct CompctrlSpec;
765impl crate::RegisterSpec for CompctrlSpec {
766    type Ux = u32;
767}
768#[doc = "`read()` method returns [`compctrl::R`](R) reader structure"]
769impl crate::Readable for CompctrlSpec {}
770#[doc = "`write(|w| ..)` method takes [`compctrl::W`](W) writer structure"]
771impl crate::Writable for CompctrlSpec {
772    type Safety = crate::Unsafe;
773    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
774    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
775}
776#[doc = "`reset()` method sets COMPCTRL[%s]
777to value 0"]
778impl crate::Resettable for CompctrlSpec {
779    const RESET_VALUE: u32 = 0;
780}
atsamd51p/ac/compctrl.rs

atsamd51p/ac/
compctrl.rs
