atsamd51p/sdhc0/
mc1r.rs

1#[doc = "Register `MC1R` reader"]
2pub type R = crate::R<Mc1rSpec>;
3#[doc = "Register `MC1R` writer"]
4pub type W = crate::W<Mc1rSpec>;
5#[doc = "e.MMC Command Type\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7#[repr(u8)]
8pub enum Cmdtypselect {
9    #[doc = "0: Not a MMC specific command"]
10    Normal = 0,
11    #[doc = "1: Wait IRQ Command"]
12    Waitirq = 1,
13    #[doc = "2: Stream Command"]
14    Stream = 2,
15    #[doc = "3: Boot Command"]
16    Boot = 3,
17}
18impl From<Cmdtypselect> for u8 {
19    #[inline(always)]
20    fn from(variant: Cmdtypselect) -> Self {
21        variant as _
22    }
23}
24impl crate::FieldSpec for Cmdtypselect {
25    type Ux = u8;
26}
27impl crate::IsEnum for Cmdtypselect {}
28#[doc = "Field `CMDTYP` reader - e.MMC Command Type"]
29pub type CmdtypR = crate::FieldReader<Cmdtypselect>;
30impl CmdtypR {
31    #[doc = "Get enumerated values variant"]
32    #[inline(always)]
33    pub const fn variant(&self) -> Cmdtypselect {
34        match self.bits {
35            0 => Cmdtypselect::Normal,
36            1 => Cmdtypselect::Waitirq,
37            2 => Cmdtypselect::Stream,
38            3 => Cmdtypselect::Boot,
39            _ => unreachable!(),
40        }
41    }
42    #[doc = "Not a MMC specific command"]
43    #[inline(always)]
44    pub fn is_normal(&self) -> bool {
45        *self == Cmdtypselect::Normal
46    }
47    #[doc = "Wait IRQ Command"]
48    #[inline(always)]
49    pub fn is_waitirq(&self) -> bool {
50        *self == Cmdtypselect::Waitirq
51    }
52    #[doc = "Stream Command"]
53    #[inline(always)]
54    pub fn is_stream(&self) -> bool {
55        *self == Cmdtypselect::Stream
56    }
57    #[doc = "Boot Command"]
58    #[inline(always)]
59    pub fn is_boot(&self) -> bool {
60        *self == Cmdtypselect::Boot
61    }
62}
63#[doc = "Field `CMDTYP` writer - e.MMC Command Type"]
64pub type CmdtypW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cmdtypselect, crate::Safe>;
65impl<'a, REG> CmdtypW<'a, REG>
66where
67    REG: crate::Writable + crate::RegisterSpec,
68    REG::Ux: From<u8>,
69{
70    #[doc = "Not a MMC specific command"]
71    #[inline(always)]
72    pub fn normal(self) -> &'a mut crate::W<REG> {
73        self.variant(Cmdtypselect::Normal)
74    }
75    #[doc = "Wait IRQ Command"]
76    #[inline(always)]
77    pub fn waitirq(self) -> &'a mut crate::W<REG> {
78        self.variant(Cmdtypselect::Waitirq)
79    }
80    #[doc = "Stream Command"]
81    #[inline(always)]
82    pub fn stream(self) -> &'a mut crate::W<REG> {
83        self.variant(Cmdtypselect::Stream)
84    }
85    #[doc = "Boot Command"]
86    #[inline(always)]
87    pub fn boot(self) -> &'a mut crate::W<REG> {
88        self.variant(Cmdtypselect::Boot)
89    }
90}
91#[doc = "Field `DDR` reader - e.MMC HSDDR Mode"]
92pub type DdrR = crate::BitReader;
93#[doc = "Field `DDR` writer - e.MMC HSDDR Mode"]
94pub type DdrW<'a, REG> = crate::BitWriter<'a, REG>;
95#[doc = "Field `OPD` reader - e.MMC Open Drain Mode"]
96pub type OpdR = crate::BitReader;
97#[doc = "Field `OPD` writer - e.MMC Open Drain Mode"]
98pub type OpdW<'a, REG> = crate::BitWriter<'a, REG>;
99#[doc = "Field `BOOTA` reader - e.MMC Boot Acknowledge Enable"]
100pub type BootaR = crate::BitReader;
101#[doc = "Field `BOOTA` writer - e.MMC Boot Acknowledge Enable"]
102pub type BootaW<'a, REG> = crate::BitWriter<'a, REG>;
103#[doc = "Field `RSTN` reader - e.MMC Reset Signal"]
104pub type RstnR = crate::BitReader;
105#[doc = "Field `RSTN` writer - e.MMC Reset Signal"]
106pub type RstnW<'a, REG> = crate::BitWriter<'a, REG>;
107#[doc = "Field `FCD` reader - e.MMC Force Card Detect"]
108pub type FcdR = crate::BitReader;
109#[doc = "Field `FCD` writer - e.MMC Force Card Detect"]
110pub type FcdW<'a, REG> = crate::BitWriter<'a, REG>;
111impl R {
112    #[doc = "Bits 0:1 - e.MMC Command Type"]
113    #[inline(always)]
114    pub fn cmdtyp(&self) -> CmdtypR {
115        CmdtypR::new(self.bits & 3)
116    }
117    #[doc = "Bit 3 - e.MMC HSDDR Mode"]
118    #[inline(always)]
119    pub fn ddr(&self) -> DdrR {
120        DdrR::new(((self.bits >> 3) & 1) != 0)
121    }
122    #[doc = "Bit 4 - e.MMC Open Drain Mode"]
123    #[inline(always)]
124    pub fn opd(&self) -> OpdR {
125        OpdR::new(((self.bits >> 4) & 1) != 0)
126    }
127    #[doc = "Bit 5 - e.MMC Boot Acknowledge Enable"]
128    #[inline(always)]
129    pub fn boota(&self) -> BootaR {
130        BootaR::new(((self.bits >> 5) & 1) != 0)
131    }
132    #[doc = "Bit 6 - e.MMC Reset Signal"]
133    #[inline(always)]
134    pub fn rstn(&self) -> RstnR {
135        RstnR::new(((self.bits >> 6) & 1) != 0)
136    }
137    #[doc = "Bit 7 - e.MMC Force Card Detect"]
138    #[inline(always)]
139    pub fn fcd(&self) -> FcdR {
140        FcdR::new(((self.bits >> 7) & 1) != 0)
141    }
142}
143impl W {
144    #[doc = "Bits 0:1 - e.MMC Command Type"]
145    #[inline(always)]
146    #[must_use]
147    pub fn cmdtyp(&mut self) -> CmdtypW<Mc1rSpec> {
148        CmdtypW::new(self, 0)
149    }
150    #[doc = "Bit 3 - e.MMC HSDDR Mode"]
151    #[inline(always)]
152    #[must_use]
153    pub fn ddr(&mut self) -> DdrW<Mc1rSpec> {
154        DdrW::new(self, 3)
155    }
156    #[doc = "Bit 4 - e.MMC Open Drain Mode"]
157    #[inline(always)]
158    #[must_use]
159    pub fn opd(&mut self) -> OpdW<Mc1rSpec> {
160        OpdW::new(self, 4)
161    }
162    #[doc = "Bit 5 - e.MMC Boot Acknowledge Enable"]
163    #[inline(always)]
164    #[must_use]
165    pub fn boota(&mut self) -> BootaW<Mc1rSpec> {
166        BootaW::new(self, 5)
167    }
168    #[doc = "Bit 6 - e.MMC Reset Signal"]
169    #[inline(always)]
170    #[must_use]
171    pub fn rstn(&mut self) -> RstnW<Mc1rSpec> {
172        RstnW::new(self, 6)
173    }
174    #[doc = "Bit 7 - e.MMC Force Card Detect"]
175    #[inline(always)]
176    #[must_use]
177    pub fn fcd(&mut self) -> FcdW<Mc1rSpec> {
178        FcdW::new(self, 7)
179    }
180}
181#[doc = "MMC Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`mc1r::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mc1r::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
182pub struct Mc1rSpec;
183impl crate::RegisterSpec for Mc1rSpec {
184    type Ux = u8;
185}
186#[doc = "`read()` method returns [`mc1r::R`](R) reader structure"]
187impl crate::Readable for Mc1rSpec {}
188#[doc = "`write(|w| ..)` method takes [`mc1r::W`](W) writer structure"]
189impl crate::Writable for Mc1rSpec {
190    type Safety = crate::Unsafe;
191    const ZERO_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
192    const ONE_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
193}
194#[doc = "`reset()` method sets MC1R to value 0"]
195impl crate::Resettable for Mc1rSpec {
196    const RESET_VALUE: u8 = 0;
197}
atsamd51p/sdhc0/mc1r.rs

atsamd51p/sdhc0/
mc1r.rs
