atsamd51p/icm/
cfg.rs

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1#[doc = "Register `CFG` reader"]
2pub type R = crate::R<CfgSpec>;
3#[doc = "Register `CFG` writer"]
4pub type W = crate::W<CfgSpec>;
5#[doc = "Field `WBDIS` reader - Write Back Disable"]
6pub type WbdisR = crate::BitReader;
7#[doc = "Field `WBDIS` writer - Write Back Disable"]
8pub type WbdisW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `EOMDIS` reader - End of Monitoring Disable"]
10pub type EomdisR = crate::BitReader;
11#[doc = "Field `EOMDIS` writer - End of Monitoring Disable"]
12pub type EomdisW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `SLBDIS` reader - Secondary List Branching Disable"]
14pub type SlbdisR = crate::BitReader;
15#[doc = "Field `SLBDIS` writer - Secondary List Branching Disable"]
16pub type SlbdisW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `BBC` reader - Bus Burden Control"]
18pub type BbcR = crate::FieldReader;
19#[doc = "Field `BBC` writer - Bus Burden Control"]
20pub type BbcW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
21#[doc = "Field `ASCD` reader - Automatic Switch To Compare Digest"]
22pub type AscdR = crate::BitReader;
23#[doc = "Field `ASCD` writer - Automatic Switch To Compare Digest"]
24pub type AscdW<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `DUALBUFF` reader - Dual Input Buffer"]
26pub type DualbuffR = crate::BitReader;
27#[doc = "Field `DUALBUFF` writer - Dual Input Buffer"]
28pub type DualbuffW<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `UIHASH` reader - User Initial Hash Value"]
30pub type UihashR = crate::BitReader;
31#[doc = "Field `UIHASH` writer - User Initial Hash Value"]
32pub type UihashW<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "User SHA Algorithm\n\nValue on reset: 0"]
34#[derive(Clone, Copy, Debug, PartialEq, Eq)]
35#[repr(u8)]
36pub enum Ualgoselect {
37    #[doc = "0: SHA1 Algorithm"]
38    Sha1 = 0,
39    #[doc = "1: SHA256 Algorithm"]
40    Sha256 = 1,
41    #[doc = "4: SHA224 Algorithm"]
42    Sha224 = 4,
43}
44impl From<Ualgoselect> for u8 {
45    #[inline(always)]
46    fn from(variant: Ualgoselect) -> Self {
47        variant as _
48    }
49}
50impl crate::FieldSpec for Ualgoselect {
51    type Ux = u8;
52}
53impl crate::IsEnum for Ualgoselect {}
54#[doc = "Field `UALGO` reader - User SHA Algorithm"]
55pub type UalgoR = crate::FieldReader<Ualgoselect>;
56impl UalgoR {
57    #[doc = "Get enumerated values variant"]
58    #[inline(always)]
59    pub const fn variant(&self) -> Option<Ualgoselect> {
60        match self.bits {
61            0 => Some(Ualgoselect::Sha1),
62            1 => Some(Ualgoselect::Sha256),
63            4 => Some(Ualgoselect::Sha224),
64            _ => None,
65        }
66    }
67    #[doc = "SHA1 Algorithm"]
68    #[inline(always)]
69    pub fn is_sha1(&self) -> bool {
70        *self == Ualgoselect::Sha1
71    }
72    #[doc = "SHA256 Algorithm"]
73    #[inline(always)]
74    pub fn is_sha256(&self) -> bool {
75        *self == Ualgoselect::Sha256
76    }
77    #[doc = "SHA224 Algorithm"]
78    #[inline(always)]
79    pub fn is_sha224(&self) -> bool {
80        *self == Ualgoselect::Sha224
81    }
82}
83#[doc = "Field `UALGO` writer - User SHA Algorithm"]
84pub type UalgoW<'a, REG> = crate::FieldWriter<'a, REG, 3, Ualgoselect>;
85impl<'a, REG> UalgoW<'a, REG>
86where
87    REG: crate::Writable + crate::RegisterSpec,
88    REG::Ux: From<u8>,
89{
90    #[doc = "SHA1 Algorithm"]
91    #[inline(always)]
92    pub fn sha1(self) -> &'a mut crate::W<REG> {
93        self.variant(Ualgoselect::Sha1)
94    }
95    #[doc = "SHA256 Algorithm"]
96    #[inline(always)]
97    pub fn sha256(self) -> &'a mut crate::W<REG> {
98        self.variant(Ualgoselect::Sha256)
99    }
100    #[doc = "SHA224 Algorithm"]
101    #[inline(always)]
102    pub fn sha224(self) -> &'a mut crate::W<REG> {
103        self.variant(Ualgoselect::Sha224)
104    }
105}
106impl R {
107    #[doc = "Bit 0 - Write Back Disable"]
108    #[inline(always)]
109    pub fn wbdis(&self) -> WbdisR {
110        WbdisR::new((self.bits & 1) != 0)
111    }
112    #[doc = "Bit 1 - End of Monitoring Disable"]
113    #[inline(always)]
114    pub fn eomdis(&self) -> EomdisR {
115        EomdisR::new(((self.bits >> 1) & 1) != 0)
116    }
117    #[doc = "Bit 2 - Secondary List Branching Disable"]
118    #[inline(always)]
119    pub fn slbdis(&self) -> SlbdisR {
120        SlbdisR::new(((self.bits >> 2) & 1) != 0)
121    }
122    #[doc = "Bits 4:7 - Bus Burden Control"]
123    #[inline(always)]
124    pub fn bbc(&self) -> BbcR {
125        BbcR::new(((self.bits >> 4) & 0x0f) as u8)
126    }
127    #[doc = "Bit 8 - Automatic Switch To Compare Digest"]
128    #[inline(always)]
129    pub fn ascd(&self) -> AscdR {
130        AscdR::new(((self.bits >> 8) & 1) != 0)
131    }
132    #[doc = "Bit 9 - Dual Input Buffer"]
133    #[inline(always)]
134    pub fn dualbuff(&self) -> DualbuffR {
135        DualbuffR::new(((self.bits >> 9) & 1) != 0)
136    }
137    #[doc = "Bit 12 - User Initial Hash Value"]
138    #[inline(always)]
139    pub fn uihash(&self) -> UihashR {
140        UihashR::new(((self.bits >> 12) & 1) != 0)
141    }
142    #[doc = "Bits 13:15 - User SHA Algorithm"]
143    #[inline(always)]
144    pub fn ualgo(&self) -> UalgoR {
145        UalgoR::new(((self.bits >> 13) & 7) as u8)
146    }
147}
148impl W {
149    #[doc = "Bit 0 - Write Back Disable"]
150    #[inline(always)]
151    #[must_use]
152    pub fn wbdis(&mut self) -> WbdisW<CfgSpec> {
153        WbdisW::new(self, 0)
154    }
155    #[doc = "Bit 1 - End of Monitoring Disable"]
156    #[inline(always)]
157    #[must_use]
158    pub fn eomdis(&mut self) -> EomdisW<CfgSpec> {
159        EomdisW::new(self, 1)
160    }
161    #[doc = "Bit 2 - Secondary List Branching Disable"]
162    #[inline(always)]
163    #[must_use]
164    pub fn slbdis(&mut self) -> SlbdisW<CfgSpec> {
165        SlbdisW::new(self, 2)
166    }
167    #[doc = "Bits 4:7 - Bus Burden Control"]
168    #[inline(always)]
169    #[must_use]
170    pub fn bbc(&mut self) -> BbcW<CfgSpec> {
171        BbcW::new(self, 4)
172    }
173    #[doc = "Bit 8 - Automatic Switch To Compare Digest"]
174    #[inline(always)]
175    #[must_use]
176    pub fn ascd(&mut self) -> AscdW<CfgSpec> {
177        AscdW::new(self, 8)
178    }
179    #[doc = "Bit 9 - Dual Input Buffer"]
180    #[inline(always)]
181    #[must_use]
182    pub fn dualbuff(&mut self) -> DualbuffW<CfgSpec> {
183        DualbuffW::new(self, 9)
184    }
185    #[doc = "Bit 12 - User Initial Hash Value"]
186    #[inline(always)]
187    #[must_use]
188    pub fn uihash(&mut self) -> UihashW<CfgSpec> {
189        UihashW::new(self, 12)
190    }
191    #[doc = "Bits 13:15 - User SHA Algorithm"]
192    #[inline(always)]
193    #[must_use]
194    pub fn ualgo(&mut self) -> UalgoW<CfgSpec> {
195        UalgoW::new(self, 13)
196    }
197}
198#[doc = "Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
199pub struct CfgSpec;
200impl crate::RegisterSpec for CfgSpec {
201    type Ux = u32;
202}
203#[doc = "`read()` method returns [`cfg::R`](R) reader structure"]
204impl crate::Readable for CfgSpec {}
205#[doc = "`write(|w| ..)` method takes [`cfg::W`](W) writer structure"]
206impl crate::Writable for CfgSpec {
207    type Safety = crate::Unsafe;
208    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
209    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
210}
211#[doc = "`reset()` method sets CFG to value 0"]
212impl crate::Resettable for CfgSpec {
213    const RESET_VALUE: u32 = 0;
214}
atsamd51p/icm/cfg.rs

atsamd51p/icm/
cfg.rs
