atsamd51p/supc/
vreg.rs

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1#[doc = "Register `VREG` reader"]
2pub type R = crate::R<VregSpec>;
3#[doc = "Register `VREG` writer"]
4pub type W = crate::W<VregSpec>;
5#[doc = "Field `ENABLE` reader - Enable"]
6pub type EnableR = crate::BitReader;
7#[doc = "Field `ENABLE` writer - Enable"]
8pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Voltage Regulator Selection\n\nValue on reset: 0"]
10#[derive(Clone, Copy, Debug, PartialEq, Eq)]
11pub enum Selselect {
12    #[doc = "0: LDO selection"]
13    Ldo = 0,
14    #[doc = "1: Buck selection"]
15    Buck = 1,
16}
17impl From<Selselect> for bool {
18    #[inline(always)]
19    fn from(variant: Selselect) -> Self {
20        variant as u8 != 0
21    }
22}
23#[doc = "Field `SEL` reader - Voltage Regulator Selection"]
24pub type SelR = crate::BitReader<Selselect>;
25impl SelR {
26    #[doc = "Get enumerated values variant"]
27    #[inline(always)]
28    pub const fn variant(&self) -> Selselect {
29        match self.bits {
30            false => Selselect::Ldo,
31            true => Selselect::Buck,
32        }
33    }
34    #[doc = "LDO selection"]
35    #[inline(always)]
36    pub fn is_ldo(&self) -> bool {
37        *self == Selselect::Ldo
38    }
39    #[doc = "Buck selection"]
40    #[inline(always)]
41    pub fn is_buck(&self) -> bool {
42        *self == Selselect::Buck
43    }
44}
45#[doc = "Field `SEL` writer - Voltage Regulator Selection"]
46pub type SelW<'a, REG> = crate::BitWriter<'a, REG, Selselect>;
47impl<'a, REG> SelW<'a, REG>
48where
49    REG: crate::Writable + crate::RegisterSpec,
50{
51    #[doc = "LDO selection"]
52    #[inline(always)]
53    pub fn ldo(self) -> &'a mut crate::W<REG> {
54        self.variant(Selselect::Ldo)
55    }
56    #[doc = "Buck selection"]
57    #[inline(always)]
58    pub fn buck(self) -> &'a mut crate::W<REG> {
59        self.variant(Selselect::Buck)
60    }
61}
62#[doc = "Field `RUNBKUP` reader - Run in Backup mode"]
63pub type RunbkupR = crate::BitReader;
64#[doc = "Field `RUNBKUP` writer - Run in Backup mode"]
65pub type RunbkupW<'a, REG> = crate::BitWriter<'a, REG>;
66#[doc = "Field `VSEN` reader - Voltage Scaling Enable"]
67pub type VsenR = crate::BitReader;
68#[doc = "Field `VSEN` writer - Voltage Scaling Enable"]
69pub type VsenW<'a, REG> = crate::BitWriter<'a, REG>;
70#[doc = "Field `VSPER` reader - Voltage Scaling Period"]
71pub type VsperR = crate::FieldReader;
72#[doc = "Field `VSPER` writer - Voltage Scaling Period"]
73pub type VsperW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
74impl R {
75    #[doc = "Bit 1 - Enable"]
76    #[inline(always)]
77    pub fn enable(&self) -> EnableR {
78        EnableR::new(((self.bits >> 1) & 1) != 0)
79    }
80    #[doc = "Bit 2 - Voltage Regulator Selection"]
81    #[inline(always)]
82    pub fn sel(&self) -> SelR {
83        SelR::new(((self.bits >> 2) & 1) != 0)
84    }
85    #[doc = "Bit 7 - Run in Backup mode"]
86    #[inline(always)]
87    pub fn runbkup(&self) -> RunbkupR {
88        RunbkupR::new(((self.bits >> 7) & 1) != 0)
89    }
90    #[doc = "Bit 16 - Voltage Scaling Enable"]
91    #[inline(always)]
92    pub fn vsen(&self) -> VsenR {
93        VsenR::new(((self.bits >> 16) & 1) != 0)
94    }
95    #[doc = "Bits 24:26 - Voltage Scaling Period"]
96    #[inline(always)]
97    pub fn vsper(&self) -> VsperR {
98        VsperR::new(((self.bits >> 24) & 7) as u8)
99    }
100}
101impl W {
102    #[doc = "Bit 1 - Enable"]
103    #[inline(always)]
104    #[must_use]
105    pub fn enable(&mut self) -> EnableW<VregSpec> {
106        EnableW::new(self, 1)
107    }
108    #[doc = "Bit 2 - Voltage Regulator Selection"]
109    #[inline(always)]
110    #[must_use]
111    pub fn sel(&mut self) -> SelW<VregSpec> {
112        SelW::new(self, 2)
113    }
114    #[doc = "Bit 7 - Run in Backup mode"]
115    #[inline(always)]
116    #[must_use]
117    pub fn runbkup(&mut self) -> RunbkupW<VregSpec> {
118        RunbkupW::new(self, 7)
119    }
120    #[doc = "Bit 16 - Voltage Scaling Enable"]
121    #[inline(always)]
122    #[must_use]
123    pub fn vsen(&mut self) -> VsenW<VregSpec> {
124        VsenW::new(self, 16)
125    }
126    #[doc = "Bits 24:26 - Voltage Scaling Period"]
127    #[inline(always)]
128    #[must_use]
129    pub fn vsper(&mut self) -> VsperW<VregSpec> {
130        VsperW::new(self, 24)
131    }
132}
133#[doc = "VREG Control\n\nYou can [`read`](crate::Reg::read) this register and get [`vreg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`vreg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
134pub struct VregSpec;
135impl crate::RegisterSpec for VregSpec {
136    type Ux = u32;
137}
138#[doc = "`read()` method returns [`vreg::R`](R) reader structure"]
139impl crate::Readable for VregSpec {}
140#[doc = "`write(|w| ..)` method takes [`vreg::W`](W) writer structure"]
141impl crate::Writable for VregSpec {
142    type Safety = crate::Unsafe;
143    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
144    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
145}
146#[doc = "`reset()` method sets VREG to value 0x02"]
147impl crate::Resettable for VregSpec {
148    const RESET_VALUE: u32 = 0x02;
149}
atsamd51p/supc/vreg.rs

atsamd51p/supc/
vreg.rs
