atsamd51p/dmac/channel/
chctrla.rs

1#[doc = "Register `CHCTRLA` reader"]
2pub type R = crate::R<ChctrlaSpec>;
3#[doc = "Register `CHCTRLA` writer"]
4pub type W = crate::W<ChctrlaSpec>;
5#[doc = "Field `SWRST` reader - Channel Software Reset"]
6pub type SwrstR = crate::BitReader;
7#[doc = "Field `SWRST` writer - Channel Software Reset"]
8pub type SwrstW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `ENABLE` reader - Channel Enable"]
10pub type EnableR = crate::BitReader;
11#[doc = "Field `ENABLE` writer - Channel Enable"]
12pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `RUNSTDBY` reader - Channel Run in Standby"]
14pub type RunstdbyR = crate::BitReader;
15#[doc = "Field `RUNSTDBY` writer - Channel Run in Standby"]
16pub type RunstdbyW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Trigger Source\n\nValue on reset: 0"]
18#[derive(Clone, Copy, Debug, PartialEq, Eq)]
19#[repr(u8)]
20pub enum Trigsrcselect {
21    #[doc = "0: Only software/event triggers"]
22    Disable = 0,
23    #[doc = "1: DMA RTC timestamp trigger"]
24    RtcTimestamp = 1,
25    #[doc = "2: DMAC ID for DCC0 register"]
26    DsuDcc0 = 2,
27    #[doc = "3: DMAC ID for DCC1 register"]
28    DsuDcc1 = 3,
29    #[doc = "4: Index of DMA RX trigger"]
30    Sercom0Rx = 4,
31    #[doc = "5: Index of DMA TX trigger"]
32    Sercom0Tx = 5,
33    #[doc = "6: Index of DMA RX trigger"]
34    Sercom1Rx = 6,
35    #[doc = "7: Index of DMA TX trigger"]
36    Sercom1Tx = 7,
37    #[doc = "8: Index of DMA RX trigger"]
38    Sercom2Rx = 8,
39    #[doc = "9: Index of DMA TX trigger"]
40    Sercom2Tx = 9,
41    #[doc = "10: Index of DMA RX trigger"]
42    Sercom3Rx = 10,
43    #[doc = "11: Index of DMA TX trigger"]
44    Sercom3Tx = 11,
45    #[doc = "12: Index of DMA RX trigger"]
46    Sercom4Rx = 12,
47    #[doc = "13: Index of DMA TX trigger"]
48    Sercom4Tx = 13,
49    #[doc = "14: Index of DMA RX trigger"]
50    Sercom5Rx = 14,
51    #[doc = "15: Index of DMA TX trigger"]
52    Sercom5Tx = 15,
53    #[doc = "16: Index of DMA RX trigger"]
54    Sercom6Rx = 16,
55    #[doc = "17: Index of DMA TX trigger"]
56    Sercom6Tx = 17,
57    #[doc = "18: Index of DMA RX trigger"]
58    Sercom7Rx = 18,
59    #[doc = "19: Index of DMA TX trigger"]
60    Sercom7Tx = 19,
61    #[doc = "20: DMA CAN Debug Req"]
62    Can0Debug = 20,
63    #[doc = "21: DMA CAN Debug Req"]
64    Can1Debug = 21,
65    #[doc = "22: DMA overflow/underflow/retrigger trigger"]
66    Tcc0Ovf = 22,
67    #[doc = "23: Indexes of DMA Match/Compare triggers"]
68    Tcc0Mc0 = 23,
69    #[doc = "24: Indexes of DMA Match/Compare triggers"]
70    Tcc0Mc1 = 24,
71    #[doc = "25: Indexes of DMA Match/Compare triggers"]
72    Tcc0Mc2 = 25,
73    #[doc = "26: Indexes of DMA Match/Compare triggers"]
74    Tcc0Mc3 = 26,
75    #[doc = "27: Indexes of DMA Match/Compare triggers"]
76    Tcc0Mc4 = 27,
77    #[doc = "28: Indexes of DMA Match/Compare triggers"]
78    Tcc0Mc5 = 28,
79    #[doc = "29: DMA overflow/underflow/retrigger trigger"]
80    Tcc1Ovf = 29,
81    #[doc = "30: Indexes of DMA Match/Compare triggers"]
82    Tcc1Mc0 = 30,
83    #[doc = "31: Indexes of DMA Match/Compare triggers"]
84    Tcc1Mc1 = 31,
85    #[doc = "32: Indexes of DMA Match/Compare triggers"]
86    Tcc1Mc2 = 32,
87    #[doc = "33: Indexes of DMA Match/Compare triggers"]
88    Tcc1Mc3 = 33,
89    #[doc = "34: DMA overflow/underflow/retrigger trigger"]
90    Tcc2Ovf = 34,
91    #[doc = "35: Indexes of DMA Match/Compare triggers"]
92    Tcc2Mc0 = 35,
93    #[doc = "36: Indexes of DMA Match/Compare triggers"]
94    Tcc2Mc1 = 36,
95    #[doc = "37: Indexes of DMA Match/Compare triggers"]
96    Tcc2Mc2 = 37,
97    #[doc = "38: DMA overflow/underflow/retrigger trigger"]
98    Tcc3Ovf = 38,
99    #[doc = "39: Indexes of DMA Match/Compare triggers"]
100    Tcc3Mc0 = 39,
101    #[doc = "40: Indexes of DMA Match/Compare triggers"]
102    Tcc3Mc1 = 40,
103    #[doc = "41: DMA overflow/underflow/retrigger trigger"]
104    Tcc4Ovf = 41,
105    #[doc = "42: Indexes of DMA Match/Compare triggers"]
106    Tcc4Mc0 = 42,
107    #[doc = "43: Indexes of DMA Match/Compare triggers"]
108    Tcc4Mc1 = 43,
109    #[doc = "44: Indexes of DMA Overflow trigger"]
110    Tc0Ovf = 44,
111    #[doc = "45: Indexes of DMA Match/Compare triggers"]
112    Tc0Mc0 = 45,
113    #[doc = "46: Indexes of DMA Match/Compare triggers"]
114    Tc0Mc1 = 46,
115    #[doc = "47: Indexes of DMA Overflow trigger"]
116    Tc1Ovf = 47,
117    #[doc = "48: Indexes of DMA Match/Compare triggers"]
118    Tc1Mc0 = 48,
119    #[doc = "49: Indexes of DMA Match/Compare triggers"]
120    Tc1Mc1 = 49,
121    #[doc = "50: Indexes of DMA Overflow trigger"]
122    Tc2Ovf = 50,
123    #[doc = "51: Indexes of DMA Match/Compare triggers"]
124    Tc2Mc0 = 51,
125    #[doc = "52: Indexes of DMA Match/Compare triggers"]
126    Tc2Mc1 = 52,
127    #[doc = "53: Indexes of DMA Overflow trigger"]
128    Tc3Ovf = 53,
129    #[doc = "54: Indexes of DMA Match/Compare triggers"]
130    Tc3Mc0 = 54,
131    #[doc = "55: Indexes of DMA Match/Compare triggers"]
132    Tc3Mc1 = 55,
133    #[doc = "56: Indexes of DMA Overflow trigger"]
134    Tc4Ovf = 56,
135    #[doc = "57: Indexes of DMA Match/Compare triggers"]
136    Tc4Mc0 = 57,
137    #[doc = "58: Indexes of DMA Match/Compare triggers"]
138    Tc4Mc1 = 58,
139    #[doc = "59: Indexes of DMA Overflow trigger"]
140    Tc5Ovf = 59,
141    #[doc = "60: Indexes of DMA Match/Compare triggers"]
142    Tc5Mc0 = 60,
143    #[doc = "61: Indexes of DMA Match/Compare triggers"]
144    Tc5Mc1 = 61,
145    #[doc = "62: Indexes of DMA Overflow trigger"]
146    Tc6Ovf = 62,
147    #[doc = "63: Indexes of DMA Match/Compare triggers"]
148    Tc6Mc0 = 63,
149    #[doc = "64: Indexes of DMA Match/Compare triggers"]
150    Tc6Mc1 = 64,
151    #[doc = "65: Indexes of DMA Overflow trigger"]
152    Tc7Ovf = 65,
153    #[doc = "66: Indexes of DMA Match/Compare triggers"]
154    Tc7Mc0 = 66,
155    #[doc = "67: Indexes of DMA Match/Compare triggers"]
156    Tc7Mc1 = 67,
157    #[doc = "68: index of DMA RESRDY trigger"]
158    Adc0Resrdy = 68,
159    #[doc = "69: Index of DMA SEQ trigger"]
160    Adc0Seq = 69,
161    #[doc = "70: Index of DMA RESRDY trigger"]
162    Adc1Resrdy = 70,
163    #[doc = "71: Index of DMA SEQ trigger"]
164    Adc1Seq = 71,
165    #[doc = "72: DMA DAC Empty Req"]
166    DacEmpty0 = 72,
167    #[doc = "73: DMA DAC Empty Req"]
168    DacEmpty1 = 73,
169    #[doc = "74: DMA DAC Result Ready Req"]
170    DacResrdy0 = 74,
171    #[doc = "75: DMA DAC Result Ready Req"]
172    DacResrdy1 = 75,
173    #[doc = "76: Indexes of DMA RX triggers"]
174    I2sRx0 = 76,
175    #[doc = "77: Indexes of DMA RX triggers"]
176    I2sRx1 = 77,
177    #[doc = "78: Indexes of DMA TX triggers"]
178    I2sTx0 = 78,
179    #[doc = "79: Indexes of DMA TX triggers"]
180    I2sTx1 = 79,
181    #[doc = "80: Indexes of PCC RX trigger"]
182    PccRx = 80,
183    #[doc = "81: DMA DATA Write trigger"]
184    AesWr = 81,
185    #[doc = "82: DMA DATA Read trigger"]
186    AesRd = 82,
187    #[doc = "83: Indexes of QSPI RX trigger"]
188    QspiRx = 83,
189    #[doc = "84: Indexes of QSPI TX trigger"]
190    QspiTx = 84,
191}
192impl From<Trigsrcselect> for u8 {
193    #[inline(always)]
194    fn from(variant: Trigsrcselect) -> Self {
195        variant as _
196    }
197}
198impl crate::FieldSpec for Trigsrcselect {
199    type Ux = u8;
200}
201impl crate::IsEnum for Trigsrcselect {}
202#[doc = "Field `TRIGSRC` reader - Trigger Source"]
203pub type TrigsrcR = crate::FieldReader<Trigsrcselect>;
204impl TrigsrcR {
205    #[doc = "Get enumerated values variant"]
206    #[inline(always)]
207    pub const fn variant(&self) -> Option<Trigsrcselect> {
208        match self.bits {
209            0 => Some(Trigsrcselect::Disable),
210            1 => Some(Trigsrcselect::RtcTimestamp),
211            2 => Some(Trigsrcselect::DsuDcc0),
212            3 => Some(Trigsrcselect::DsuDcc1),
213            4 => Some(Trigsrcselect::Sercom0Rx),
214            5 => Some(Trigsrcselect::Sercom0Tx),
215            6 => Some(Trigsrcselect::Sercom1Rx),
216            7 => Some(Trigsrcselect::Sercom1Tx),
217            8 => Some(Trigsrcselect::Sercom2Rx),
218            9 => Some(Trigsrcselect::Sercom2Tx),
219            10 => Some(Trigsrcselect::Sercom3Rx),
220            11 => Some(Trigsrcselect::Sercom3Tx),
221            12 => Some(Trigsrcselect::Sercom4Rx),
222            13 => Some(Trigsrcselect::Sercom4Tx),
223            14 => Some(Trigsrcselect::Sercom5Rx),
224            15 => Some(Trigsrcselect::Sercom5Tx),
225            16 => Some(Trigsrcselect::Sercom6Rx),
226            17 => Some(Trigsrcselect::Sercom6Tx),
227            18 => Some(Trigsrcselect::Sercom7Rx),
228            19 => Some(Trigsrcselect::Sercom7Tx),
229            20 => Some(Trigsrcselect::Can0Debug),
230            21 => Some(Trigsrcselect::Can1Debug),
231            22 => Some(Trigsrcselect::Tcc0Ovf),
232            23 => Some(Trigsrcselect::Tcc0Mc0),
233            24 => Some(Trigsrcselect::Tcc0Mc1),
234            25 => Some(Trigsrcselect::Tcc0Mc2),
235            26 => Some(Trigsrcselect::Tcc0Mc3),
236            27 => Some(Trigsrcselect::Tcc0Mc4),
237            28 => Some(Trigsrcselect::Tcc0Mc5),
238            29 => Some(Trigsrcselect::Tcc1Ovf),
239            30 => Some(Trigsrcselect::Tcc1Mc0),
240            31 => Some(Trigsrcselect::Tcc1Mc1),
241            32 => Some(Trigsrcselect::Tcc1Mc2),
242            33 => Some(Trigsrcselect::Tcc1Mc3),
243            34 => Some(Trigsrcselect::Tcc2Ovf),
244            35 => Some(Trigsrcselect::Tcc2Mc0),
245            36 => Some(Trigsrcselect::Tcc2Mc1),
246            37 => Some(Trigsrcselect::Tcc2Mc2),
247            38 => Some(Trigsrcselect::Tcc3Ovf),
248            39 => Some(Trigsrcselect::Tcc3Mc0),
249            40 => Some(Trigsrcselect::Tcc3Mc1),
250            41 => Some(Trigsrcselect::Tcc4Ovf),
251            42 => Some(Trigsrcselect::Tcc4Mc0),
252            43 => Some(Trigsrcselect::Tcc4Mc1),
253            44 => Some(Trigsrcselect::Tc0Ovf),
254            45 => Some(Trigsrcselect::Tc0Mc0),
255            46 => Some(Trigsrcselect::Tc0Mc1),
256            47 => Some(Trigsrcselect::Tc1Ovf),
257            48 => Some(Trigsrcselect::Tc1Mc0),
258            49 => Some(Trigsrcselect::Tc1Mc1),
259            50 => Some(Trigsrcselect::Tc2Ovf),
260            51 => Some(Trigsrcselect::Tc2Mc0),
261            52 => Some(Trigsrcselect::Tc2Mc1),
262            53 => Some(Trigsrcselect::Tc3Ovf),
263            54 => Some(Trigsrcselect::Tc3Mc0),
264            55 => Some(Trigsrcselect::Tc3Mc1),
265            56 => Some(Trigsrcselect::Tc4Ovf),
266            57 => Some(Trigsrcselect::Tc4Mc0),
267            58 => Some(Trigsrcselect::Tc4Mc1),
268            59 => Some(Trigsrcselect::Tc5Ovf),
269            60 => Some(Trigsrcselect::Tc5Mc0),
270            61 => Some(Trigsrcselect::Tc5Mc1),
271            62 => Some(Trigsrcselect::Tc6Ovf),
272            63 => Some(Trigsrcselect::Tc6Mc0),
273            64 => Some(Trigsrcselect::Tc6Mc1),
274            65 => Some(Trigsrcselect::Tc7Ovf),
275            66 => Some(Trigsrcselect::Tc7Mc0),
276            67 => Some(Trigsrcselect::Tc7Mc1),
277            68 => Some(Trigsrcselect::Adc0Resrdy),
278            69 => Some(Trigsrcselect::Adc0Seq),
279            70 => Some(Trigsrcselect::Adc1Resrdy),
280            71 => Some(Trigsrcselect::Adc1Seq),
281            72 => Some(Trigsrcselect::DacEmpty0),
282            73 => Some(Trigsrcselect::DacEmpty1),
283            74 => Some(Trigsrcselect::DacResrdy0),
284            75 => Some(Trigsrcselect::DacResrdy1),
285            76 => Some(Trigsrcselect::I2sRx0),
286            77 => Some(Trigsrcselect::I2sRx1),
287            78 => Some(Trigsrcselect::I2sTx0),
288            79 => Some(Trigsrcselect::I2sTx1),
289            80 => Some(Trigsrcselect::PccRx),
290            81 => Some(Trigsrcselect::AesWr),
291            82 => Some(Trigsrcselect::AesRd),
292            83 => Some(Trigsrcselect::QspiRx),
293            84 => Some(Trigsrcselect::QspiTx),
294            _ => None,
295        }
296    }
297    #[doc = "Only software/event triggers"]
298    #[inline(always)]
299    pub fn is_disable(&self) -> bool {
300        *self == Trigsrcselect::Disable
301    }
302    #[doc = "DMA RTC timestamp trigger"]
303    #[inline(always)]
304    pub fn is_rtc_timestamp(&self) -> bool {
305        *self == Trigsrcselect::RtcTimestamp
306    }
307    #[doc = "DMAC ID for DCC0 register"]
308    #[inline(always)]
309    pub fn is_dsu_dcc0(&self) -> bool {
310        *self == Trigsrcselect::DsuDcc0
311    }
312    #[doc = "DMAC ID for DCC1 register"]
313    #[inline(always)]
314    pub fn is_dsu_dcc1(&self) -> bool {
315        *self == Trigsrcselect::DsuDcc1
316    }
317    #[doc = "Index of DMA RX trigger"]
318    #[inline(always)]
319    pub fn is_sercom0_rx(&self) -> bool {
320        *self == Trigsrcselect::Sercom0Rx
321    }
322    #[doc = "Index of DMA TX trigger"]
323    #[inline(always)]
324    pub fn is_sercom0_tx(&self) -> bool {
325        *self == Trigsrcselect::Sercom0Tx
326    }
327    #[doc = "Index of DMA RX trigger"]
328    #[inline(always)]
329    pub fn is_sercom1_rx(&self) -> bool {
330        *self == Trigsrcselect::Sercom1Rx
331    }
332    #[doc = "Index of DMA TX trigger"]
333    #[inline(always)]
334    pub fn is_sercom1_tx(&self) -> bool {
335        *self == Trigsrcselect::Sercom1Tx
336    }
337    #[doc = "Index of DMA RX trigger"]
338    #[inline(always)]
339    pub fn is_sercom2_rx(&self) -> bool {
340        *self == Trigsrcselect::Sercom2Rx
341    }
342    #[doc = "Index of DMA TX trigger"]
343    #[inline(always)]
344    pub fn is_sercom2_tx(&self) -> bool {
345        *self == Trigsrcselect::Sercom2Tx
346    }
347    #[doc = "Index of DMA RX trigger"]
348    #[inline(always)]
349    pub fn is_sercom3_rx(&self) -> bool {
350        *self == Trigsrcselect::Sercom3Rx
351    }
352    #[doc = "Index of DMA TX trigger"]
353    #[inline(always)]
354    pub fn is_sercom3_tx(&self) -> bool {
355        *self == Trigsrcselect::Sercom3Tx
356    }
357    #[doc = "Index of DMA RX trigger"]
358    #[inline(always)]
359    pub fn is_sercom4_rx(&self) -> bool {
360        *self == Trigsrcselect::Sercom4Rx
361    }
362    #[doc = "Index of DMA TX trigger"]
363    #[inline(always)]
364    pub fn is_sercom4_tx(&self) -> bool {
365        *self == Trigsrcselect::Sercom4Tx
366    }
367    #[doc = "Index of DMA RX trigger"]
368    #[inline(always)]
369    pub fn is_sercom5_rx(&self) -> bool {
370        *self == Trigsrcselect::Sercom5Rx
371    }
372    #[doc = "Index of DMA TX trigger"]
373    #[inline(always)]
374    pub fn is_sercom5_tx(&self) -> bool {
375        *self == Trigsrcselect::Sercom5Tx
376    }
377    #[doc = "Index of DMA RX trigger"]
378    #[inline(always)]
379    pub fn is_sercom6_rx(&self) -> bool {
380        *self == Trigsrcselect::Sercom6Rx
381    }
382    #[doc = "Index of DMA TX trigger"]
383    #[inline(always)]
384    pub fn is_sercom6_tx(&self) -> bool {
385        *self == Trigsrcselect::Sercom6Tx
386    }
387    #[doc = "Index of DMA RX trigger"]
388    #[inline(always)]
389    pub fn is_sercom7_rx(&self) -> bool {
390        *self == Trigsrcselect::Sercom7Rx
391    }
392    #[doc = "Index of DMA TX trigger"]
393    #[inline(always)]
394    pub fn is_sercom7_tx(&self) -> bool {
395        *self == Trigsrcselect::Sercom7Tx
396    }
397    #[doc = "DMA CAN Debug Req"]
398    #[inline(always)]
399    pub fn is_can0_debug(&self) -> bool {
400        *self == Trigsrcselect::Can0Debug
401    }
402    #[doc = "DMA CAN Debug Req"]
403    #[inline(always)]
404    pub fn is_can1_debug(&self) -> bool {
405        *self == Trigsrcselect::Can1Debug
406    }
407    #[doc = "DMA overflow/underflow/retrigger trigger"]
408    #[inline(always)]
409    pub fn is_tcc0_ovf(&self) -> bool {
410        *self == Trigsrcselect::Tcc0Ovf
411    }
412    #[doc = "Indexes of DMA Match/Compare triggers"]
413    #[inline(always)]
414    pub fn is_tcc0_mc_0(&self) -> bool {
415        *self == Trigsrcselect::Tcc0Mc0
416    }
417    #[doc = "Indexes of DMA Match/Compare triggers"]
418    #[inline(always)]
419    pub fn is_tcc0_mc_1(&self) -> bool {
420        *self == Trigsrcselect::Tcc0Mc1
421    }
422    #[doc = "Indexes of DMA Match/Compare triggers"]
423    #[inline(always)]
424    pub fn is_tcc0_mc_2(&self) -> bool {
425        *self == Trigsrcselect::Tcc0Mc2
426    }
427    #[doc = "Indexes of DMA Match/Compare triggers"]
428    #[inline(always)]
429    pub fn is_tcc0_mc_3(&self) -> bool {
430        *self == Trigsrcselect::Tcc0Mc3
431    }
432    #[doc = "Indexes of DMA Match/Compare triggers"]
433    #[inline(always)]
434    pub fn is_tcc0_mc_4(&self) -> bool {
435        *self == Trigsrcselect::Tcc0Mc4
436    }
437    #[doc = "Indexes of DMA Match/Compare triggers"]
438    #[inline(always)]
439    pub fn is_tcc0_mc_5(&self) -> bool {
440        *self == Trigsrcselect::Tcc0Mc5
441    }
442    #[doc = "DMA overflow/underflow/retrigger trigger"]
443    #[inline(always)]
444    pub fn is_tcc1_ovf(&self) -> bool {
445        *self == Trigsrcselect::Tcc1Ovf
446    }
447    #[doc = "Indexes of DMA Match/Compare triggers"]
448    #[inline(always)]
449    pub fn is_tcc1_mc_0(&self) -> bool {
450        *self == Trigsrcselect::Tcc1Mc0
451    }
452    #[doc = "Indexes of DMA Match/Compare triggers"]
453    #[inline(always)]
454    pub fn is_tcc1_mc_1(&self) -> bool {
455        *self == Trigsrcselect::Tcc1Mc1
456    }
457    #[doc = "Indexes of DMA Match/Compare triggers"]
458    #[inline(always)]
459    pub fn is_tcc1_mc_2(&self) -> bool {
460        *self == Trigsrcselect::Tcc1Mc2
461    }
462    #[doc = "Indexes of DMA Match/Compare triggers"]
463    #[inline(always)]
464    pub fn is_tcc1_mc_3(&self) -> bool {
465        *self == Trigsrcselect::Tcc1Mc3
466    }
467    #[doc = "DMA overflow/underflow/retrigger trigger"]
468    #[inline(always)]
469    pub fn is_tcc2_ovf(&self) -> bool {
470        *self == Trigsrcselect::Tcc2Ovf
471    }
472    #[doc = "Indexes of DMA Match/Compare triggers"]
473    #[inline(always)]
474    pub fn is_tcc2_mc_0(&self) -> bool {
475        *self == Trigsrcselect::Tcc2Mc0
476    }
477    #[doc = "Indexes of DMA Match/Compare triggers"]
478    #[inline(always)]
479    pub fn is_tcc2_mc_1(&self) -> bool {
480        *self == Trigsrcselect::Tcc2Mc1
481    }
482    #[doc = "Indexes of DMA Match/Compare triggers"]
483    #[inline(always)]
484    pub fn is_tcc2_mc_2(&self) -> bool {
485        *self == Trigsrcselect::Tcc2Mc2
486    }
487    #[doc = "DMA overflow/underflow/retrigger trigger"]
488    #[inline(always)]
489    pub fn is_tcc3_ovf(&self) -> bool {
490        *self == Trigsrcselect::Tcc3Ovf
491    }
492    #[doc = "Indexes of DMA Match/Compare triggers"]
493    #[inline(always)]
494    pub fn is_tcc3_mc_0(&self) -> bool {
495        *self == Trigsrcselect::Tcc3Mc0
496    }
497    #[doc = "Indexes of DMA Match/Compare triggers"]
498    #[inline(always)]
499    pub fn is_tcc3_mc_1(&self) -> bool {
500        *self == Trigsrcselect::Tcc3Mc1
501    }
502    #[doc = "DMA overflow/underflow/retrigger trigger"]
503    #[inline(always)]
504    pub fn is_tcc4_ovf(&self) -> bool {
505        *self == Trigsrcselect::Tcc4Ovf
506    }
507    #[doc = "Indexes of DMA Match/Compare triggers"]
508    #[inline(always)]
509    pub fn is_tcc4_mc_0(&self) -> bool {
510        *self == Trigsrcselect::Tcc4Mc0
511    }
512    #[doc = "Indexes of DMA Match/Compare triggers"]
513    #[inline(always)]
514    pub fn is_tcc4_mc_1(&self) -> bool {
515        *self == Trigsrcselect::Tcc4Mc1
516    }
517    #[doc = "Indexes of DMA Overflow trigger"]
518    #[inline(always)]
519    pub fn is_tc0_ovf(&self) -> bool {
520        *self == Trigsrcselect::Tc0Ovf
521    }
522    #[doc = "Indexes of DMA Match/Compare triggers"]
523    #[inline(always)]
524    pub fn is_tc0_mc_0(&self) -> bool {
525        *self == Trigsrcselect::Tc0Mc0
526    }
527    #[doc = "Indexes of DMA Match/Compare triggers"]
528    #[inline(always)]
529    pub fn is_tc0_mc_1(&self) -> bool {
530        *self == Trigsrcselect::Tc0Mc1
531    }
532    #[doc = "Indexes of DMA Overflow trigger"]
533    #[inline(always)]
534    pub fn is_tc1_ovf(&self) -> bool {
535        *self == Trigsrcselect::Tc1Ovf
536    }
537    #[doc = "Indexes of DMA Match/Compare triggers"]
538    #[inline(always)]
539    pub fn is_tc1_mc_0(&self) -> bool {
540        *self == Trigsrcselect::Tc1Mc0
541    }
542    #[doc = "Indexes of DMA Match/Compare triggers"]
543    #[inline(always)]
544    pub fn is_tc1_mc_1(&self) -> bool {
545        *self == Trigsrcselect::Tc1Mc1
546    }
547    #[doc = "Indexes of DMA Overflow trigger"]
548    #[inline(always)]
549    pub fn is_tc2_ovf(&self) -> bool {
550        *self == Trigsrcselect::Tc2Ovf
551    }
552    #[doc = "Indexes of DMA Match/Compare triggers"]
553    #[inline(always)]
554    pub fn is_tc2_mc_0(&self) -> bool {
555        *self == Trigsrcselect::Tc2Mc0
556    }
557    #[doc = "Indexes of DMA Match/Compare triggers"]
558    #[inline(always)]
559    pub fn is_tc2_mc_1(&self) -> bool {
560        *self == Trigsrcselect::Tc2Mc1
561    }
562    #[doc = "Indexes of DMA Overflow trigger"]
563    #[inline(always)]
564    pub fn is_tc3_ovf(&self) -> bool {
565        *self == Trigsrcselect::Tc3Ovf
566    }
567    #[doc = "Indexes of DMA Match/Compare triggers"]
568    #[inline(always)]
569    pub fn is_tc3_mc_0(&self) -> bool {
570        *self == Trigsrcselect::Tc3Mc0
571    }
572    #[doc = "Indexes of DMA Match/Compare triggers"]
573    #[inline(always)]
574    pub fn is_tc3_mc_1(&self) -> bool {
575        *self == Trigsrcselect::Tc3Mc1
576    }
577    #[doc = "Indexes of DMA Overflow trigger"]
578    #[inline(always)]
579    pub fn is_tc4_ovf(&self) -> bool {
580        *self == Trigsrcselect::Tc4Ovf
581    }
582    #[doc = "Indexes of DMA Match/Compare triggers"]
583    #[inline(always)]
584    pub fn is_tc4_mc_0(&self) -> bool {
585        *self == Trigsrcselect::Tc4Mc0
586    }
587    #[doc = "Indexes of DMA Match/Compare triggers"]
588    #[inline(always)]
589    pub fn is_tc4_mc_1(&self) -> bool {
590        *self == Trigsrcselect::Tc4Mc1
591    }
592    #[doc = "Indexes of DMA Overflow trigger"]
593    #[inline(always)]
594    pub fn is_tc5_ovf(&self) -> bool {
595        *self == Trigsrcselect::Tc5Ovf
596    }
597    #[doc = "Indexes of DMA Match/Compare triggers"]
598    #[inline(always)]
599    pub fn is_tc5_mc_0(&self) -> bool {
600        *self == Trigsrcselect::Tc5Mc0
601    }
602    #[doc = "Indexes of DMA Match/Compare triggers"]
603    #[inline(always)]
604    pub fn is_tc5_mc_1(&self) -> bool {
605        *self == Trigsrcselect::Tc5Mc1
606    }
607    #[doc = "Indexes of DMA Overflow trigger"]
608    #[inline(always)]
609    pub fn is_tc6_ovf(&self) -> bool {
610        *self == Trigsrcselect::Tc6Ovf
611    }
612    #[doc = "Indexes of DMA Match/Compare triggers"]
613    #[inline(always)]
614    pub fn is_tc6_mc_0(&self) -> bool {
615        *self == Trigsrcselect::Tc6Mc0
616    }
617    #[doc = "Indexes of DMA Match/Compare triggers"]
618    #[inline(always)]
619    pub fn is_tc6_mc_1(&self) -> bool {
620        *self == Trigsrcselect::Tc6Mc1
621    }
622    #[doc = "Indexes of DMA Overflow trigger"]
623    #[inline(always)]
624    pub fn is_tc7_ovf(&self) -> bool {
625        *self == Trigsrcselect::Tc7Ovf
626    }
627    #[doc = "Indexes of DMA Match/Compare triggers"]
628    #[inline(always)]
629    pub fn is_tc7_mc_0(&self) -> bool {
630        *self == Trigsrcselect::Tc7Mc0
631    }
632    #[doc = "Indexes of DMA Match/Compare triggers"]
633    #[inline(always)]
634    pub fn is_tc7_mc_1(&self) -> bool {
635        *self == Trigsrcselect::Tc7Mc1
636    }
637    #[doc = "index of DMA RESRDY trigger"]
638    #[inline(always)]
639    pub fn is_adc0_resrdy(&self) -> bool {
640        *self == Trigsrcselect::Adc0Resrdy
641    }
642    #[doc = "Index of DMA SEQ trigger"]
643    #[inline(always)]
644    pub fn is_adc0_seq(&self) -> bool {
645        *self == Trigsrcselect::Adc0Seq
646    }
647    #[doc = "Index of DMA RESRDY trigger"]
648    #[inline(always)]
649    pub fn is_adc1_resrdy(&self) -> bool {
650        *self == Trigsrcselect::Adc1Resrdy
651    }
652    #[doc = "Index of DMA SEQ trigger"]
653    #[inline(always)]
654    pub fn is_adc1_seq(&self) -> bool {
655        *self == Trigsrcselect::Adc1Seq
656    }
657    #[doc = "DMA DAC Empty Req"]
658    #[inline(always)]
659    pub fn is_dac_empty_0(&self) -> bool {
660        *self == Trigsrcselect::DacEmpty0
661    }
662    #[doc = "DMA DAC Empty Req"]
663    #[inline(always)]
664    pub fn is_dac_empty_1(&self) -> bool {
665        *self == Trigsrcselect::DacEmpty1
666    }
667    #[doc = "DMA DAC Result Ready Req"]
668    #[inline(always)]
669    pub fn is_dac_resrdy_0(&self) -> bool {
670        *self == Trigsrcselect::DacResrdy0
671    }
672    #[doc = "DMA DAC Result Ready Req"]
673    #[inline(always)]
674    pub fn is_dac_resrdy_1(&self) -> bool {
675        *self == Trigsrcselect::DacResrdy1
676    }
677    #[doc = "Indexes of DMA RX triggers"]
678    #[inline(always)]
679    pub fn is_i2s_rx_0(&self) -> bool {
680        *self == Trigsrcselect::I2sRx0
681    }
682    #[doc = "Indexes of DMA RX triggers"]
683    #[inline(always)]
684    pub fn is_i2s_rx_1(&self) -> bool {
685        *self == Trigsrcselect::I2sRx1
686    }
687    #[doc = "Indexes of DMA TX triggers"]
688    #[inline(always)]
689    pub fn is_i2s_tx_0(&self) -> bool {
690        *self == Trigsrcselect::I2sTx0
691    }
692    #[doc = "Indexes of DMA TX triggers"]
693    #[inline(always)]
694    pub fn is_i2s_tx_1(&self) -> bool {
695        *self == Trigsrcselect::I2sTx1
696    }
697    #[doc = "Indexes of PCC RX trigger"]
698    #[inline(always)]
699    pub fn is_pcc_rx(&self) -> bool {
700        *self == Trigsrcselect::PccRx
701    }
702    #[doc = "DMA DATA Write trigger"]
703    #[inline(always)]
704    pub fn is_aes_wr(&self) -> bool {
705        *self == Trigsrcselect::AesWr
706    }
707    #[doc = "DMA DATA Read trigger"]
708    #[inline(always)]
709    pub fn is_aes_rd(&self) -> bool {
710        *self == Trigsrcselect::AesRd
711    }
712    #[doc = "Indexes of QSPI RX trigger"]
713    #[inline(always)]
714    pub fn is_qspi_rx(&self) -> bool {
715        *self == Trigsrcselect::QspiRx
716    }
717    #[doc = "Indexes of QSPI TX trigger"]
718    #[inline(always)]
719    pub fn is_qspi_tx(&self) -> bool {
720        *self == Trigsrcselect::QspiTx
721    }
722}
723#[doc = "Field `TRIGSRC` writer - Trigger Source"]
724pub type TrigsrcW<'a, REG> = crate::FieldWriter<'a, REG, 7, Trigsrcselect>;
725impl<'a, REG> TrigsrcW<'a, REG>
726where
727    REG: crate::Writable + crate::RegisterSpec,
728    REG::Ux: From<u8>,
729{
730    #[doc = "Only software/event triggers"]
731    #[inline(always)]
732    pub fn disable(self) -> &'a mut crate::W<REG> {
733        self.variant(Trigsrcselect::Disable)
734    }
735    #[doc = "DMA RTC timestamp trigger"]
736    #[inline(always)]
737    pub fn rtc_timestamp(self) -> &'a mut crate::W<REG> {
738        self.variant(Trigsrcselect::RtcTimestamp)
739    }
740    #[doc = "DMAC ID for DCC0 register"]
741    #[inline(always)]
742    pub fn dsu_dcc0(self) -> &'a mut crate::W<REG> {
743        self.variant(Trigsrcselect::DsuDcc0)
744    }
745    #[doc = "DMAC ID for DCC1 register"]
746    #[inline(always)]
747    pub fn dsu_dcc1(self) -> &'a mut crate::W<REG> {
748        self.variant(Trigsrcselect::DsuDcc1)
749    }
750    #[doc = "Index of DMA RX trigger"]
751    #[inline(always)]
752    pub fn sercom0_rx(self) -> &'a mut crate::W<REG> {
753        self.variant(Trigsrcselect::Sercom0Rx)
754    }
755    #[doc = "Index of DMA TX trigger"]
756    #[inline(always)]
757    pub fn sercom0_tx(self) -> &'a mut crate::W<REG> {
758        self.variant(Trigsrcselect::Sercom0Tx)
759    }
760    #[doc = "Index of DMA RX trigger"]
761    #[inline(always)]
762    pub fn sercom1_rx(self) -> &'a mut crate::W<REG> {
763        self.variant(Trigsrcselect::Sercom1Rx)
764    }
765    #[doc = "Index of DMA TX trigger"]
766    #[inline(always)]
767    pub fn sercom1_tx(self) -> &'a mut crate::W<REG> {
768        self.variant(Trigsrcselect::Sercom1Tx)
769    }
770    #[doc = "Index of DMA RX trigger"]
771    #[inline(always)]
772    pub fn sercom2_rx(self) -> &'a mut crate::W<REG> {
773        self.variant(Trigsrcselect::Sercom2Rx)
774    }
775    #[doc = "Index of DMA TX trigger"]
776    #[inline(always)]
777    pub fn sercom2_tx(self) -> &'a mut crate::W<REG> {
778        self.variant(Trigsrcselect::Sercom2Tx)
779    }
780    #[doc = "Index of DMA RX trigger"]
781    #[inline(always)]
782    pub fn sercom3_rx(self) -> &'a mut crate::W<REG> {
783        self.variant(Trigsrcselect::Sercom3Rx)
784    }
785    #[doc = "Index of DMA TX trigger"]
786    #[inline(always)]
787    pub fn sercom3_tx(self) -> &'a mut crate::W<REG> {
788        self.variant(Trigsrcselect::Sercom3Tx)
789    }
790    #[doc = "Index of DMA RX trigger"]
791    #[inline(always)]
792    pub fn sercom4_rx(self) -> &'a mut crate::W<REG> {
793        self.variant(Trigsrcselect::Sercom4Rx)
794    }
795    #[doc = "Index of DMA TX trigger"]
796    #[inline(always)]
797    pub fn sercom4_tx(self) -> &'a mut crate::W<REG> {
798        self.variant(Trigsrcselect::Sercom4Tx)
799    }
800    #[doc = "Index of DMA RX trigger"]
801    #[inline(always)]
802    pub fn sercom5_rx(self) -> &'a mut crate::W<REG> {
803        self.variant(Trigsrcselect::Sercom5Rx)
804    }
805    #[doc = "Index of DMA TX trigger"]
806    #[inline(always)]
807    pub fn sercom5_tx(self) -> &'a mut crate::W<REG> {
808        self.variant(Trigsrcselect::Sercom5Tx)
809    }
810    #[doc = "Index of DMA RX trigger"]
811    #[inline(always)]
812    pub fn sercom6_rx(self) -> &'a mut crate::W<REG> {
813        self.variant(Trigsrcselect::Sercom6Rx)
814    }
815    #[doc = "Index of DMA TX trigger"]
816    #[inline(always)]
817    pub fn sercom6_tx(self) -> &'a mut crate::W<REG> {
818        self.variant(Trigsrcselect::Sercom6Tx)
819    }
820    #[doc = "Index of DMA RX trigger"]
821    #[inline(always)]
822    pub fn sercom7_rx(self) -> &'a mut crate::W<REG> {
823        self.variant(Trigsrcselect::Sercom7Rx)
824    }
825    #[doc = "Index of DMA TX trigger"]
826    #[inline(always)]
827    pub fn sercom7_tx(self) -> &'a mut crate::W<REG> {
828        self.variant(Trigsrcselect::Sercom7Tx)
829    }
830    #[doc = "DMA CAN Debug Req"]
831    #[inline(always)]
832    pub fn can0_debug(self) -> &'a mut crate::W<REG> {
833        self.variant(Trigsrcselect::Can0Debug)
834    }
835    #[doc = "DMA CAN Debug Req"]
836    #[inline(always)]
837    pub fn can1_debug(self) -> &'a mut crate::W<REG> {
838        self.variant(Trigsrcselect::Can1Debug)
839    }
840    #[doc = "DMA overflow/underflow/retrigger trigger"]
841    #[inline(always)]
842    pub fn tcc0_ovf(self) -> &'a mut crate::W<REG> {
843        self.variant(Trigsrcselect::Tcc0Ovf)
844    }
845    #[doc = "Indexes of DMA Match/Compare triggers"]
846    #[inline(always)]
847    pub fn tcc0_mc_0(self) -> &'a mut crate::W<REG> {
848        self.variant(Trigsrcselect::Tcc0Mc0)
849    }
850    #[doc = "Indexes of DMA Match/Compare triggers"]
851    #[inline(always)]
852    pub fn tcc0_mc_1(self) -> &'a mut crate::W<REG> {
853        self.variant(Trigsrcselect::Tcc0Mc1)
854    }
855    #[doc = "Indexes of DMA Match/Compare triggers"]
856    #[inline(always)]
857    pub fn tcc0_mc_2(self) -> &'a mut crate::W<REG> {
858        self.variant(Trigsrcselect::Tcc0Mc2)
859    }
860    #[doc = "Indexes of DMA Match/Compare triggers"]
861    #[inline(always)]
862    pub fn tcc0_mc_3(self) -> &'a mut crate::W<REG> {
863        self.variant(Trigsrcselect::Tcc0Mc3)
864    }
865    #[doc = "Indexes of DMA Match/Compare triggers"]
866    #[inline(always)]
867    pub fn tcc0_mc_4(self) -> &'a mut crate::W<REG> {
868        self.variant(Trigsrcselect::Tcc0Mc4)
869    }
870    #[doc = "Indexes of DMA Match/Compare triggers"]
871    #[inline(always)]
872    pub fn tcc0_mc_5(self) -> &'a mut crate::W<REG> {
873        self.variant(Trigsrcselect::Tcc0Mc5)
874    }
875    #[doc = "DMA overflow/underflow/retrigger trigger"]
876    #[inline(always)]
877    pub fn tcc1_ovf(self) -> &'a mut crate::W<REG> {
878        self.variant(Trigsrcselect::Tcc1Ovf)
879    }
880    #[doc = "Indexes of DMA Match/Compare triggers"]
881    #[inline(always)]
882    pub fn tcc1_mc_0(self) -> &'a mut crate::W<REG> {
883        self.variant(Trigsrcselect::Tcc1Mc0)
884    }
885    #[doc = "Indexes of DMA Match/Compare triggers"]
886    #[inline(always)]
887    pub fn tcc1_mc_1(self) -> &'a mut crate::W<REG> {
888        self.variant(Trigsrcselect::Tcc1Mc1)
889    }
890    #[doc = "Indexes of DMA Match/Compare triggers"]
891    #[inline(always)]
892    pub fn tcc1_mc_2(self) -> &'a mut crate::W<REG> {
893        self.variant(Trigsrcselect::Tcc1Mc2)
894    }
895    #[doc = "Indexes of DMA Match/Compare triggers"]
896    #[inline(always)]
897    pub fn tcc1_mc_3(self) -> &'a mut crate::W<REG> {
898        self.variant(Trigsrcselect::Tcc1Mc3)
899    }
900    #[doc = "DMA overflow/underflow/retrigger trigger"]
901    #[inline(always)]
902    pub fn tcc2_ovf(self) -> &'a mut crate::W<REG> {
903        self.variant(Trigsrcselect::Tcc2Ovf)
904    }
905    #[doc = "Indexes of DMA Match/Compare triggers"]
906    #[inline(always)]
907    pub fn tcc2_mc_0(self) -> &'a mut crate::W<REG> {
908        self.variant(Trigsrcselect::Tcc2Mc0)
909    }
910    #[doc = "Indexes of DMA Match/Compare triggers"]
911    #[inline(always)]
912    pub fn tcc2_mc_1(self) -> &'a mut crate::W<REG> {
913        self.variant(Trigsrcselect::Tcc2Mc1)
914    }
915    #[doc = "Indexes of DMA Match/Compare triggers"]
916    #[inline(always)]
917    pub fn tcc2_mc_2(self) -> &'a mut crate::W<REG> {
918        self.variant(Trigsrcselect::Tcc2Mc2)
919    }
920    #[doc = "DMA overflow/underflow/retrigger trigger"]
921    #[inline(always)]
922    pub fn tcc3_ovf(self) -> &'a mut crate::W<REG> {
923        self.variant(Trigsrcselect::Tcc3Ovf)
924    }
925    #[doc = "Indexes of DMA Match/Compare triggers"]
926    #[inline(always)]
927    pub fn tcc3_mc_0(self) -> &'a mut crate::W<REG> {
928        self.variant(Trigsrcselect::Tcc3Mc0)
929    }
930    #[doc = "Indexes of DMA Match/Compare triggers"]
931    #[inline(always)]
932    pub fn tcc3_mc_1(self) -> &'a mut crate::W<REG> {
933        self.variant(Trigsrcselect::Tcc3Mc1)
934    }
935    #[doc = "DMA overflow/underflow/retrigger trigger"]
936    #[inline(always)]
937    pub fn tcc4_ovf(self) -> &'a mut crate::W<REG> {
938        self.variant(Trigsrcselect::Tcc4Ovf)
939    }
940    #[doc = "Indexes of DMA Match/Compare triggers"]
941    #[inline(always)]
942    pub fn tcc4_mc_0(self) -> &'a mut crate::W<REG> {
943        self.variant(Trigsrcselect::Tcc4Mc0)
944    }
945    #[doc = "Indexes of DMA Match/Compare triggers"]
946    #[inline(always)]
947    pub fn tcc4_mc_1(self) -> &'a mut crate::W<REG> {
948        self.variant(Trigsrcselect::Tcc4Mc1)
949    }
950    #[doc = "Indexes of DMA Overflow trigger"]
951    #[inline(always)]
952    pub fn tc0_ovf(self) -> &'a mut crate::W<REG> {
953        self.variant(Trigsrcselect::Tc0Ovf)
954    }
955    #[doc = "Indexes of DMA Match/Compare triggers"]
956    #[inline(always)]
957    pub fn tc0_mc_0(self) -> &'a mut crate::W<REG> {
958        self.variant(Trigsrcselect::Tc0Mc0)
959    }
960    #[doc = "Indexes of DMA Match/Compare triggers"]
961    #[inline(always)]
962    pub fn tc0_mc_1(self) -> &'a mut crate::W<REG> {
963        self.variant(Trigsrcselect::Tc0Mc1)
964    }
965    #[doc = "Indexes of DMA Overflow trigger"]
966    #[inline(always)]
967    pub fn tc1_ovf(self) -> &'a mut crate::W<REG> {
968        self.variant(Trigsrcselect::Tc1Ovf)
969    }
970    #[doc = "Indexes of DMA Match/Compare triggers"]
971    #[inline(always)]
972    pub fn tc1_mc_0(self) -> &'a mut crate::W<REG> {
973        self.variant(Trigsrcselect::Tc1Mc0)
974    }
975    #[doc = "Indexes of DMA Match/Compare triggers"]
976    #[inline(always)]
977    pub fn tc1_mc_1(self) -> &'a mut crate::W<REG> {
978        self.variant(Trigsrcselect::Tc1Mc1)
979    }
980    #[doc = "Indexes of DMA Overflow trigger"]
981    #[inline(always)]
982    pub fn tc2_ovf(self) -> &'a mut crate::W<REG> {
983        self.variant(Trigsrcselect::Tc2Ovf)
984    }
985    #[doc = "Indexes of DMA Match/Compare triggers"]
986    #[inline(always)]
987    pub fn tc2_mc_0(self) -> &'a mut crate::W<REG> {
988        self.variant(Trigsrcselect::Tc2Mc0)
989    }
990    #[doc = "Indexes of DMA Match/Compare triggers"]
991    #[inline(always)]
992    pub fn tc2_mc_1(self) -> &'a mut crate::W<REG> {
993        self.variant(Trigsrcselect::Tc2Mc1)
994    }
995    #[doc = "Indexes of DMA Overflow trigger"]
996    #[inline(always)]
997    pub fn tc3_ovf(self) -> &'a mut crate::W<REG> {
998        self.variant(Trigsrcselect::Tc3Ovf)
999    }
1000    #[doc = "Indexes of DMA Match/Compare triggers"]
1001    #[inline(always)]
1002    pub fn tc3_mc_0(self) -> &'a mut crate::W<REG> {
1003        self.variant(Trigsrcselect::Tc3Mc0)
1004    }
1005    #[doc = "Indexes of DMA Match/Compare triggers"]
1006    #[inline(always)]
1007    pub fn tc3_mc_1(self) -> &'a mut crate::W<REG> {
1008        self.variant(Trigsrcselect::Tc3Mc1)
1009    }
1010    #[doc = "Indexes of DMA Overflow trigger"]
1011    #[inline(always)]
1012    pub fn tc4_ovf(self) -> &'a mut crate::W<REG> {
1013        self.variant(Trigsrcselect::Tc4Ovf)
1014    }
1015    #[doc = "Indexes of DMA Match/Compare triggers"]
1016    #[inline(always)]
1017    pub fn tc4_mc_0(self) -> &'a mut crate::W<REG> {
1018        self.variant(Trigsrcselect::Tc4Mc0)
1019    }
1020    #[doc = "Indexes of DMA Match/Compare triggers"]
1021    #[inline(always)]
1022    pub fn tc4_mc_1(self) -> &'a mut crate::W<REG> {
1023        self.variant(Trigsrcselect::Tc4Mc1)
1024    }
1025    #[doc = "Indexes of DMA Overflow trigger"]
1026    #[inline(always)]
1027    pub fn tc5_ovf(self) -> &'a mut crate::W<REG> {
1028        self.variant(Trigsrcselect::Tc5Ovf)
1029    }
1030    #[doc = "Indexes of DMA Match/Compare triggers"]
1031    #[inline(always)]
1032    pub fn tc5_mc_0(self) -> &'a mut crate::W<REG> {
1033        self.variant(Trigsrcselect::Tc5Mc0)
1034    }
1035    #[doc = "Indexes of DMA Match/Compare triggers"]
1036    #[inline(always)]
1037    pub fn tc5_mc_1(self) -> &'a mut crate::W<REG> {
1038        self.variant(Trigsrcselect::Tc5Mc1)
1039    }
1040    #[doc = "Indexes of DMA Overflow trigger"]
1041    #[inline(always)]
1042    pub fn tc6_ovf(self) -> &'a mut crate::W<REG> {
1043        self.variant(Trigsrcselect::Tc6Ovf)
1044    }
1045    #[doc = "Indexes of DMA Match/Compare triggers"]
1046    #[inline(always)]
1047    pub fn tc6_mc_0(self) -> &'a mut crate::W<REG> {
1048        self.variant(Trigsrcselect::Tc6Mc0)
1049    }
1050    #[doc = "Indexes of DMA Match/Compare triggers"]
1051    #[inline(always)]
1052    pub fn tc6_mc_1(self) -> &'a mut crate::W<REG> {
1053        self.variant(Trigsrcselect::Tc6Mc1)
1054    }
1055    #[doc = "Indexes of DMA Overflow trigger"]
1056    #[inline(always)]
1057    pub fn tc7_ovf(self) -> &'a mut crate::W<REG> {
1058        self.variant(Trigsrcselect::Tc7Ovf)
1059    }
1060    #[doc = "Indexes of DMA Match/Compare triggers"]
1061    #[inline(always)]
1062    pub fn tc7_mc_0(self) -> &'a mut crate::W<REG> {
1063        self.variant(Trigsrcselect::Tc7Mc0)
1064    }
1065    #[doc = "Indexes of DMA Match/Compare triggers"]
1066    #[inline(always)]
1067    pub fn tc7_mc_1(self) -> &'a mut crate::W<REG> {
1068        self.variant(Trigsrcselect::Tc7Mc1)
1069    }
1070    #[doc = "index of DMA RESRDY trigger"]
1071    #[inline(always)]
1072    pub fn adc0_resrdy(self) -> &'a mut crate::W<REG> {
1073        self.variant(Trigsrcselect::Adc0Resrdy)
1074    }
1075    #[doc = "Index of DMA SEQ trigger"]
1076    #[inline(always)]
1077    pub fn adc0_seq(self) -> &'a mut crate::W<REG> {
1078        self.variant(Trigsrcselect::Adc0Seq)
1079    }
1080    #[doc = "Index of DMA RESRDY trigger"]
1081    #[inline(always)]
1082    pub fn adc1_resrdy(self) -> &'a mut crate::W<REG> {
1083        self.variant(Trigsrcselect::Adc1Resrdy)
1084    }
1085    #[doc = "Index of DMA SEQ trigger"]
1086    #[inline(always)]
1087    pub fn adc1_seq(self) -> &'a mut crate::W<REG> {
1088        self.variant(Trigsrcselect::Adc1Seq)
1089    }
1090    #[doc = "DMA DAC Empty Req"]
1091    #[inline(always)]
1092    pub fn dac_empty_0(self) -> &'a mut crate::W<REG> {
1093        self.variant(Trigsrcselect::DacEmpty0)
1094    }
1095    #[doc = "DMA DAC Empty Req"]
1096    #[inline(always)]
1097    pub fn dac_empty_1(self) -> &'a mut crate::W<REG> {
1098        self.variant(Trigsrcselect::DacEmpty1)
1099    }
1100    #[doc = "DMA DAC Result Ready Req"]
1101    #[inline(always)]
1102    pub fn dac_resrdy_0(self) -> &'a mut crate::W<REG> {
1103        self.variant(Trigsrcselect::DacResrdy0)
1104    }
1105    #[doc = "DMA DAC Result Ready Req"]
1106    #[inline(always)]
1107    pub fn dac_resrdy_1(self) -> &'a mut crate::W<REG> {
1108        self.variant(Trigsrcselect::DacResrdy1)
1109    }
1110    #[doc = "Indexes of DMA RX triggers"]
1111    #[inline(always)]
1112    pub fn i2s_rx_0(self) -> &'a mut crate::W<REG> {
1113        self.variant(Trigsrcselect::I2sRx0)
1114    }
1115    #[doc = "Indexes of DMA RX triggers"]
1116    #[inline(always)]
1117    pub fn i2s_rx_1(self) -> &'a mut crate::W<REG> {
1118        self.variant(Trigsrcselect::I2sRx1)
1119    }
1120    #[doc = "Indexes of DMA TX triggers"]
1121    #[inline(always)]
1122    pub fn i2s_tx_0(self) -> &'a mut crate::W<REG> {
1123        self.variant(Trigsrcselect::I2sTx0)
1124    }
1125    #[doc = "Indexes of DMA TX triggers"]
1126    #[inline(always)]
1127    pub fn i2s_tx_1(self) -> &'a mut crate::W<REG> {
1128        self.variant(Trigsrcselect::I2sTx1)
1129    }
1130    #[doc = "Indexes of PCC RX trigger"]
1131    #[inline(always)]
1132    pub fn pcc_rx(self) -> &'a mut crate::W<REG> {
1133        self.variant(Trigsrcselect::PccRx)
1134    }
1135    #[doc = "DMA DATA Write trigger"]
1136    #[inline(always)]
1137    pub fn aes_wr(self) -> &'a mut crate::W<REG> {
1138        self.variant(Trigsrcselect::AesWr)
1139    }
1140    #[doc = "DMA DATA Read trigger"]
1141    #[inline(always)]
1142    pub fn aes_rd(self) -> &'a mut crate::W<REG> {
1143        self.variant(Trigsrcselect::AesRd)
1144    }
1145    #[doc = "Indexes of QSPI RX trigger"]
1146    #[inline(always)]
1147    pub fn qspi_rx(self) -> &'a mut crate::W<REG> {
1148        self.variant(Trigsrcselect::QspiRx)
1149    }
1150    #[doc = "Indexes of QSPI TX trigger"]
1151    #[inline(always)]
1152    pub fn qspi_tx(self) -> &'a mut crate::W<REG> {
1153        self.variant(Trigsrcselect::QspiTx)
1154    }
1155}
1156#[doc = "Trigger Action\n\nValue on reset: 0"]
1157#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1158#[repr(u8)]
1159pub enum Trigactselect {
1160    #[doc = "0: One trigger required for each block transfer"]
1161    Block = 0,
1162    #[doc = "2: One trigger required for each burst transfer"]
1163    Burst = 2,
1164    #[doc = "3: One trigger required for each transaction"]
1165    Transaction = 3,
1166}
1167impl From<Trigactselect> for u8 {
1168    #[inline(always)]
1169    fn from(variant: Trigactselect) -> Self {
1170        variant as _
1171    }
1172}
1173impl crate::FieldSpec for Trigactselect {
1174    type Ux = u8;
1175}
1176impl crate::IsEnum for Trigactselect {}
1177#[doc = "Field `TRIGACT` reader - Trigger Action"]
1178pub type TrigactR = crate::FieldReader<Trigactselect>;
1179impl TrigactR {
1180    #[doc = "Get enumerated values variant"]
1181    #[inline(always)]
1182    pub const fn variant(&self) -> Option<Trigactselect> {
1183        match self.bits {
1184            0 => Some(Trigactselect::Block),
1185            2 => Some(Trigactselect::Burst),
1186            3 => Some(Trigactselect::Transaction),
1187            _ => None,
1188        }
1189    }
1190    #[doc = "One trigger required for each block transfer"]
1191    #[inline(always)]
1192    pub fn is_block(&self) -> bool {
1193        *self == Trigactselect::Block
1194    }
1195    #[doc = "One trigger required for each burst transfer"]
1196    #[inline(always)]
1197    pub fn is_burst(&self) -> bool {
1198        *self == Trigactselect::Burst
1199    }
1200    #[doc = "One trigger required for each transaction"]
1201    #[inline(always)]
1202    pub fn is_transaction(&self) -> bool {
1203        *self == Trigactselect::Transaction
1204    }
1205}
1206#[doc = "Field `TRIGACT` writer - Trigger Action"]
1207pub type TrigactW<'a, REG> = crate::FieldWriter<'a, REG, 2, Trigactselect>;
1208impl<'a, REG> TrigactW<'a, REG>
1209where
1210    REG: crate::Writable + crate::RegisterSpec,
1211    REG::Ux: From<u8>,
1212{
1213    #[doc = "One trigger required for each block transfer"]
1214    #[inline(always)]
1215    pub fn block(self) -> &'a mut crate::W<REG> {
1216        self.variant(Trigactselect::Block)
1217    }
1218    #[doc = "One trigger required for each burst transfer"]
1219    #[inline(always)]
1220    pub fn burst(self) -> &'a mut crate::W<REG> {
1221        self.variant(Trigactselect::Burst)
1222    }
1223    #[doc = "One trigger required for each transaction"]
1224    #[inline(always)]
1225    pub fn transaction(self) -> &'a mut crate::W<REG> {
1226        self.variant(Trigactselect::Transaction)
1227    }
1228}
1229#[doc = "Burst Length\n\nValue on reset: 0"]
1230#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1231#[repr(u8)]
1232pub enum Burstlenselect {
1233    #[doc = "0: Single-beat burst length"]
1234    Single = 0,
1235    #[doc = "1: 2-beats burst length"]
1236    _2beat = 1,
1237    #[doc = "2: 3-beats burst length"]
1238    _3beat = 2,
1239    #[doc = "3: 4-beats burst length"]
1240    _4beat = 3,
1241    #[doc = "4: 5-beats burst length"]
1242    _5beat = 4,
1243    #[doc = "5: 6-beats burst length"]
1244    _6beat = 5,
1245    #[doc = "6: 7-beats burst length"]
1246    _7beat = 6,
1247    #[doc = "7: 8-beats burst length"]
1248    _8beat = 7,
1249    #[doc = "8: 9-beats burst length"]
1250    _9beat = 8,
1251    #[doc = "9: 10-beats burst length"]
1252    _10beat = 9,
1253    #[doc = "10: 11-beats burst length"]
1254    _11beat = 10,
1255    #[doc = "11: 12-beats burst length"]
1256    _12beat = 11,
1257    #[doc = "12: 13-beats burst length"]
1258    _13beat = 12,
1259    #[doc = "13: 14-beats burst length"]
1260    _14beat = 13,
1261    #[doc = "14: 15-beats burst length"]
1262    _15beat = 14,
1263    #[doc = "15: 16-beats burst length"]
1264    _16beat = 15,
1265}
1266impl From<Burstlenselect> for u8 {
1267    #[inline(always)]
1268    fn from(variant: Burstlenselect) -> Self {
1269        variant as _
1270    }
1271}
1272impl crate::FieldSpec for Burstlenselect {
1273    type Ux = u8;
1274}
1275impl crate::IsEnum for Burstlenselect {}
1276#[doc = "Field `BURSTLEN` reader - Burst Length"]
1277pub type BurstlenR = crate::FieldReader<Burstlenselect>;
1278impl BurstlenR {
1279    #[doc = "Get enumerated values variant"]
1280    #[inline(always)]
1281    pub const fn variant(&self) -> Burstlenselect {
1282        match self.bits {
1283            0 => Burstlenselect::Single,
1284            1 => Burstlenselect::_2beat,
1285            2 => Burstlenselect::_3beat,
1286            3 => Burstlenselect::_4beat,
1287            4 => Burstlenselect::_5beat,
1288            5 => Burstlenselect::_6beat,
1289            6 => Burstlenselect::_7beat,
1290            7 => Burstlenselect::_8beat,
1291            8 => Burstlenselect::_9beat,
1292            9 => Burstlenselect::_10beat,
1293            10 => Burstlenselect::_11beat,
1294            11 => Burstlenselect::_12beat,
1295            12 => Burstlenselect::_13beat,
1296            13 => Burstlenselect::_14beat,
1297            14 => Burstlenselect::_15beat,
1298            15 => Burstlenselect::_16beat,
1299            _ => unreachable!(),
1300        }
1301    }
1302    #[doc = "Single-beat burst length"]
1303    #[inline(always)]
1304    pub fn is_single(&self) -> bool {
1305        *self == Burstlenselect::Single
1306    }
1307    #[doc = "2-beats burst length"]
1308    #[inline(always)]
1309    pub fn is_2beat(&self) -> bool {
1310        *self == Burstlenselect::_2beat
1311    }
1312    #[doc = "3-beats burst length"]
1313    #[inline(always)]
1314    pub fn is_3beat(&self) -> bool {
1315        *self == Burstlenselect::_3beat
1316    }
1317    #[doc = "4-beats burst length"]
1318    #[inline(always)]
1319    pub fn is_4beat(&self) -> bool {
1320        *self == Burstlenselect::_4beat
1321    }
1322    #[doc = "5-beats burst length"]
1323    #[inline(always)]
1324    pub fn is_5beat(&self) -> bool {
1325        *self == Burstlenselect::_5beat
1326    }
1327    #[doc = "6-beats burst length"]
1328    #[inline(always)]
1329    pub fn is_6beat(&self) -> bool {
1330        *self == Burstlenselect::_6beat
1331    }
1332    #[doc = "7-beats burst length"]
1333    #[inline(always)]
1334    pub fn is_7beat(&self) -> bool {
1335        *self == Burstlenselect::_7beat
1336    }
1337    #[doc = "8-beats burst length"]
1338    #[inline(always)]
1339    pub fn is_8beat(&self) -> bool {
1340        *self == Burstlenselect::_8beat
1341    }
1342    #[doc = "9-beats burst length"]
1343    #[inline(always)]
1344    pub fn is_9beat(&self) -> bool {
1345        *self == Burstlenselect::_9beat
1346    }
1347    #[doc = "10-beats burst length"]
1348    #[inline(always)]
1349    pub fn is_10beat(&self) -> bool {
1350        *self == Burstlenselect::_10beat
1351    }
1352    #[doc = "11-beats burst length"]
1353    #[inline(always)]
1354    pub fn is_11beat(&self) -> bool {
1355        *self == Burstlenselect::_11beat
1356    }
1357    #[doc = "12-beats burst length"]
1358    #[inline(always)]
1359    pub fn is_12beat(&self) -> bool {
1360        *self == Burstlenselect::_12beat
1361    }
1362    #[doc = "13-beats burst length"]
1363    #[inline(always)]
1364    pub fn is_13beat(&self) -> bool {
1365        *self == Burstlenselect::_13beat
1366    }
1367    #[doc = "14-beats burst length"]
1368    #[inline(always)]
1369    pub fn is_14beat(&self) -> bool {
1370        *self == Burstlenselect::_14beat
1371    }
1372    #[doc = "15-beats burst length"]
1373    #[inline(always)]
1374    pub fn is_15beat(&self) -> bool {
1375        *self == Burstlenselect::_15beat
1376    }
1377    #[doc = "16-beats burst length"]
1378    #[inline(always)]
1379    pub fn is_16beat(&self) -> bool {
1380        *self == Burstlenselect::_16beat
1381    }
1382}
1383#[doc = "Field `BURSTLEN` writer - Burst Length"]
1384pub type BurstlenW<'a, REG> = crate::FieldWriter<'a, REG, 4, Burstlenselect, crate::Safe>;
1385impl<'a, REG> BurstlenW<'a, REG>
1386where
1387    REG: crate::Writable + crate::RegisterSpec,
1388    REG::Ux: From<u8>,
1389{
1390    #[doc = "Single-beat burst length"]
1391    #[inline(always)]
1392    pub fn single(self) -> &'a mut crate::W<REG> {
1393        self.variant(Burstlenselect::Single)
1394    }
1395    #[doc = "2-beats burst length"]
1396    #[inline(always)]
1397    pub fn _2beat(self) -> &'a mut crate::W<REG> {
1398        self.variant(Burstlenselect::_2beat)
1399    }
1400    #[doc = "3-beats burst length"]
1401    #[inline(always)]
1402    pub fn _3beat(self) -> &'a mut crate::W<REG> {
1403        self.variant(Burstlenselect::_3beat)
1404    }
1405    #[doc = "4-beats burst length"]
1406    #[inline(always)]
1407    pub fn _4beat(self) -> &'a mut crate::W<REG> {
1408        self.variant(Burstlenselect::_4beat)
1409    }
1410    #[doc = "5-beats burst length"]
1411    #[inline(always)]
1412    pub fn _5beat(self) -> &'a mut crate::W<REG> {
1413        self.variant(Burstlenselect::_5beat)
1414    }
1415    #[doc = "6-beats burst length"]
1416    #[inline(always)]
1417    pub fn _6beat(self) -> &'a mut crate::W<REG> {
1418        self.variant(Burstlenselect::_6beat)
1419    }
1420    #[doc = "7-beats burst length"]
1421    #[inline(always)]
1422    pub fn _7beat(self) -> &'a mut crate::W<REG> {
1423        self.variant(Burstlenselect::_7beat)
1424    }
1425    #[doc = "8-beats burst length"]
1426    #[inline(always)]
1427    pub fn _8beat(self) -> &'a mut crate::W<REG> {
1428        self.variant(Burstlenselect::_8beat)
1429    }
1430    #[doc = "9-beats burst length"]
1431    #[inline(always)]
1432    pub fn _9beat(self) -> &'a mut crate::W<REG> {
1433        self.variant(Burstlenselect::_9beat)
1434    }
1435    #[doc = "10-beats burst length"]
1436    #[inline(always)]
1437    pub fn _10beat(self) -> &'a mut crate::W<REG> {
1438        self.variant(Burstlenselect::_10beat)
1439    }
1440    #[doc = "11-beats burst length"]
1441    #[inline(always)]
1442    pub fn _11beat(self) -> &'a mut crate::W<REG> {
1443        self.variant(Burstlenselect::_11beat)
1444    }
1445    #[doc = "12-beats burst length"]
1446    #[inline(always)]
1447    pub fn _12beat(self) -> &'a mut crate::W<REG> {
1448        self.variant(Burstlenselect::_12beat)
1449    }
1450    #[doc = "13-beats burst length"]
1451    #[inline(always)]
1452    pub fn _13beat(self) -> &'a mut crate::W<REG> {
1453        self.variant(Burstlenselect::_13beat)
1454    }
1455    #[doc = "14-beats burst length"]
1456    #[inline(always)]
1457    pub fn _14beat(self) -> &'a mut crate::W<REG> {
1458        self.variant(Burstlenselect::_14beat)
1459    }
1460    #[doc = "15-beats burst length"]
1461    #[inline(always)]
1462    pub fn _15beat(self) -> &'a mut crate::W<REG> {
1463        self.variant(Burstlenselect::_15beat)
1464    }
1465    #[doc = "16-beats burst length"]
1466    #[inline(always)]
1467    pub fn _16beat(self) -> &'a mut crate::W<REG> {
1468        self.variant(Burstlenselect::_16beat)
1469    }
1470}
1471#[doc = "FIFO Threshold\n\nValue on reset: 0"]
1472#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1473#[repr(u8)]
1474pub enum Thresholdselect {
1475    #[doc = "0: Destination write starts after each beat source address read"]
1476    _1beat = 0,
1477    #[doc = "1: Destination write starts after 2-beats source address read"]
1478    _2beats = 1,
1479    #[doc = "2: Destination write starts after 4-beats source address read"]
1480    _4beats = 2,
1481    #[doc = "3: Destination write starts after 8-beats source address read"]
1482    _8beats = 3,
1483}
1484impl From<Thresholdselect> for u8 {
1485    #[inline(always)]
1486    fn from(variant: Thresholdselect) -> Self {
1487        variant as _
1488    }
1489}
1490impl crate::FieldSpec for Thresholdselect {
1491    type Ux = u8;
1492}
1493impl crate::IsEnum for Thresholdselect {}
1494#[doc = "Field `THRESHOLD` reader - FIFO Threshold"]
1495pub type ThresholdR = crate::FieldReader<Thresholdselect>;
1496impl ThresholdR {
1497    #[doc = "Get enumerated values variant"]
1498    #[inline(always)]
1499    pub const fn variant(&self) -> Thresholdselect {
1500        match self.bits {
1501            0 => Thresholdselect::_1beat,
1502            1 => Thresholdselect::_2beats,
1503            2 => Thresholdselect::_4beats,
1504            3 => Thresholdselect::_8beats,
1505            _ => unreachable!(),
1506        }
1507    }
1508    #[doc = "Destination write starts after each beat source address read"]
1509    #[inline(always)]
1510    pub fn is_1beat(&self) -> bool {
1511        *self == Thresholdselect::_1beat
1512    }
1513    #[doc = "Destination write starts after 2-beats source address read"]
1514    #[inline(always)]
1515    pub fn is_2beats(&self) -> bool {
1516        *self == Thresholdselect::_2beats
1517    }
1518    #[doc = "Destination write starts after 4-beats source address read"]
1519    #[inline(always)]
1520    pub fn is_4beats(&self) -> bool {
1521        *self == Thresholdselect::_4beats
1522    }
1523    #[doc = "Destination write starts after 8-beats source address read"]
1524    #[inline(always)]
1525    pub fn is_8beats(&self) -> bool {
1526        *self == Thresholdselect::_8beats
1527    }
1528}
1529#[doc = "Field `THRESHOLD` writer - FIFO Threshold"]
1530pub type ThresholdW<'a, REG> = crate::FieldWriter<'a, REG, 2, Thresholdselect, crate::Safe>;
1531impl<'a, REG> ThresholdW<'a, REG>
1532where
1533    REG: crate::Writable + crate::RegisterSpec,
1534    REG::Ux: From<u8>,
1535{
1536    #[doc = "Destination write starts after each beat source address read"]
1537    #[inline(always)]
1538    pub fn _1beat(self) -> &'a mut crate::W<REG> {
1539        self.variant(Thresholdselect::_1beat)
1540    }
1541    #[doc = "Destination write starts after 2-beats source address read"]
1542    #[inline(always)]
1543    pub fn _2beats(self) -> &'a mut crate::W<REG> {
1544        self.variant(Thresholdselect::_2beats)
1545    }
1546    #[doc = "Destination write starts after 4-beats source address read"]
1547    #[inline(always)]
1548    pub fn _4beats(self) -> &'a mut crate::W<REG> {
1549        self.variant(Thresholdselect::_4beats)
1550    }
1551    #[doc = "Destination write starts after 8-beats source address read"]
1552    #[inline(always)]
1553    pub fn _8beats(self) -> &'a mut crate::W<REG> {
1554        self.variant(Thresholdselect::_8beats)
1555    }
1556}
1557impl R {
1558    #[doc = "Bit 0 - Channel Software Reset"]
1559    #[inline(always)]
1560    pub fn swrst(&self) -> SwrstR {
1561        SwrstR::new((self.bits & 1) != 0)
1562    }
1563    #[doc = "Bit 1 - Channel Enable"]
1564    #[inline(always)]
1565    pub fn enable(&self) -> EnableR {
1566        EnableR::new(((self.bits >> 1) & 1) != 0)
1567    }
1568    #[doc = "Bit 6 - Channel Run in Standby"]
1569    #[inline(always)]
1570    pub fn runstdby(&self) -> RunstdbyR {
1571        RunstdbyR::new(((self.bits >> 6) & 1) != 0)
1572    }
1573    #[doc = "Bits 8:14 - Trigger Source"]
1574    #[inline(always)]
1575    pub fn trigsrc(&self) -> TrigsrcR {
1576        TrigsrcR::new(((self.bits >> 8) & 0x7f) as u8)
1577    }
1578    #[doc = "Bits 20:21 - Trigger Action"]
1579    #[inline(always)]
1580    pub fn trigact(&self) -> TrigactR {
1581        TrigactR::new(((self.bits >> 20) & 3) as u8)
1582    }
1583    #[doc = "Bits 24:27 - Burst Length"]
1584    #[inline(always)]
1585    pub fn burstlen(&self) -> BurstlenR {
1586        BurstlenR::new(((self.bits >> 24) & 0x0f) as u8)
1587    }
1588    #[doc = "Bits 28:29 - FIFO Threshold"]
1589    #[inline(always)]
1590    pub fn threshold(&self) -> ThresholdR {
1591        ThresholdR::new(((self.bits >> 28) & 3) as u8)
1592    }
1593}
1594impl W {
1595    #[doc = "Bit 0 - Channel Software Reset"]
1596    #[inline(always)]
1597    #[must_use]
1598    pub fn swrst(&mut self) -> SwrstW<ChctrlaSpec> {
1599        SwrstW::new(self, 0)
1600    }
1601    #[doc = "Bit 1 - Channel Enable"]
1602    #[inline(always)]
1603    #[must_use]
1604    pub fn enable(&mut self) -> EnableW<ChctrlaSpec> {
1605        EnableW::new(self, 1)
1606    }
1607    #[doc = "Bit 6 - Channel Run in Standby"]
1608    #[inline(always)]
1609    #[must_use]
1610    pub fn runstdby(&mut self) -> RunstdbyW<ChctrlaSpec> {
1611        RunstdbyW::new(self, 6)
1612    }
1613    #[doc = "Bits 8:14 - Trigger Source"]
1614    #[inline(always)]
1615    #[must_use]
1616    pub fn trigsrc(&mut self) -> TrigsrcW<ChctrlaSpec> {
1617        TrigsrcW::new(self, 8)
1618    }
1619    #[doc = "Bits 20:21 - Trigger Action"]
1620    #[inline(always)]
1621    #[must_use]
1622    pub fn trigact(&mut self) -> TrigactW<ChctrlaSpec> {
1623        TrigactW::new(self, 20)
1624    }
1625    #[doc = "Bits 24:27 - Burst Length"]
1626    #[inline(always)]
1627    #[must_use]
1628    pub fn burstlen(&mut self) -> BurstlenW<ChctrlaSpec> {
1629        BurstlenW::new(self, 24)
1630    }
1631    #[doc = "Bits 28:29 - FIFO Threshold"]
1632    #[inline(always)]
1633    #[must_use]
1634    pub fn threshold(&mut self) -> ThresholdW<ChctrlaSpec> {
1635        ThresholdW::new(self, 28)
1636    }
1637}
1638#[doc = "Channel n Control A\n\nYou can [`read`](crate::Reg::read) this register and get [`chctrla::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chctrla::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
1639pub struct ChctrlaSpec;
1640impl crate::RegisterSpec for ChctrlaSpec {
1641    type Ux = u32;
1642}
1643#[doc = "`read()` method returns [`chctrla::R`](R) reader structure"]
1644impl crate::Readable for ChctrlaSpec {}
1645#[doc = "`write(|w| ..)` method takes [`chctrla::W`](W) writer structure"]
1646impl crate::Writable for ChctrlaSpec {
1647    type Safety = crate::Unsafe;
1648    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
1649    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
1650}
1651#[doc = "`reset()` method sets CHCTRLA to value 0"]
1652impl crate::Resettable for ChctrlaSpec {
1653    const RESET_VALUE: u32 = 0;
1654}
atsamd51p/dmac/channel/chctrla.rs

atsamd51p/dmac/channel/
chctrla.rs
