atsamd51p/icm/
idr.rs

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1#[doc = "Register `IDR` writer"]
2pub type W = crate::W<IdrSpec>;
3#[doc = "Field `RHC` writer - Region Hash Completed Interrupt Disable"]
4pub type RhcW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
5#[doc = "Field `RDM` writer - Region Digest Mismatch Interrupt Disable"]
6pub type RdmW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
7#[doc = "Field `RBE` writer - Region Bus Error Interrupt Disable"]
8pub type RbeW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
9#[doc = "Field `RWC` writer - Region Wrap Condition Detected Interrupt Disable"]
10pub type RwcW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
11#[doc = "Field `REC` writer - Region End bit Condition detected Interrupt Disable"]
12pub type RecW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
13#[doc = "Field `RSU` writer - Region Status Updated Interrupt Disable"]
14pub type RsuW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
15#[doc = "Field `URAD` writer - Undefined Register Access Detection Interrupt Disable"]
16pub type UradW<'a, REG> = crate::BitWriter<'a, REG>;
17impl W {
18    #[doc = "Bits 0:3 - Region Hash Completed Interrupt Disable"]
19    #[inline(always)]
20    #[must_use]
21    pub fn rhc(&mut self) -> RhcW<IdrSpec> {
22        RhcW::new(self, 0)
23    }
24    #[doc = "Bits 4:7 - Region Digest Mismatch Interrupt Disable"]
25    #[inline(always)]
26    #[must_use]
27    pub fn rdm(&mut self) -> RdmW<IdrSpec> {
28        RdmW::new(self, 4)
29    }
30    #[doc = "Bits 8:11 - Region Bus Error Interrupt Disable"]
31    #[inline(always)]
32    #[must_use]
33    pub fn rbe(&mut self) -> RbeW<IdrSpec> {
34        RbeW::new(self, 8)
35    }
36    #[doc = "Bits 12:15 - Region Wrap Condition Detected Interrupt Disable"]
37    #[inline(always)]
38    #[must_use]
39    pub fn rwc(&mut self) -> RwcW<IdrSpec> {
40        RwcW::new(self, 12)
41    }
42    #[doc = "Bits 16:19 - Region End bit Condition detected Interrupt Disable"]
43    #[inline(always)]
44    #[must_use]
45    pub fn rec(&mut self) -> RecW<IdrSpec> {
46        RecW::new(self, 16)
47    }
48    #[doc = "Bits 20:23 - Region Status Updated Interrupt Disable"]
49    #[inline(always)]
50    #[must_use]
51    pub fn rsu(&mut self) -> RsuW<IdrSpec> {
52        RsuW::new(self, 20)
53    }
54    #[doc = "Bit 24 - Undefined Register Access Detection Interrupt Disable"]
55    #[inline(always)]
56    #[must_use]
57    pub fn urad(&mut self) -> UradW<IdrSpec> {
58        UradW::new(self, 24)
59    }
60}
61#[doc = "Interrupt Disable\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`idr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
62pub struct IdrSpec;
63impl crate::RegisterSpec for IdrSpec {
64    type Ux = u32;
65}
66#[doc = "`write(|w| ..)` method takes [`idr::W`](W) writer structure"]
67impl crate::Writable for IdrSpec {
68    type Safety = crate::Unsafe;
69    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
70    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
71}
72#[doc = "`reset()` method sets IDR to value 0"]
73impl crate::Resettable for IdrSpec {
74    const RESET_VALUE: u32 = 0;
75}
atsamd51p/icm/idr.rs

atsamd51p/icm/
idr.rs
