atsamd51p/mclk/
apbcmask.rs

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1#[doc = "Register `APBCMASK` reader"]
2pub type R = crate::R<ApbcmaskSpec>;
3#[doc = "Register `APBCMASK` writer"]
4pub type W = crate::W<ApbcmaskSpec>;
5#[doc = "Field `TCC2_` reader - TCC2 APB Clock Enable"]
6pub type Tcc2_R = crate::BitReader;
7#[doc = "Field `TCC2_` writer - TCC2 APB Clock Enable"]
8pub type Tcc2_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `TCC3_` reader - TCC3 APB Clock Enable"]
10pub type Tcc3_R = crate::BitReader;
11#[doc = "Field `TCC3_` writer - TCC3 APB Clock Enable"]
12pub type Tcc3_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `TC4_` reader - TC4 APB Clock Enable"]
14pub type Tc4_R = crate::BitReader;
15#[doc = "Field `TC4_` writer - TC4 APB Clock Enable"]
16pub type Tc4_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `TC5_` reader - TC5 APB Clock Enable"]
18pub type Tc5_R = crate::BitReader;
19#[doc = "Field `TC5_` writer - TC5 APB Clock Enable"]
20pub type Tc5_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `PDEC_` reader - PDEC APB Clock Enable"]
22pub type Pdec_R = crate::BitReader;
23#[doc = "Field `PDEC_` writer - PDEC APB Clock Enable"]
24pub type Pdec_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `AC_` reader - AC APB Clock Enable"]
26pub type Ac_R = crate::BitReader;
27#[doc = "Field `AC_` writer - AC APB Clock Enable"]
28pub type Ac_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `AES_` reader - AES APB Clock Enable"]
30pub type Aes_R = crate::BitReader;
31#[doc = "Field `AES_` writer - AES APB Clock Enable"]
32pub type Aes_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `TRNG_` reader - TRNG APB Clock Enable"]
34pub type Trng_R = crate::BitReader;
35#[doc = "Field `TRNG_` writer - TRNG APB Clock Enable"]
36pub type Trng_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `ICM_` reader - ICM APB Clock Enable"]
38pub type Icm_R = crate::BitReader;
39#[doc = "Field `ICM_` writer - ICM APB Clock Enable"]
40pub type Icm_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `QSPI_` reader - QSPI APB Clock Enable"]
42pub type Qspi_R = crate::BitReader;
43#[doc = "Field `QSPI_` writer - QSPI APB Clock Enable"]
44pub type Qspi_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `CCL_` reader - CCL APB Clock Enable"]
46pub type Ccl_R = crate::BitReader;
47#[doc = "Field `CCL_` writer - CCL APB Clock Enable"]
48pub type Ccl_W<'a, REG> = crate::BitWriter<'a, REG>;
49impl R {
50    #[doc = "Bit 3 - TCC2 APB Clock Enable"]
51    #[inline(always)]
52    pub fn tcc2_(&self) -> Tcc2_R {
53        Tcc2_R::new(((self.bits >> 3) & 1) != 0)
54    }
55    #[doc = "Bit 4 - TCC3 APB Clock Enable"]
56    #[inline(always)]
57    pub fn tcc3_(&self) -> Tcc3_R {
58        Tcc3_R::new(((self.bits >> 4) & 1) != 0)
59    }
60    #[doc = "Bit 5 - TC4 APB Clock Enable"]
61    #[inline(always)]
62    pub fn tc4_(&self) -> Tc4_R {
63        Tc4_R::new(((self.bits >> 5) & 1) != 0)
64    }
65    #[doc = "Bit 6 - TC5 APB Clock Enable"]
66    #[inline(always)]
67    pub fn tc5_(&self) -> Tc5_R {
68        Tc5_R::new(((self.bits >> 6) & 1) != 0)
69    }
70    #[doc = "Bit 7 - PDEC APB Clock Enable"]
71    #[inline(always)]
72    pub fn pdec_(&self) -> Pdec_R {
73        Pdec_R::new(((self.bits >> 7) & 1) != 0)
74    }
75    #[doc = "Bit 8 - AC APB Clock Enable"]
76    #[inline(always)]
77    pub fn ac_(&self) -> Ac_R {
78        Ac_R::new(((self.bits >> 8) & 1) != 0)
79    }
80    #[doc = "Bit 9 - AES APB Clock Enable"]
81    #[inline(always)]
82    pub fn aes_(&self) -> Aes_R {
83        Aes_R::new(((self.bits >> 9) & 1) != 0)
84    }
85    #[doc = "Bit 10 - TRNG APB Clock Enable"]
86    #[inline(always)]
87    pub fn trng_(&self) -> Trng_R {
88        Trng_R::new(((self.bits >> 10) & 1) != 0)
89    }
90    #[doc = "Bit 11 - ICM APB Clock Enable"]
91    #[inline(always)]
92    pub fn icm_(&self) -> Icm_R {
93        Icm_R::new(((self.bits >> 11) & 1) != 0)
94    }
95    #[doc = "Bit 13 - QSPI APB Clock Enable"]
96    #[inline(always)]
97    pub fn qspi_(&self) -> Qspi_R {
98        Qspi_R::new(((self.bits >> 13) & 1) != 0)
99    }
100    #[doc = "Bit 14 - CCL APB Clock Enable"]
101    #[inline(always)]
102    pub fn ccl_(&self) -> Ccl_R {
103        Ccl_R::new(((self.bits >> 14) & 1) != 0)
104    }
105}
106impl W {
107    #[doc = "Bit 3 - TCC2 APB Clock Enable"]
108    #[inline(always)]
109    #[must_use]
110    pub fn tcc2_(&mut self) -> Tcc2_W<ApbcmaskSpec> {
111        Tcc2_W::new(self, 3)
112    }
113    #[doc = "Bit 4 - TCC3 APB Clock Enable"]
114    #[inline(always)]
115    #[must_use]
116    pub fn tcc3_(&mut self) -> Tcc3_W<ApbcmaskSpec> {
117        Tcc3_W::new(self, 4)
118    }
119    #[doc = "Bit 5 - TC4 APB Clock Enable"]
120    #[inline(always)]
121    #[must_use]
122    pub fn tc4_(&mut self) -> Tc4_W<ApbcmaskSpec> {
123        Tc4_W::new(self, 5)
124    }
125    #[doc = "Bit 6 - TC5 APB Clock Enable"]
126    #[inline(always)]
127    #[must_use]
128    pub fn tc5_(&mut self) -> Tc5_W<ApbcmaskSpec> {
129        Tc5_W::new(self, 6)
130    }
131    #[doc = "Bit 7 - PDEC APB Clock Enable"]
132    #[inline(always)]
133    #[must_use]
134    pub fn pdec_(&mut self) -> Pdec_W<ApbcmaskSpec> {
135        Pdec_W::new(self, 7)
136    }
137    #[doc = "Bit 8 - AC APB Clock Enable"]
138    #[inline(always)]
139    #[must_use]
140    pub fn ac_(&mut self) -> Ac_W<ApbcmaskSpec> {
141        Ac_W::new(self, 8)
142    }
143    #[doc = "Bit 9 - AES APB Clock Enable"]
144    #[inline(always)]
145    #[must_use]
146    pub fn aes_(&mut self) -> Aes_W<ApbcmaskSpec> {
147        Aes_W::new(self, 9)
148    }
149    #[doc = "Bit 10 - TRNG APB Clock Enable"]
150    #[inline(always)]
151    #[must_use]
152    pub fn trng_(&mut self) -> Trng_W<ApbcmaskSpec> {
153        Trng_W::new(self, 10)
154    }
155    #[doc = "Bit 11 - ICM APB Clock Enable"]
156    #[inline(always)]
157    #[must_use]
158    pub fn icm_(&mut self) -> Icm_W<ApbcmaskSpec> {
159        Icm_W::new(self, 11)
160    }
161    #[doc = "Bit 13 - QSPI APB Clock Enable"]
162    #[inline(always)]
163    #[must_use]
164    pub fn qspi_(&mut self) -> Qspi_W<ApbcmaskSpec> {
165        Qspi_W::new(self, 13)
166    }
167    #[doc = "Bit 14 - CCL APB Clock Enable"]
168    #[inline(always)]
169    #[must_use]
170    pub fn ccl_(&mut self) -> Ccl_W<ApbcmaskSpec> {
171        Ccl_W::new(self, 14)
172    }
173}
174#[doc = "APBC Mask\n\nYou can [`read`](crate::Reg::read) this register and get [`apbcmask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apbcmask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
175pub struct ApbcmaskSpec;
176impl crate::RegisterSpec for ApbcmaskSpec {
177    type Ux = u32;
178}
179#[doc = "`read()` method returns [`apbcmask::R`](R) reader structure"]
180impl crate::Readable for ApbcmaskSpec {}
181#[doc = "`write(|w| ..)` method takes [`apbcmask::W`](W) writer structure"]
182impl crate::Writable for ApbcmaskSpec {
183    type Safety = crate::Unsafe;
184    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
185    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
186}
187#[doc = "`reset()` method sets APBCMASK to value 0x2000"]
188impl crate::Resettable for ApbcmaskSpec {
189    const RESET_VALUE: u32 = 0x2000;
190}
atsamd51p/mclk/apbcmask.rs

atsamd51p/mclk/
apbcmask.rs
