atsamd51p/sdhc0/
cc2r.rs

1#[doc = "Register `CC2R` reader"]
2pub type R = crate::R<Cc2rSpec>;
3#[doc = "Register `CC2R` writer"]
4pub type W = crate::W<Cc2rSpec>;
5#[doc = "Force SDCK Disabled\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7pub enum Fsdclkdselect {
8    #[doc = "0: No effect"]
9    Noeffect = 0,
10    #[doc = "1: SDCLK can be stopped at any time after DATA transfer.SDCLK enable forcing for 8 SDCLK cycles is disabled"]
11    Disable = 1,
12}
13impl From<Fsdclkdselect> for bool {
14    #[inline(always)]
15    fn from(variant: Fsdclkdselect) -> Self {
16        variant as u8 != 0
17    }
18}
19#[doc = "Field `FSDCLKD` reader - Force SDCK Disabled"]
20pub type FsdclkdR = crate::BitReader<Fsdclkdselect>;
21impl FsdclkdR {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> Fsdclkdselect {
25        match self.bits {
26            false => Fsdclkdselect::Noeffect,
27            true => Fsdclkdselect::Disable,
28        }
29    }
30    #[doc = "No effect"]
31    #[inline(always)]
32    pub fn is_noeffect(&self) -> bool {
33        *self == Fsdclkdselect::Noeffect
34    }
35    #[doc = "SDCLK can be stopped at any time after DATA transfer.SDCLK enable forcing for 8 SDCLK cycles is disabled"]
36    #[inline(always)]
37    pub fn is_disable(&self) -> bool {
38        *self == Fsdclkdselect::Disable
39    }
40}
41#[doc = "Field `FSDCLKD` writer - Force SDCK Disabled"]
42pub type FsdclkdW<'a, REG> = crate::BitWriter<'a, REG, Fsdclkdselect>;
43impl<'a, REG> FsdclkdW<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "No effect"]
48    #[inline(always)]
49    pub fn noeffect(self) -> &'a mut crate::W<REG> {
50        self.variant(Fsdclkdselect::Noeffect)
51    }
52    #[doc = "SDCLK can be stopped at any time after DATA transfer.SDCLK enable forcing for 8 SDCLK cycles is disabled"]
53    #[inline(always)]
54    pub fn disable(self) -> &'a mut crate::W<REG> {
55        self.variant(Fsdclkdselect::Disable)
56    }
57}
58impl R {
59    #[doc = "Bit 0 - Force SDCK Disabled"]
60    #[inline(always)]
61    pub fn fsdclkd(&self) -> FsdclkdR {
62        FsdclkdR::new((self.bits & 1) != 0)
63    }
64}
65impl W {
66    #[doc = "Bit 0 - Force SDCK Disabled"]
67    #[inline(always)]
68    #[must_use]
69    pub fn fsdclkd(&mut self) -> FsdclkdW<Cc2rSpec> {
70        FsdclkdW::new(self, 0)
71    }
72}
73#[doc = "Clock Control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`cc2r::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cc2r::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
74pub struct Cc2rSpec;
75impl crate::RegisterSpec for Cc2rSpec {
76    type Ux = u32;
77}
78#[doc = "`read()` method returns [`cc2r::R`](R) reader structure"]
79impl crate::Readable for Cc2rSpec {}
80#[doc = "`write(|w| ..)` method takes [`cc2r::W`](W) writer structure"]
81impl crate::Writable for Cc2rSpec {
82    type Safety = crate::Unsafe;
83    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
84    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
85}
86#[doc = "`reset()` method sets CC2R to value 0"]
87impl crate::Resettable for Cc2rSpec {
88    const RESET_VALUE: u32 = 0;
89}
atsamd51p/sdhc0/cc2r.rs

atsamd51p/sdhc0/
cc2r.rs
