atsamd51p/sercom0/spim/
ctrlc.rs

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1#[doc = "Register `CTRLC` reader"]
2pub type R = crate::R<CtrlcSpec>;
3#[doc = "Register `CTRLC` writer"]
4pub type W = crate::W<CtrlcSpec>;
5#[doc = "Field `ICSPACE` reader - Inter-Character Spacing"]
6pub type IcspaceR = crate::FieldReader;
7#[doc = "Field `ICSPACE` writer - Inter-Character Spacing"]
8pub type IcspaceW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
9#[doc = "Data 32 Bit\n\nValue on reset: 0"]
10#[derive(Clone, Copy, Debug, PartialEq, Eq)]
11pub enum Data32bselect {
12    #[doc = "0: Transaction from and to DATA register are 8-bit"]
13    DataTrans8bit = 0,
14    #[doc = "1: Transaction from and to DATA register are 32-bit"]
15    DataTrans32bit = 1,
16}
17impl From<Data32bselect> for bool {
18    #[inline(always)]
19    fn from(variant: Data32bselect) -> Self {
20        variant as u8 != 0
21    }
22}
23#[doc = "Field `DATA32B` reader - Data 32 Bit"]
24pub type Data32bR = crate::BitReader<Data32bselect>;
25impl Data32bR {
26    #[doc = "Get enumerated values variant"]
27    #[inline(always)]
28    pub const fn variant(&self) -> Data32bselect {
29        match self.bits {
30            false => Data32bselect::DataTrans8bit,
31            true => Data32bselect::DataTrans32bit,
32        }
33    }
34    #[doc = "Transaction from and to DATA register are 8-bit"]
35    #[inline(always)]
36    pub fn is_data_trans_8bit(&self) -> bool {
37        *self == Data32bselect::DataTrans8bit
38    }
39    #[doc = "Transaction from and to DATA register are 32-bit"]
40    #[inline(always)]
41    pub fn is_data_trans_32bit(&self) -> bool {
42        *self == Data32bselect::DataTrans32bit
43    }
44}
45#[doc = "Field `DATA32B` writer - Data 32 Bit"]
46pub type Data32bW<'a, REG> = crate::BitWriter<'a, REG, Data32bselect>;
47impl<'a, REG> Data32bW<'a, REG>
48where
49    REG: crate::Writable + crate::RegisterSpec,
50{
51    #[doc = "Transaction from and to DATA register are 8-bit"]
52    #[inline(always)]
53    pub fn data_trans_8bit(self) -> &'a mut crate::W<REG> {
54        self.variant(Data32bselect::DataTrans8bit)
55    }
56    #[doc = "Transaction from and to DATA register are 32-bit"]
57    #[inline(always)]
58    pub fn data_trans_32bit(self) -> &'a mut crate::W<REG> {
59        self.variant(Data32bselect::DataTrans32bit)
60    }
61}
62impl R {
63    #[doc = "Bits 0:5 - Inter-Character Spacing"]
64    #[inline(always)]
65    pub fn icspace(&self) -> IcspaceR {
66        IcspaceR::new((self.bits & 0x3f) as u8)
67    }
68    #[doc = "Bit 24 - Data 32 Bit"]
69    #[inline(always)]
70    pub fn data32b(&self) -> Data32bR {
71        Data32bR::new(((self.bits >> 24) & 1) != 0)
72    }
73}
74impl W {
75    #[doc = "Bits 0:5 - Inter-Character Spacing"]
76    #[inline(always)]
77    #[must_use]
78    pub fn icspace(&mut self) -> IcspaceW<CtrlcSpec> {
79        IcspaceW::new(self, 0)
80    }
81    #[doc = "Bit 24 - Data 32 Bit"]
82    #[inline(always)]
83    #[must_use]
84    pub fn data32b(&mut self) -> Data32bW<CtrlcSpec> {
85        Data32bW::new(self, 24)
86    }
87}
88#[doc = "SPIM Control C\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrlc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrlc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
89pub struct CtrlcSpec;
90impl crate::RegisterSpec for CtrlcSpec {
91    type Ux = u32;
92}
93#[doc = "`read()` method returns [`ctrlc::R`](R) reader structure"]
94impl crate::Readable for CtrlcSpec {}
95#[doc = "`write(|w| ..)` method takes [`ctrlc::W`](W) writer structure"]
96impl crate::Writable for CtrlcSpec {
97    type Safety = crate::Unsafe;
98    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
99    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
100}
101#[doc = "`reset()` method sets CTRLC to value 0"]
102impl crate::Resettable for CtrlcSpec {
103    const RESET_VALUE: u32 = 0;
104}
atsamd51p/sercom0/spim/ctrlc.rs

atsamd51p/sercom0/spim/
ctrlc.rs
