1#[repr(C)]
2#[doc = "Register block"]
3pub struct RegisterBlock {
4 ctrla: Ctrla,
5 _reserved1: [u8; 0x03],
6 clkctrl: [Clkctrl; 2],
7 intenclr: Intenclr,
8 _reserved3: [u8; 0x02],
9 intenset: Intenset,
10 _reserved4: [u8; 0x02],
11 intflag: Intflag,
12 _reserved5: [u8; 0x02],
13 syncbusy: Syncbusy,
14 _reserved6: [u8; 0x06],
15 txctrl: Txctrl,
16 rxctrl: Rxctrl,
17 _reserved8: [u8; 0x08],
18 txdata: Txdata,
19 rxdata: Rxdata,
20}
21impl RegisterBlock {
22 #[doc = "0x00 - Control A"]
23 #[inline(always)]
24 pub const fn ctrla(&self) -> &Ctrla {
25 &self.ctrla
26 }
27 #[doc = "0x04..0x0c - Clock Unit n Control"]
28 #[inline(always)]
29 pub const fn clkctrl(&self, n: usize) -> &Clkctrl {
30 &self.clkctrl[n]
31 }
32 #[doc = "Iterator for array of:"]
33 #[doc = "0x04..0x0c - Clock Unit n Control"]
34 #[inline(always)]
35 pub fn clkctrl_iter(&self) -> impl Iterator<Item = &Clkctrl> {
36 self.clkctrl.iter()
37 }
38 #[doc = "0x0c - Interrupt Enable Clear"]
39 #[inline(always)]
40 pub const fn intenclr(&self) -> &Intenclr {
41 &self.intenclr
42 }
43 #[doc = "0x10 - Interrupt Enable Set"]
44 #[inline(always)]
45 pub const fn intenset(&self) -> &Intenset {
46 &self.intenset
47 }
48 #[doc = "0x14 - Interrupt Flag Status and Clear"]
49 #[inline(always)]
50 pub const fn intflag(&self) -> &Intflag {
51 &self.intflag
52 }
53 #[doc = "0x18 - Synchronization Status"]
54 #[inline(always)]
55 pub const fn syncbusy(&self) -> &Syncbusy {
56 &self.syncbusy
57 }
58 #[doc = "0x20 - Tx Serializer Control"]
59 #[inline(always)]
60 pub const fn txctrl(&self) -> &Txctrl {
61 &self.txctrl
62 }
63 #[doc = "0x24 - Rx Serializer Control"]
64 #[inline(always)]
65 pub const fn rxctrl(&self) -> &Rxctrl {
66 &self.rxctrl
67 }
68 #[doc = "0x30 - Tx Data"]
69 #[inline(always)]
70 pub const fn txdata(&self) -> &Txdata {
71 &self.txdata
72 }
73 #[doc = "0x34 - Rx Data"]
74 #[inline(always)]
75 pub const fn rxdata(&self) -> &Rxdata {
76 &self.rxdata
77 }
78}
79#[doc = "CTRLA (rw) register accessor: Control A\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrla::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrla::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrla`]
80module"]
81#[doc(alias = "CTRLA")]
82pub type Ctrla = crate::Reg<ctrla::CtrlaSpec>;
83#[doc = "Control A"]
84pub mod ctrla;
85#[doc = "CLKCTRL (rw) register accessor: Clock Unit n Control\n\nYou can [`read`](crate::Reg::read) this register and get [`clkctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkctrl`]
86module"]
87#[doc(alias = "CLKCTRL")]
88pub type Clkctrl = crate::Reg<clkctrl::ClkctrlSpec>;
89#[doc = "Clock Unit n Control"]
90pub mod clkctrl;
91#[doc = "INTENCLR (rw) register accessor: Interrupt Enable Clear\n\nYou can [`read`](crate::Reg::read) this register and get [`intenclr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intenclr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intenclr`]
92module"]
93#[doc(alias = "INTENCLR")]
94pub type Intenclr = crate::Reg<intenclr::IntenclrSpec>;
95#[doc = "Interrupt Enable Clear"]
96pub mod intenclr;
97#[doc = "INTENSET (rw) register accessor: Interrupt Enable Set\n\nYou can [`read`](crate::Reg::read) this register and get [`intenset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intenset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intenset`]
98module"]
99#[doc(alias = "INTENSET")]
100pub type Intenset = crate::Reg<intenset::IntensetSpec>;
101#[doc = "Interrupt Enable Set"]
102pub mod intenset;
103#[doc = "INTFLAG (rw) register accessor: Interrupt Flag Status and Clear\n\nYou can [`read`](crate::Reg::read) this register and get [`intflag::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intflag::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intflag`]
104module"]
105#[doc(alias = "INTFLAG")]
106pub type Intflag = crate::Reg<intflag::IntflagSpec>;
107#[doc = "Interrupt Flag Status and Clear"]
108pub mod intflag;
109#[doc = "SYNCBUSY (r) register accessor: Synchronization Status\n\nYou can [`read`](crate::Reg::read) this register and get [`syncbusy::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@syncbusy`]
110module"]
111#[doc(alias = "SYNCBUSY")]
112pub type Syncbusy = crate::Reg<syncbusy::SyncbusySpec>;
113#[doc = "Synchronization Status"]
114pub mod syncbusy;
115#[doc = "TXCTRL (rw) register accessor: Tx Serializer Control\n\nYou can [`read`](crate::Reg::read) this register and get [`txctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txctrl`]
116module"]
117#[doc(alias = "TXCTRL")]
118pub type Txctrl = crate::Reg<txctrl::TxctrlSpec>;
119#[doc = "Tx Serializer Control"]
120pub mod txctrl;
121#[doc = "RXCTRL (rw) register accessor: Rx Serializer Control\n\nYou can [`read`](crate::Reg::read) this register and get [`rxctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxctrl`]
122module"]
123#[doc(alias = "RXCTRL")]
124pub type Rxctrl = crate::Reg<rxctrl::RxctrlSpec>;
125#[doc = "Rx Serializer Control"]
126pub mod rxctrl;
127#[doc = "TXDATA (w) register accessor: Tx Data\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txdata::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txdata`]
128module"]
129#[doc(alias = "TXDATA")]
130pub type Txdata = crate::Reg<txdata::TxdataSpec>;
131#[doc = "Tx Data"]
132pub mod txdata;
133#[doc = "RXDATA (r) register accessor: Rx Data\n\nYou can [`read`](crate::Reg::read) this register and get [`rxdata::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxdata`]
134module"]
135#[doc(alias = "RXDATA")]
136pub type Rxdata = crate::Reg<rxdata::RxdataSpec>;
137#[doc = "Rx Data"]
138pub mod rxdata;