atsamd51p/rtc/mode2/
ctrla.rs

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1#[doc = "Register `CTRLA` reader"]
2pub type R = crate::R<CtrlaSpec>;
3#[doc = "Register `CTRLA` writer"]
4pub type W = crate::W<CtrlaSpec>;
5#[doc = "Field `SWRST` reader - Software Reset"]
6pub type SwrstR = crate::BitReader;
7#[doc = "Field `SWRST` writer - Software Reset"]
8pub type SwrstW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `ENABLE` reader - Enable"]
10pub type EnableR = crate::BitReader;
11#[doc = "Field `ENABLE` writer - Enable"]
12pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Operating Mode\n\nValue on reset: 0"]
14#[derive(Clone, Copy, Debug, PartialEq, Eq)]
15#[repr(u8)]
16pub enum Modeselect {
17    #[doc = "0: Mode 0: 32-bit Counter"]
18    Count32 = 0,
19    #[doc = "1: Mode 1: 16-bit Counter"]
20    Count16 = 1,
21    #[doc = "2: Mode 2: Clock/Calendar"]
22    Clock = 2,
23}
24impl From<Modeselect> for u8 {
25    #[inline(always)]
26    fn from(variant: Modeselect) -> Self {
27        variant as _
28    }
29}
30impl crate::FieldSpec for Modeselect {
31    type Ux = u8;
32}
33impl crate::IsEnum for Modeselect {}
34#[doc = "Field `MODE` reader - Operating Mode"]
35pub type ModeR = crate::FieldReader<Modeselect>;
36impl ModeR {
37    #[doc = "Get enumerated values variant"]
38    #[inline(always)]
39    pub const fn variant(&self) -> Option<Modeselect> {
40        match self.bits {
41            0 => Some(Modeselect::Count32),
42            1 => Some(Modeselect::Count16),
43            2 => Some(Modeselect::Clock),
44            _ => None,
45        }
46    }
47    #[doc = "Mode 0: 32-bit Counter"]
48    #[inline(always)]
49    pub fn is_count32(&self) -> bool {
50        *self == Modeselect::Count32
51    }
52    #[doc = "Mode 1: 16-bit Counter"]
53    #[inline(always)]
54    pub fn is_count16(&self) -> bool {
55        *self == Modeselect::Count16
56    }
57    #[doc = "Mode 2: Clock/Calendar"]
58    #[inline(always)]
59    pub fn is_clock(&self) -> bool {
60        *self == Modeselect::Clock
61    }
62}
63#[doc = "Field `MODE` writer - Operating Mode"]
64pub type ModeW<'a, REG> = crate::FieldWriter<'a, REG, 2, Modeselect>;
65impl<'a, REG> ModeW<'a, REG>
66where
67    REG: crate::Writable + crate::RegisterSpec,
68    REG::Ux: From<u8>,
69{
70    #[doc = "Mode 0: 32-bit Counter"]
71    #[inline(always)]
72    pub fn count32(self) -> &'a mut crate::W<REG> {
73        self.variant(Modeselect::Count32)
74    }
75    #[doc = "Mode 1: 16-bit Counter"]
76    #[inline(always)]
77    pub fn count16(self) -> &'a mut crate::W<REG> {
78        self.variant(Modeselect::Count16)
79    }
80    #[doc = "Mode 2: Clock/Calendar"]
81    #[inline(always)]
82    pub fn clock(self) -> &'a mut crate::W<REG> {
83        self.variant(Modeselect::Clock)
84    }
85}
86#[doc = "Field `CLKREP` reader - Clock Representation"]
87pub type ClkrepR = crate::BitReader;
88#[doc = "Field `CLKREP` writer - Clock Representation"]
89pub type ClkrepW<'a, REG> = crate::BitWriter<'a, REG>;
90#[doc = "Field `MATCHCLR` reader - Clear on Match"]
91pub type MatchclrR = crate::BitReader;
92#[doc = "Field `MATCHCLR` writer - Clear on Match"]
93pub type MatchclrW<'a, REG> = crate::BitWriter<'a, REG>;
94#[doc = "Prescaler\n\nValue on reset: 0"]
95#[derive(Clone, Copy, Debug, PartialEq, Eq)]
96#[repr(u8)]
97pub enum Prescalerselect {
98    #[doc = "0: CLK_RTC_CNT = GCLK_RTC/1"]
99    Off = 0,
100    #[doc = "1: CLK_RTC_CNT = GCLK_RTC/1"]
101    Div1 = 1,
102    #[doc = "2: CLK_RTC_CNT = GCLK_RTC/2"]
103    Div2 = 2,
104    #[doc = "3: CLK_RTC_CNT = GCLK_RTC/4"]
105    Div4 = 3,
106    #[doc = "4: CLK_RTC_CNT = GCLK_RTC/8"]
107    Div8 = 4,
108    #[doc = "5: CLK_RTC_CNT = GCLK_RTC/16"]
109    Div16 = 5,
110    #[doc = "6: CLK_RTC_CNT = GCLK_RTC/32"]
111    Div32 = 6,
112    #[doc = "7: CLK_RTC_CNT = GCLK_RTC/64"]
113    Div64 = 7,
114    #[doc = "8: CLK_RTC_CNT = GCLK_RTC/128"]
115    Div128 = 8,
116    #[doc = "9: CLK_RTC_CNT = GCLK_RTC/256"]
117    Div256 = 9,
118    #[doc = "10: CLK_RTC_CNT = GCLK_RTC/512"]
119    Div512 = 10,
120    #[doc = "11: CLK_RTC_CNT = GCLK_RTC/1024"]
121    Div1024 = 11,
122}
123impl From<Prescalerselect> for u8 {
124    #[inline(always)]
125    fn from(variant: Prescalerselect) -> Self {
126        variant as _
127    }
128}
129impl crate::FieldSpec for Prescalerselect {
130    type Ux = u8;
131}
132impl crate::IsEnum for Prescalerselect {}
133#[doc = "Field `PRESCALER` reader - Prescaler"]
134pub type PrescalerR = crate::FieldReader<Prescalerselect>;
135impl PrescalerR {
136    #[doc = "Get enumerated values variant"]
137    #[inline(always)]
138    pub const fn variant(&self) -> Option<Prescalerselect> {
139        match self.bits {
140            0 => Some(Prescalerselect::Off),
141            1 => Some(Prescalerselect::Div1),
142            2 => Some(Prescalerselect::Div2),
143            3 => Some(Prescalerselect::Div4),
144            4 => Some(Prescalerselect::Div8),
145            5 => Some(Prescalerselect::Div16),
146            6 => Some(Prescalerselect::Div32),
147            7 => Some(Prescalerselect::Div64),
148            8 => Some(Prescalerselect::Div128),
149            9 => Some(Prescalerselect::Div256),
150            10 => Some(Prescalerselect::Div512),
151            11 => Some(Prescalerselect::Div1024),
152            _ => None,
153        }
154    }
155    #[doc = "CLK_RTC_CNT = GCLK_RTC/1"]
156    #[inline(always)]
157    pub fn is_off(&self) -> bool {
158        *self == Prescalerselect::Off
159    }
160    #[doc = "CLK_RTC_CNT = GCLK_RTC/1"]
161    #[inline(always)]
162    pub fn is_div1(&self) -> bool {
163        *self == Prescalerselect::Div1
164    }
165    #[doc = "CLK_RTC_CNT = GCLK_RTC/2"]
166    #[inline(always)]
167    pub fn is_div2(&self) -> bool {
168        *self == Prescalerselect::Div2
169    }
170    #[doc = "CLK_RTC_CNT = GCLK_RTC/4"]
171    #[inline(always)]
172    pub fn is_div4(&self) -> bool {
173        *self == Prescalerselect::Div4
174    }
175    #[doc = "CLK_RTC_CNT = GCLK_RTC/8"]
176    #[inline(always)]
177    pub fn is_div8(&self) -> bool {
178        *self == Prescalerselect::Div8
179    }
180    #[doc = "CLK_RTC_CNT = GCLK_RTC/16"]
181    #[inline(always)]
182    pub fn is_div16(&self) -> bool {
183        *self == Prescalerselect::Div16
184    }
185    #[doc = "CLK_RTC_CNT = GCLK_RTC/32"]
186    #[inline(always)]
187    pub fn is_div32(&self) -> bool {
188        *self == Prescalerselect::Div32
189    }
190    #[doc = "CLK_RTC_CNT = GCLK_RTC/64"]
191    #[inline(always)]
192    pub fn is_div64(&self) -> bool {
193        *self == Prescalerselect::Div64
194    }
195    #[doc = "CLK_RTC_CNT = GCLK_RTC/128"]
196    #[inline(always)]
197    pub fn is_div128(&self) -> bool {
198        *self == Prescalerselect::Div128
199    }
200    #[doc = "CLK_RTC_CNT = GCLK_RTC/256"]
201    #[inline(always)]
202    pub fn is_div256(&self) -> bool {
203        *self == Prescalerselect::Div256
204    }
205    #[doc = "CLK_RTC_CNT = GCLK_RTC/512"]
206    #[inline(always)]
207    pub fn is_div512(&self) -> bool {
208        *self == Prescalerselect::Div512
209    }
210    #[doc = "CLK_RTC_CNT = GCLK_RTC/1024"]
211    #[inline(always)]
212    pub fn is_div1024(&self) -> bool {
213        *self == Prescalerselect::Div1024
214    }
215}
216#[doc = "Field `PRESCALER` writer - Prescaler"]
217pub type PrescalerW<'a, REG> = crate::FieldWriter<'a, REG, 4, Prescalerselect>;
218impl<'a, REG> PrescalerW<'a, REG>
219where
220    REG: crate::Writable + crate::RegisterSpec,
221    REG::Ux: From<u8>,
222{
223    #[doc = "CLK_RTC_CNT = GCLK_RTC/1"]
224    #[inline(always)]
225    pub fn off(self) -> &'a mut crate::W<REG> {
226        self.variant(Prescalerselect::Off)
227    }
228    #[doc = "CLK_RTC_CNT = GCLK_RTC/1"]
229    #[inline(always)]
230    pub fn div1(self) -> &'a mut crate::W<REG> {
231        self.variant(Prescalerselect::Div1)
232    }
233    #[doc = "CLK_RTC_CNT = GCLK_RTC/2"]
234    #[inline(always)]
235    pub fn div2(self) -> &'a mut crate::W<REG> {
236        self.variant(Prescalerselect::Div2)
237    }
238    #[doc = "CLK_RTC_CNT = GCLK_RTC/4"]
239    #[inline(always)]
240    pub fn div4(self) -> &'a mut crate::W<REG> {
241        self.variant(Prescalerselect::Div4)
242    }
243    #[doc = "CLK_RTC_CNT = GCLK_RTC/8"]
244    #[inline(always)]
245    pub fn div8(self) -> &'a mut crate::W<REG> {
246        self.variant(Prescalerselect::Div8)
247    }
248    #[doc = "CLK_RTC_CNT = GCLK_RTC/16"]
249    #[inline(always)]
250    pub fn div16(self) -> &'a mut crate::W<REG> {
251        self.variant(Prescalerselect::Div16)
252    }
253    #[doc = "CLK_RTC_CNT = GCLK_RTC/32"]
254    #[inline(always)]
255    pub fn div32(self) -> &'a mut crate::W<REG> {
256        self.variant(Prescalerselect::Div32)
257    }
258    #[doc = "CLK_RTC_CNT = GCLK_RTC/64"]
259    #[inline(always)]
260    pub fn div64(self) -> &'a mut crate::W<REG> {
261        self.variant(Prescalerselect::Div64)
262    }
263    #[doc = "CLK_RTC_CNT = GCLK_RTC/128"]
264    #[inline(always)]
265    pub fn div128(self) -> &'a mut crate::W<REG> {
266        self.variant(Prescalerselect::Div128)
267    }
268    #[doc = "CLK_RTC_CNT = GCLK_RTC/256"]
269    #[inline(always)]
270    pub fn div256(self) -> &'a mut crate::W<REG> {
271        self.variant(Prescalerselect::Div256)
272    }
273    #[doc = "CLK_RTC_CNT = GCLK_RTC/512"]
274    #[inline(always)]
275    pub fn div512(self) -> &'a mut crate::W<REG> {
276        self.variant(Prescalerselect::Div512)
277    }
278    #[doc = "CLK_RTC_CNT = GCLK_RTC/1024"]
279    #[inline(always)]
280    pub fn div1024(self) -> &'a mut crate::W<REG> {
281        self.variant(Prescalerselect::Div1024)
282    }
283}
284#[doc = "Field `BKTRST` reader - BKUP Registers Reset On Tamper Enable"]
285pub type BktrstR = crate::BitReader;
286#[doc = "Field `BKTRST` writer - BKUP Registers Reset On Tamper Enable"]
287pub type BktrstW<'a, REG> = crate::BitWriter<'a, REG>;
288#[doc = "Field `GPTRST` reader - GP Registers Reset On Tamper Enable"]
289pub type GptrstR = crate::BitReader;
290#[doc = "Field `GPTRST` writer - GP Registers Reset On Tamper Enable"]
291pub type GptrstW<'a, REG> = crate::BitWriter<'a, REG>;
292#[doc = "Field `CLOCKSYNC` reader - Clock Read Synchronization Enable"]
293pub type ClocksyncR = crate::BitReader;
294#[doc = "Field `CLOCKSYNC` writer - Clock Read Synchronization Enable"]
295pub type ClocksyncW<'a, REG> = crate::BitWriter<'a, REG>;
296impl R {
297    #[doc = "Bit 0 - Software Reset"]
298    #[inline(always)]
299    pub fn swrst(&self) -> SwrstR {
300        SwrstR::new((self.bits & 1) != 0)
301    }
302    #[doc = "Bit 1 - Enable"]
303    #[inline(always)]
304    pub fn enable(&self) -> EnableR {
305        EnableR::new(((self.bits >> 1) & 1) != 0)
306    }
307    #[doc = "Bits 2:3 - Operating Mode"]
308    #[inline(always)]
309    pub fn mode(&self) -> ModeR {
310        ModeR::new(((self.bits >> 2) & 3) as u8)
311    }
312    #[doc = "Bit 6 - Clock Representation"]
313    #[inline(always)]
314    pub fn clkrep(&self) -> ClkrepR {
315        ClkrepR::new(((self.bits >> 6) & 1) != 0)
316    }
317    #[doc = "Bit 7 - Clear on Match"]
318    #[inline(always)]
319    pub fn matchclr(&self) -> MatchclrR {
320        MatchclrR::new(((self.bits >> 7) & 1) != 0)
321    }
322    #[doc = "Bits 8:11 - Prescaler"]
323    #[inline(always)]
324    pub fn prescaler(&self) -> PrescalerR {
325        PrescalerR::new(((self.bits >> 8) & 0x0f) as u8)
326    }
327    #[doc = "Bit 13 - BKUP Registers Reset On Tamper Enable"]
328    #[inline(always)]
329    pub fn bktrst(&self) -> BktrstR {
330        BktrstR::new(((self.bits >> 13) & 1) != 0)
331    }
332    #[doc = "Bit 14 - GP Registers Reset On Tamper Enable"]
333    #[inline(always)]
334    pub fn gptrst(&self) -> GptrstR {
335        GptrstR::new(((self.bits >> 14) & 1) != 0)
336    }
337    #[doc = "Bit 15 - Clock Read Synchronization Enable"]
338    #[inline(always)]
339    pub fn clocksync(&self) -> ClocksyncR {
340        ClocksyncR::new(((self.bits >> 15) & 1) != 0)
341    }
342}
343impl W {
344    #[doc = "Bit 0 - Software Reset"]
345    #[inline(always)]
346    #[must_use]
347    pub fn swrst(&mut self) -> SwrstW<CtrlaSpec> {
348        SwrstW::new(self, 0)
349    }
350    #[doc = "Bit 1 - Enable"]
351    #[inline(always)]
352    #[must_use]
353    pub fn enable(&mut self) -> EnableW<CtrlaSpec> {
354        EnableW::new(self, 1)
355    }
356    #[doc = "Bits 2:3 - Operating Mode"]
357    #[inline(always)]
358    #[must_use]
359    pub fn mode(&mut self) -> ModeW<CtrlaSpec> {
360        ModeW::new(self, 2)
361    }
362    #[doc = "Bit 6 - Clock Representation"]
363    #[inline(always)]
364    #[must_use]
365    pub fn clkrep(&mut self) -> ClkrepW<CtrlaSpec> {
366        ClkrepW::new(self, 6)
367    }
368    #[doc = "Bit 7 - Clear on Match"]
369    #[inline(always)]
370    #[must_use]
371    pub fn matchclr(&mut self) -> MatchclrW<CtrlaSpec> {
372        MatchclrW::new(self, 7)
373    }
374    #[doc = "Bits 8:11 - Prescaler"]
375    #[inline(always)]
376    #[must_use]
377    pub fn prescaler(&mut self) -> PrescalerW<CtrlaSpec> {
378        PrescalerW::new(self, 8)
379    }
380    #[doc = "Bit 13 - BKUP Registers Reset On Tamper Enable"]
381    #[inline(always)]
382    #[must_use]
383    pub fn bktrst(&mut self) -> BktrstW<CtrlaSpec> {
384        BktrstW::new(self, 13)
385    }
386    #[doc = "Bit 14 - GP Registers Reset On Tamper Enable"]
387    #[inline(always)]
388    #[must_use]
389    pub fn gptrst(&mut self) -> GptrstW<CtrlaSpec> {
390        GptrstW::new(self, 14)
391    }
392    #[doc = "Bit 15 - Clock Read Synchronization Enable"]
393    #[inline(always)]
394    #[must_use]
395    pub fn clocksync(&mut self) -> ClocksyncW<CtrlaSpec> {
396        ClocksyncW::new(self, 15)
397    }
398}
399#[doc = "MODE2 Control A\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrla::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrla::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
400pub struct CtrlaSpec;
401impl crate::RegisterSpec for CtrlaSpec {
402    type Ux = u16;
403}
404#[doc = "`read()` method returns [`ctrla::R`](R) reader structure"]
405impl crate::Readable for CtrlaSpec {}
406#[doc = "`write(|w| ..)` method takes [`ctrla::W`](W) writer structure"]
407impl crate::Writable for CtrlaSpec {
408    type Safety = crate::Unsafe;
409    const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
410    const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
411}
412#[doc = "`reset()` method sets CTRLA to value 0"]
413impl crate::Resettable for CtrlaSpec {
414    const RESET_VALUE: u16 = 0;
415}
atsamd51p/rtc/mode2/ctrla.rs

atsamd51p/rtc/mode2/
ctrla.rs
