atsamd51p/sdhc0/
hc1r_emmc_mode.rs

1#[doc = "Register `HC1R_EMMC_MODE` reader"]
2pub type R = crate::R<Hc1rEmmcModeSpec>;
3#[doc = "Register `HC1R_EMMC_MODE` writer"]
4pub type W = crate::W<Hc1rEmmcModeSpec>;
5#[doc = "Data Width\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7pub enum Dwselect {
8    #[doc = "0: 1-bit mode"]
9    _1bit = 0,
10    #[doc = "1: 4-bit mode"]
11    _4bit = 1,
12}
13impl From<Dwselect> for bool {
14    #[inline(always)]
15    fn from(variant: Dwselect) -> Self {
16        variant as u8 != 0
17    }
18}
19#[doc = "Field `DW` reader - Data Width"]
20pub type DwR = crate::BitReader<Dwselect>;
21impl DwR {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> Dwselect {
25        match self.bits {
26            false => Dwselect::_1bit,
27            true => Dwselect::_4bit,
28        }
29    }
30    #[doc = "1-bit mode"]
31    #[inline(always)]
32    pub fn is_1bit(&self) -> bool {
33        *self == Dwselect::_1bit
34    }
35    #[doc = "4-bit mode"]
36    #[inline(always)]
37    pub fn is_4bit(&self) -> bool {
38        *self == Dwselect::_4bit
39    }
40}
41#[doc = "Field `DW` writer - Data Width"]
42pub type DwW<'a, REG> = crate::BitWriter<'a, REG, Dwselect>;
43impl<'a, REG> DwW<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "1-bit mode"]
48    #[inline(always)]
49    pub fn _1bit(self) -> &'a mut crate::W<REG> {
50        self.variant(Dwselect::_1bit)
51    }
52    #[doc = "4-bit mode"]
53    #[inline(always)]
54    pub fn _4bit(self) -> &'a mut crate::W<REG> {
55        self.variant(Dwselect::_4bit)
56    }
57}
58#[doc = "High Speed Enable\n\nValue on reset: 0"]
59#[derive(Clone, Copy, Debug, PartialEq, Eq)]
60pub enum Hsenselect {
61    #[doc = "0: Normal Speed mode"]
62    Normal = 0,
63    #[doc = "1: High Speed mode"]
64    High = 1,
65}
66impl From<Hsenselect> for bool {
67    #[inline(always)]
68    fn from(variant: Hsenselect) -> Self {
69        variant as u8 != 0
70    }
71}
72#[doc = "Field `HSEN` reader - High Speed Enable"]
73pub type HsenR = crate::BitReader<Hsenselect>;
74impl HsenR {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> Hsenselect {
78        match self.bits {
79            false => Hsenselect::Normal,
80            true => Hsenselect::High,
81        }
82    }
83    #[doc = "Normal Speed mode"]
84    #[inline(always)]
85    pub fn is_normal(&self) -> bool {
86        *self == Hsenselect::Normal
87    }
88    #[doc = "High Speed mode"]
89    #[inline(always)]
90    pub fn is_high(&self) -> bool {
91        *self == Hsenselect::High
92    }
93}
94#[doc = "Field `HSEN` writer - High Speed Enable"]
95pub type HsenW<'a, REG> = crate::BitWriter<'a, REG, Hsenselect>;
96impl<'a, REG> HsenW<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "Normal Speed mode"]
101    #[inline(always)]
102    pub fn normal(self) -> &'a mut crate::W<REG> {
103        self.variant(Hsenselect::Normal)
104    }
105    #[doc = "High Speed mode"]
106    #[inline(always)]
107    pub fn high(self) -> &'a mut crate::W<REG> {
108        self.variant(Hsenselect::High)
109    }
110}
111#[doc = "DMA Select\n\nValue on reset: 0"]
112#[derive(Clone, Copy, Debug, PartialEq, Eq)]
113#[repr(u8)]
114pub enum Dmaselselect {
115    #[doc = "0: SDMA is selected"]
116    Sdma = 0,
117    #[doc = "2: 32-bit Address ADMA2 is selected"]
118    _32bit = 2,
119}
120impl From<Dmaselselect> for u8 {
121    #[inline(always)]
122    fn from(variant: Dmaselselect) -> Self {
123        variant as _
124    }
125}
126impl crate::FieldSpec for Dmaselselect {
127    type Ux = u8;
128}
129impl crate::IsEnum for Dmaselselect {}
130#[doc = "Field `DMASEL` reader - DMA Select"]
131pub type DmaselR = crate::FieldReader<Dmaselselect>;
132impl DmaselR {
133    #[doc = "Get enumerated values variant"]
134    #[inline(always)]
135    pub const fn variant(&self) -> Option<Dmaselselect> {
136        match self.bits {
137            0 => Some(Dmaselselect::Sdma),
138            2 => Some(Dmaselselect::_32bit),
139            _ => None,
140        }
141    }
142    #[doc = "SDMA is selected"]
143    #[inline(always)]
144    pub fn is_sdma(&self) -> bool {
145        *self == Dmaselselect::Sdma
146    }
147    #[doc = "32-bit Address ADMA2 is selected"]
148    #[inline(always)]
149    pub fn is_32bit(&self) -> bool {
150        *self == Dmaselselect::_32bit
151    }
152}
153#[doc = "Field `DMASEL` writer - DMA Select"]
154pub type DmaselW<'a, REG> = crate::FieldWriter<'a, REG, 2, Dmaselselect>;
155impl<'a, REG> DmaselW<'a, REG>
156where
157    REG: crate::Writable + crate::RegisterSpec,
158    REG::Ux: From<u8>,
159{
160    #[doc = "SDMA is selected"]
161    #[inline(always)]
162    pub fn sdma(self) -> &'a mut crate::W<REG> {
163        self.variant(Dmaselselect::Sdma)
164    }
165    #[doc = "32-bit Address ADMA2 is selected"]
166    #[inline(always)]
167    pub fn _32bit(self) -> &'a mut crate::W<REG> {
168        self.variant(Dmaselselect::_32bit)
169    }
170}
171impl R {
172    #[doc = "Bit 1 - Data Width"]
173    #[inline(always)]
174    pub fn dw(&self) -> DwR {
175        DwR::new(((self.bits >> 1) & 1) != 0)
176    }
177    #[doc = "Bit 2 - High Speed Enable"]
178    #[inline(always)]
179    pub fn hsen(&self) -> HsenR {
180        HsenR::new(((self.bits >> 2) & 1) != 0)
181    }
182    #[doc = "Bits 3:4 - DMA Select"]
183    #[inline(always)]
184    pub fn dmasel(&self) -> DmaselR {
185        DmaselR::new((self.bits >> 3) & 3)
186    }
187}
188impl W {
189    #[doc = "Bit 1 - Data Width"]
190    #[inline(always)]
191    #[must_use]
192    pub fn dw(&mut self) -> DwW<Hc1rEmmcModeSpec> {
193        DwW::new(self, 1)
194    }
195    #[doc = "Bit 2 - High Speed Enable"]
196    #[inline(always)]
197    #[must_use]
198    pub fn hsen(&mut self) -> HsenW<Hc1rEmmcModeSpec> {
199        HsenW::new(self, 2)
200    }
201    #[doc = "Bits 3:4 - DMA Select"]
202    #[inline(always)]
203    #[must_use]
204    pub fn dmasel(&mut self) -> DmaselW<Hc1rEmmcModeSpec> {
205        DmaselW::new(self, 3)
206    }
207}
208#[doc = "Host Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`hc1r_emmc_mode::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hc1r_emmc_mode::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
209pub struct Hc1rEmmcModeSpec;
210impl crate::RegisterSpec for Hc1rEmmcModeSpec {
211    type Ux = u8;
212}
213#[doc = "`read()` method returns [`hc1r_emmc_mode::R`](R) reader structure"]
214impl crate::Readable for Hc1rEmmcModeSpec {}
215#[doc = "`write(|w| ..)` method takes [`hc1r_emmc_mode::W`](W) writer structure"]
216impl crate::Writable for Hc1rEmmcModeSpec {
217    type Safety = crate::Unsafe;
218    const ZERO_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
219    const ONE_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
220}
221#[doc = "`reset()` method sets HC1R_EMMC_MODE to value 0"]
222impl crate::Resettable for Hc1rEmmcModeSpec {
223    const RESET_VALUE: u8 = 0;
224}
atsamd51p/sdhc0/hc1r_emmc_mode.rs

atsamd51p/sdhc0/
hc1r_emmc_mode.rs
