atsamd51p/sercom0/i2cm/
intenclr.rs

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1#[doc = "Register `INTENCLR` reader"]
2pub type R = crate::R<IntenclrSpec>;
3#[doc = "Register `INTENCLR` writer"]
4pub type W = crate::W<IntenclrSpec>;
5#[doc = "Field `MB` reader - Master On Bus Interrupt Disable"]
6pub type MbR = crate::BitReader;
7#[doc = "Field `MB` writer - Master On Bus Interrupt Disable"]
8pub type MbW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `SB` reader - Slave On Bus Interrupt Disable"]
10pub type SbR = crate::BitReader;
11#[doc = "Field `SB` writer - Slave On Bus Interrupt Disable"]
12pub type SbW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"]
14pub type ErrorR = crate::BitReader;
15#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"]
16pub type ErrorW<'a, REG> = crate::BitWriter<'a, REG>;
17impl R {
18    #[doc = "Bit 0 - Master On Bus Interrupt Disable"]
19    #[inline(always)]
20    pub fn mb(&self) -> MbR {
21        MbR::new((self.bits & 1) != 0)
22    }
23    #[doc = "Bit 1 - Slave On Bus Interrupt Disable"]
24    #[inline(always)]
25    pub fn sb(&self) -> SbR {
26        SbR::new(((self.bits >> 1) & 1) != 0)
27    }
28    #[doc = "Bit 7 - Combined Error Interrupt Disable"]
29    #[inline(always)]
30    pub fn error(&self) -> ErrorR {
31        ErrorR::new(((self.bits >> 7) & 1) != 0)
32    }
33}
34impl W {
35    #[doc = "Bit 0 - Master On Bus Interrupt Disable"]
36    #[inline(always)]
37    #[must_use]
38    pub fn mb(&mut self) -> MbW<IntenclrSpec> {
39        MbW::new(self, 0)
40    }
41    #[doc = "Bit 1 - Slave On Bus Interrupt Disable"]
42    #[inline(always)]
43    #[must_use]
44    pub fn sb(&mut self) -> SbW<IntenclrSpec> {
45        SbW::new(self, 1)
46    }
47    #[doc = "Bit 7 - Combined Error Interrupt Disable"]
48    #[inline(always)]
49    #[must_use]
50    pub fn error(&mut self) -> ErrorW<IntenclrSpec> {
51        ErrorW::new(self, 7)
52    }
53}
54#[doc = "I2CM Interrupt Enable Clear\n\nYou can [`read`](crate::Reg::read) this register and get [`intenclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intenclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
55pub struct IntenclrSpec;
56impl crate::RegisterSpec for IntenclrSpec {
57    type Ux = u8;
58}
59#[doc = "`read()` method returns [`intenclr::R`](R) reader structure"]
60impl crate::Readable for IntenclrSpec {}
61#[doc = "`write(|w| ..)` method takes [`intenclr::W`](W) writer structure"]
62impl crate::Writable for IntenclrSpec {
63    type Safety = crate::Unsafe;
64    const ZERO_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
65    const ONE_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
66}
67#[doc = "`reset()` method sets INTENCLR to value 0"]
68impl crate::Resettable for IntenclrSpec {
69    const RESET_VALUE: u8 = 0;
70}
atsamd51p/sercom0/i2cm/intenclr.rs

atsamd51p/sercom0/i2cm/
intenclr.rs
