atsamd51p/oscctrl/
status.rs

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1#[doc = "Register `STATUS` reader"]
2pub type R = crate::R<StatusSpec>;
3#[doc = "Field `XOSCRDY0` reader - XOSC 0 Ready"]
4pub type Xoscrdy0R = crate::BitReader;
5#[doc = "Field `XOSCRDY1` reader - XOSC 1 Ready"]
6pub type Xoscrdy1R = crate::BitReader;
7#[doc = "Field `XOSCFAIL0` reader - XOSC 0 Clock Failure Detector"]
8pub type Xoscfail0R = crate::BitReader;
9#[doc = "Field `XOSCFAIL1` reader - XOSC 1 Clock Failure Detector"]
10pub type Xoscfail1R = crate::BitReader;
11#[doc = "Field `XOSCCKSW0` reader - XOSC 0 Clock Switch"]
12pub type Xosccksw0R = crate::BitReader;
13#[doc = "Field `XOSCCKSW1` reader - XOSC 1 Clock Switch"]
14pub type Xosccksw1R = crate::BitReader;
15#[doc = "Field `DFLLRDY` reader - DFLL Ready"]
16pub type DfllrdyR = crate::BitReader;
17#[doc = "Field `DFLLOOB` reader - DFLL Out Of Bounds"]
18pub type DflloobR = crate::BitReader;
19#[doc = "Field `DFLLLCKF` reader - DFLL Lock Fine"]
20pub type DflllckfR = crate::BitReader;
21#[doc = "Field `DFLLLCKC` reader - DFLL Lock Coarse"]
22pub type DflllckcR = crate::BitReader;
23#[doc = "Field `DFLLRCS` reader - DFLL Reference Clock Stopped"]
24pub type DfllrcsR = crate::BitReader;
25#[doc = "Field `DPLL0LCKR` reader - DPLL0 Lock Rise"]
26pub type Dpll0lckrR = crate::BitReader;
27#[doc = "Field `DPLL0LCKF` reader - DPLL0 Lock Fall"]
28pub type Dpll0lckfR = crate::BitReader;
29#[doc = "Field `DPLL0TO` reader - DPLL0 Timeout"]
30pub type Dpll0toR = crate::BitReader;
31#[doc = "Field `DPLL0LDRTO` reader - DPLL0 Loop Divider Ratio Update Complete"]
32pub type Dpll0ldrtoR = crate::BitReader;
33#[doc = "Field `DPLL1LCKR` reader - DPLL1 Lock Rise"]
34pub type Dpll1lckrR = crate::BitReader;
35#[doc = "Field `DPLL1LCKF` reader - DPLL1 Lock Fall"]
36pub type Dpll1lckfR = crate::BitReader;
37#[doc = "Field `DPLL1TO` reader - DPLL1 Timeout"]
38pub type Dpll1toR = crate::BitReader;
39#[doc = "Field `DPLL1LDRTO` reader - DPLL1 Loop Divider Ratio Update Complete"]
40pub type Dpll1ldrtoR = crate::BitReader;
41impl R {
42    #[doc = "Bit 0 - XOSC 0 Ready"]
43    #[inline(always)]
44    pub fn xoscrdy0(&self) -> Xoscrdy0R {
45        Xoscrdy0R::new((self.bits & 1) != 0)
46    }
47    #[doc = "Bit 1 - XOSC 1 Ready"]
48    #[inline(always)]
49    pub fn xoscrdy1(&self) -> Xoscrdy1R {
50        Xoscrdy1R::new(((self.bits >> 1) & 1) != 0)
51    }
52    #[doc = "Bit 2 - XOSC 0 Clock Failure Detector"]
53    #[inline(always)]
54    pub fn xoscfail0(&self) -> Xoscfail0R {
55        Xoscfail0R::new(((self.bits >> 2) & 1) != 0)
56    }
57    #[doc = "Bit 3 - XOSC 1 Clock Failure Detector"]
58    #[inline(always)]
59    pub fn xoscfail1(&self) -> Xoscfail1R {
60        Xoscfail1R::new(((self.bits >> 3) & 1) != 0)
61    }
62    #[doc = "Bit 4 - XOSC 0 Clock Switch"]
63    #[inline(always)]
64    pub fn xosccksw0(&self) -> Xosccksw0R {
65        Xosccksw0R::new(((self.bits >> 4) & 1) != 0)
66    }
67    #[doc = "Bit 5 - XOSC 1 Clock Switch"]
68    #[inline(always)]
69    pub fn xosccksw1(&self) -> Xosccksw1R {
70        Xosccksw1R::new(((self.bits >> 5) & 1) != 0)
71    }
72    #[doc = "Bit 8 - DFLL Ready"]
73    #[inline(always)]
74    pub fn dfllrdy(&self) -> DfllrdyR {
75        DfllrdyR::new(((self.bits >> 8) & 1) != 0)
76    }
77    #[doc = "Bit 9 - DFLL Out Of Bounds"]
78    #[inline(always)]
79    pub fn dflloob(&self) -> DflloobR {
80        DflloobR::new(((self.bits >> 9) & 1) != 0)
81    }
82    #[doc = "Bit 10 - DFLL Lock Fine"]
83    #[inline(always)]
84    pub fn dflllckf(&self) -> DflllckfR {
85        DflllckfR::new(((self.bits >> 10) & 1) != 0)
86    }
87    #[doc = "Bit 11 - DFLL Lock Coarse"]
88    #[inline(always)]
89    pub fn dflllckc(&self) -> DflllckcR {
90        DflllckcR::new(((self.bits >> 11) & 1) != 0)
91    }
92    #[doc = "Bit 12 - DFLL Reference Clock Stopped"]
93    #[inline(always)]
94    pub fn dfllrcs(&self) -> DfllrcsR {
95        DfllrcsR::new(((self.bits >> 12) & 1) != 0)
96    }
97    #[doc = "Bit 16 - DPLL0 Lock Rise"]
98    #[inline(always)]
99    pub fn dpll0lckr(&self) -> Dpll0lckrR {
100        Dpll0lckrR::new(((self.bits >> 16) & 1) != 0)
101    }
102    #[doc = "Bit 17 - DPLL0 Lock Fall"]
103    #[inline(always)]
104    pub fn dpll0lckf(&self) -> Dpll0lckfR {
105        Dpll0lckfR::new(((self.bits >> 17) & 1) != 0)
106    }
107    #[doc = "Bit 18 - DPLL0 Timeout"]
108    #[inline(always)]
109    pub fn dpll0to(&self) -> Dpll0toR {
110        Dpll0toR::new(((self.bits >> 18) & 1) != 0)
111    }
112    #[doc = "Bit 19 - DPLL0 Loop Divider Ratio Update Complete"]
113    #[inline(always)]
114    pub fn dpll0ldrto(&self) -> Dpll0ldrtoR {
115        Dpll0ldrtoR::new(((self.bits >> 19) & 1) != 0)
116    }
117    #[doc = "Bit 24 - DPLL1 Lock Rise"]
118    #[inline(always)]
119    pub fn dpll1lckr(&self) -> Dpll1lckrR {
120        Dpll1lckrR::new(((self.bits >> 24) & 1) != 0)
121    }
122    #[doc = "Bit 25 - DPLL1 Lock Fall"]
123    #[inline(always)]
124    pub fn dpll1lckf(&self) -> Dpll1lckfR {
125        Dpll1lckfR::new(((self.bits >> 25) & 1) != 0)
126    }
127    #[doc = "Bit 26 - DPLL1 Timeout"]
128    #[inline(always)]
129    pub fn dpll1to(&self) -> Dpll1toR {
130        Dpll1toR::new(((self.bits >> 26) & 1) != 0)
131    }
132    #[doc = "Bit 27 - DPLL1 Loop Divider Ratio Update Complete"]
133    #[inline(always)]
134    pub fn dpll1ldrto(&self) -> Dpll1ldrtoR {
135        Dpll1ldrtoR::new(((self.bits >> 27) & 1) != 0)
136    }
137}
138#[doc = "Status\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
139pub struct StatusSpec;
140impl crate::RegisterSpec for StatusSpec {
141    type Ux = u32;
142}
143#[doc = "`read()` method returns [`status::R`](R) reader structure"]
144impl crate::Readable for StatusSpec {}
145#[doc = "`reset()` method sets STATUS to value 0"]
146impl crate::Resettable for StatusSpec {
147    const RESET_VALUE: u32 = 0;
148}
atsamd51p/oscctrl/status.rs

atsamd51p/oscctrl/
status.rs
