atsamd51p/system_control/
icsr.rs

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1#[doc = "Register `ICSR` reader"]
2pub type R = crate::R<IcsrSpec>;
3#[doc = "Register `ICSR` writer"]
4pub type W = crate::W<IcsrSpec>;
5#[doc = "Field `VECTACTIVE` reader - Active exception number"]
6pub type VectactiveR = crate::FieldReader<u16>;
7#[doc = "Field `VECTACTIVE` writer - Active exception number"]
8pub type VectactiveW<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
9#[doc = "Field `RETTOBASE` reader - No preempted active exceptions to execute"]
10pub type RettobaseR = crate::BitReader;
11#[doc = "Field `RETTOBASE` writer - No preempted active exceptions to execute"]
12pub type RettobaseW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `VECTPENDING` reader - Exception number of the highest priority pending enabled exception"]
14pub type VectpendingR = crate::FieldReader;
15#[doc = "Field `VECTPENDING` writer - Exception number of the highest priority pending enabled exception"]
16pub type VectpendingW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
17#[doc = "Field `ISRPENDING` reader - Interrupt pending flag"]
18pub type IsrpendingR = crate::BitReader;
19#[doc = "Field `ISRPENDING` writer - Interrupt pending flag"]
20pub type IsrpendingW<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `ISRPREEMPT` reader - Debug only"]
22pub type IsrpreemptR = crate::BitReader;
23#[doc = "Field `ISRPREEMPT` writer - Debug only"]
24pub type IsrpreemptW<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "SysTick clear-pending bit\n\nValue on reset: 0"]
26#[derive(Clone, Copy, Debug, PartialEq, Eq)]
27pub enum Pendstclrselect {
28    #[doc = "0: No effect"]
29    Value0 = 0,
30    #[doc = "1: Removes the pending state from the SysTick exception"]
31    Value1 = 1,
32}
33impl From<Pendstclrselect> for bool {
34    #[inline(always)]
35    fn from(variant: Pendstclrselect) -> Self {
36        variant as u8 != 0
37    }
38}
39#[doc = "Field `PENDSTCLR` reader - SysTick clear-pending bit"]
40pub type PendstclrR = crate::BitReader<Pendstclrselect>;
41impl PendstclrR {
42    #[doc = "Get enumerated values variant"]
43    #[inline(always)]
44    pub const fn variant(&self) -> Pendstclrselect {
45        match self.bits {
46            false => Pendstclrselect::Value0,
47            true => Pendstclrselect::Value1,
48        }
49    }
50    #[doc = "No effect"]
51    #[inline(always)]
52    pub fn is_value_0(&self) -> bool {
53        *self == Pendstclrselect::Value0
54    }
55    #[doc = "Removes the pending state from the SysTick exception"]
56    #[inline(always)]
57    pub fn is_value_1(&self) -> bool {
58        *self == Pendstclrselect::Value1
59    }
60}
61#[doc = "Field `PENDSTCLR` writer - SysTick clear-pending bit"]
62pub type PendstclrW<'a, REG> = crate::BitWriter<'a, REG, Pendstclrselect>;
63impl<'a, REG> PendstclrW<'a, REG>
64where
65    REG: crate::Writable + crate::RegisterSpec,
66{
67    #[doc = "No effect"]
68    #[inline(always)]
69    pub fn value_0(self) -> &'a mut crate::W<REG> {
70        self.variant(Pendstclrselect::Value0)
71    }
72    #[doc = "Removes the pending state from the SysTick exception"]
73    #[inline(always)]
74    pub fn value_1(self) -> &'a mut crate::W<REG> {
75        self.variant(Pendstclrselect::Value1)
76    }
77}
78#[doc = "SysTick set-pending bit\n\nValue on reset: 0"]
79#[derive(Clone, Copy, Debug, PartialEq, Eq)]
80pub enum Pendstsetselect {
81    #[doc = "0: Write: no effect; read: SysTick exception is not pending"]
82    Value0 = 0,
83    #[doc = "1: Write: changes SysTick exception state to pending; read: SysTick exception is pending"]
84    Value1 = 1,
85}
86impl From<Pendstsetselect> for bool {
87    #[inline(always)]
88    fn from(variant: Pendstsetselect) -> Self {
89        variant as u8 != 0
90    }
91}
92#[doc = "Field `PENDSTSET` reader - SysTick set-pending bit"]
93pub type PendstsetR = crate::BitReader<Pendstsetselect>;
94impl PendstsetR {
95    #[doc = "Get enumerated values variant"]
96    #[inline(always)]
97    pub const fn variant(&self) -> Pendstsetselect {
98        match self.bits {
99            false => Pendstsetselect::Value0,
100            true => Pendstsetselect::Value1,
101        }
102    }
103    #[doc = "Write: no effect; read: SysTick exception is not pending"]
104    #[inline(always)]
105    pub fn is_value_0(&self) -> bool {
106        *self == Pendstsetselect::Value0
107    }
108    #[doc = "Write: changes SysTick exception state to pending; read: SysTick exception is pending"]
109    #[inline(always)]
110    pub fn is_value_1(&self) -> bool {
111        *self == Pendstsetselect::Value1
112    }
113}
114#[doc = "Field `PENDSTSET` writer - SysTick set-pending bit"]
115pub type PendstsetW<'a, REG> = crate::BitWriter<'a, REG, Pendstsetselect>;
116impl<'a, REG> PendstsetW<'a, REG>
117where
118    REG: crate::Writable + crate::RegisterSpec,
119{
120    #[doc = "Write: no effect; read: SysTick exception is not pending"]
121    #[inline(always)]
122    pub fn value_0(self) -> &'a mut crate::W<REG> {
123        self.variant(Pendstsetselect::Value0)
124    }
125    #[doc = "Write: changes SysTick exception state to pending; read: SysTick exception is pending"]
126    #[inline(always)]
127    pub fn value_1(self) -> &'a mut crate::W<REG> {
128        self.variant(Pendstsetselect::Value1)
129    }
130}
131#[doc = "PendSV clear-pending bit\n\nValue on reset: 0"]
132#[derive(Clone, Copy, Debug, PartialEq, Eq)]
133pub enum Pendsvclrselect {
134    #[doc = "0: No effect"]
135    Value0 = 0,
136    #[doc = "1: Removes the pending state from the PendSV exception"]
137    Value1 = 1,
138}
139impl From<Pendsvclrselect> for bool {
140    #[inline(always)]
141    fn from(variant: Pendsvclrselect) -> Self {
142        variant as u8 != 0
143    }
144}
145#[doc = "Field `PENDSVCLR` reader - PendSV clear-pending bit"]
146pub type PendsvclrR = crate::BitReader<Pendsvclrselect>;
147impl PendsvclrR {
148    #[doc = "Get enumerated values variant"]
149    #[inline(always)]
150    pub const fn variant(&self) -> Pendsvclrselect {
151        match self.bits {
152            false => Pendsvclrselect::Value0,
153            true => Pendsvclrselect::Value1,
154        }
155    }
156    #[doc = "No effect"]
157    #[inline(always)]
158    pub fn is_value_0(&self) -> bool {
159        *self == Pendsvclrselect::Value0
160    }
161    #[doc = "Removes the pending state from the PendSV exception"]
162    #[inline(always)]
163    pub fn is_value_1(&self) -> bool {
164        *self == Pendsvclrselect::Value1
165    }
166}
167#[doc = "Field `PENDSVCLR` writer - PendSV clear-pending bit"]
168pub type PendsvclrW<'a, REG> = crate::BitWriter<'a, REG, Pendsvclrselect>;
169impl<'a, REG> PendsvclrW<'a, REG>
170where
171    REG: crate::Writable + crate::RegisterSpec,
172{
173    #[doc = "No effect"]
174    #[inline(always)]
175    pub fn value_0(self) -> &'a mut crate::W<REG> {
176        self.variant(Pendsvclrselect::Value0)
177    }
178    #[doc = "Removes the pending state from the PendSV exception"]
179    #[inline(always)]
180    pub fn value_1(self) -> &'a mut crate::W<REG> {
181        self.variant(Pendsvclrselect::Value1)
182    }
183}
184#[doc = "PendSV set-pending bit\n\nValue on reset: 0"]
185#[derive(Clone, Copy, Debug, PartialEq, Eq)]
186pub enum Pendsvsetselect {
187    #[doc = "0: Write: no effect; read: PendSV exception is not pending"]
188    Value0 = 0,
189    #[doc = "1: Write: changes PendSV exception state to pending; read: PendSV exception is pending"]
190    Value1 = 1,
191}
192impl From<Pendsvsetselect> for bool {
193    #[inline(always)]
194    fn from(variant: Pendsvsetselect) -> Self {
195        variant as u8 != 0
196    }
197}
198#[doc = "Field `PENDSVSET` reader - PendSV set-pending bit"]
199pub type PendsvsetR = crate::BitReader<Pendsvsetselect>;
200impl PendsvsetR {
201    #[doc = "Get enumerated values variant"]
202    #[inline(always)]
203    pub const fn variant(&self) -> Pendsvsetselect {
204        match self.bits {
205            false => Pendsvsetselect::Value0,
206            true => Pendsvsetselect::Value1,
207        }
208    }
209    #[doc = "Write: no effect; read: PendSV exception is not pending"]
210    #[inline(always)]
211    pub fn is_value_0(&self) -> bool {
212        *self == Pendsvsetselect::Value0
213    }
214    #[doc = "Write: changes PendSV exception state to pending; read: PendSV exception is pending"]
215    #[inline(always)]
216    pub fn is_value_1(&self) -> bool {
217        *self == Pendsvsetselect::Value1
218    }
219}
220#[doc = "Field `PENDSVSET` writer - PendSV set-pending bit"]
221pub type PendsvsetW<'a, REG> = crate::BitWriter<'a, REG, Pendsvsetselect>;
222impl<'a, REG> PendsvsetW<'a, REG>
223where
224    REG: crate::Writable + crate::RegisterSpec,
225{
226    #[doc = "Write: no effect; read: PendSV exception is not pending"]
227    #[inline(always)]
228    pub fn value_0(self) -> &'a mut crate::W<REG> {
229        self.variant(Pendsvsetselect::Value0)
230    }
231    #[doc = "Write: changes PendSV exception state to pending; read: PendSV exception is pending"]
232    #[inline(always)]
233    pub fn value_1(self) -> &'a mut crate::W<REG> {
234        self.variant(Pendsvsetselect::Value1)
235    }
236}
237#[doc = "NMI set-pending bit\n\nValue on reset: 0"]
238#[derive(Clone, Copy, Debug, PartialEq, Eq)]
239pub enum Nmipendsetselect {
240    #[doc = "0: Write: no effect; read: NMI exception is not pending"]
241    Value0 = 0,
242    #[doc = "1: Write: changes NMI exception state to pending; read: NMI exception is pending"]
243    Value1 = 1,
244}
245impl From<Nmipendsetselect> for bool {
246    #[inline(always)]
247    fn from(variant: Nmipendsetselect) -> Self {
248        variant as u8 != 0
249    }
250}
251#[doc = "Field `NMIPENDSET` reader - NMI set-pending bit"]
252pub type NmipendsetR = crate::BitReader<Nmipendsetselect>;
253impl NmipendsetR {
254    #[doc = "Get enumerated values variant"]
255    #[inline(always)]
256    pub const fn variant(&self) -> Nmipendsetselect {
257        match self.bits {
258            false => Nmipendsetselect::Value0,
259            true => Nmipendsetselect::Value1,
260        }
261    }
262    #[doc = "Write: no effect; read: NMI exception is not pending"]
263    #[inline(always)]
264    pub fn is_value_0(&self) -> bool {
265        *self == Nmipendsetselect::Value0
266    }
267    #[doc = "Write: changes NMI exception state to pending; read: NMI exception is pending"]
268    #[inline(always)]
269    pub fn is_value_1(&self) -> bool {
270        *self == Nmipendsetselect::Value1
271    }
272}
273#[doc = "Field `NMIPENDSET` writer - NMI set-pending bit"]
274pub type NmipendsetW<'a, REG> = crate::BitWriter<'a, REG, Nmipendsetselect>;
275impl<'a, REG> NmipendsetW<'a, REG>
276where
277    REG: crate::Writable + crate::RegisterSpec,
278{
279    #[doc = "Write: no effect; read: NMI exception is not pending"]
280    #[inline(always)]
281    pub fn value_0(self) -> &'a mut crate::W<REG> {
282        self.variant(Nmipendsetselect::Value0)
283    }
284    #[doc = "Write: changes NMI exception state to pending; read: NMI exception is pending"]
285    #[inline(always)]
286    pub fn value_1(self) -> &'a mut crate::W<REG> {
287        self.variant(Nmipendsetselect::Value1)
288    }
289}
290impl R {
291    #[doc = "Bits 0:8 - Active exception number"]
292    #[inline(always)]
293    pub fn vectactive(&self) -> VectactiveR {
294        VectactiveR::new((self.bits & 0x01ff) as u16)
295    }
296    #[doc = "Bit 11 - No preempted active exceptions to execute"]
297    #[inline(always)]
298    pub fn rettobase(&self) -> RettobaseR {
299        RettobaseR::new(((self.bits >> 11) & 1) != 0)
300    }
301    #[doc = "Bits 12:17 - Exception number of the highest priority pending enabled exception"]
302    #[inline(always)]
303    pub fn vectpending(&self) -> VectpendingR {
304        VectpendingR::new(((self.bits >> 12) & 0x3f) as u8)
305    }
306    #[doc = "Bit 22 - Interrupt pending flag"]
307    #[inline(always)]
308    pub fn isrpending(&self) -> IsrpendingR {
309        IsrpendingR::new(((self.bits >> 22) & 1) != 0)
310    }
311    #[doc = "Bit 23 - Debug only"]
312    #[inline(always)]
313    pub fn isrpreempt(&self) -> IsrpreemptR {
314        IsrpreemptR::new(((self.bits >> 23) & 1) != 0)
315    }
316    #[doc = "Bit 25 - SysTick clear-pending bit"]
317    #[inline(always)]
318    pub fn pendstclr(&self) -> PendstclrR {
319        PendstclrR::new(((self.bits >> 25) & 1) != 0)
320    }
321    #[doc = "Bit 26 - SysTick set-pending bit"]
322    #[inline(always)]
323    pub fn pendstset(&self) -> PendstsetR {
324        PendstsetR::new(((self.bits >> 26) & 1) != 0)
325    }
326    #[doc = "Bit 27 - PendSV clear-pending bit"]
327    #[inline(always)]
328    pub fn pendsvclr(&self) -> PendsvclrR {
329        PendsvclrR::new(((self.bits >> 27) & 1) != 0)
330    }
331    #[doc = "Bit 28 - PendSV set-pending bit"]
332    #[inline(always)]
333    pub fn pendsvset(&self) -> PendsvsetR {
334        PendsvsetR::new(((self.bits >> 28) & 1) != 0)
335    }
336    #[doc = "Bit 31 - NMI set-pending bit"]
337    #[inline(always)]
338    pub fn nmipendset(&self) -> NmipendsetR {
339        NmipendsetR::new(((self.bits >> 31) & 1) != 0)
340    }
341}
342impl W {
343    #[doc = "Bits 0:8 - Active exception number"]
344    #[inline(always)]
345    #[must_use]
346    pub fn vectactive(&mut self) -> VectactiveW<IcsrSpec> {
347        VectactiveW::new(self, 0)
348    }
349    #[doc = "Bit 11 - No preempted active exceptions to execute"]
350    #[inline(always)]
351    #[must_use]
352    pub fn rettobase(&mut self) -> RettobaseW<IcsrSpec> {
353        RettobaseW::new(self, 11)
354    }
355    #[doc = "Bits 12:17 - Exception number of the highest priority pending enabled exception"]
356    #[inline(always)]
357    #[must_use]
358    pub fn vectpending(&mut self) -> VectpendingW<IcsrSpec> {
359        VectpendingW::new(self, 12)
360    }
361    #[doc = "Bit 22 - Interrupt pending flag"]
362    #[inline(always)]
363    #[must_use]
364    pub fn isrpending(&mut self) -> IsrpendingW<IcsrSpec> {
365        IsrpendingW::new(self, 22)
366    }
367    #[doc = "Bit 23 - Debug only"]
368    #[inline(always)]
369    #[must_use]
370    pub fn isrpreempt(&mut self) -> IsrpreemptW<IcsrSpec> {
371        IsrpreemptW::new(self, 23)
372    }
373    #[doc = "Bit 25 - SysTick clear-pending bit"]
374    #[inline(always)]
375    #[must_use]
376    pub fn pendstclr(&mut self) -> PendstclrW<IcsrSpec> {
377        PendstclrW::new(self, 25)
378    }
379    #[doc = "Bit 26 - SysTick set-pending bit"]
380    #[inline(always)]
381    #[must_use]
382    pub fn pendstset(&mut self) -> PendstsetW<IcsrSpec> {
383        PendstsetW::new(self, 26)
384    }
385    #[doc = "Bit 27 - PendSV clear-pending bit"]
386    #[inline(always)]
387    #[must_use]
388    pub fn pendsvclr(&mut self) -> PendsvclrW<IcsrSpec> {
389        PendsvclrW::new(self, 27)
390    }
391    #[doc = "Bit 28 - PendSV set-pending bit"]
392    #[inline(always)]
393    #[must_use]
394    pub fn pendsvset(&mut self) -> PendsvsetW<IcsrSpec> {
395        PendsvsetW::new(self, 28)
396    }
397    #[doc = "Bit 31 - NMI set-pending bit"]
398    #[inline(always)]
399    #[must_use]
400    pub fn nmipendset(&mut self) -> NmipendsetW<IcsrSpec> {
401        NmipendsetW::new(self, 31)
402    }
403}
404#[doc = "Interrupt Control and State Register\n\nYou can [`read`](crate::Reg::read) this register and get [`icsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
405pub struct IcsrSpec;
406impl crate::RegisterSpec for IcsrSpec {
407    type Ux = u32;
408}
409#[doc = "`read()` method returns [`icsr::R`](R) reader structure"]
410impl crate::Readable for IcsrSpec {}
411#[doc = "`write(|w| ..)` method takes [`icsr::W`](W) writer structure"]
412impl crate::Writable for IcsrSpec {
413    type Safety = crate::Unsafe;
414    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
415    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
416}
417#[doc = "`reset()` method sets ICSR to value 0"]
418impl crate::Resettable for IcsrSpec {
419    const RESET_VALUE: u32 = 0;
420}
atsamd51p/system_control/icsr.rs

atsamd51p/system_control/
icsr.rs
