atsamd51p/qspi/
ctrlb.rs

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1#[doc = "Register `CTRLB` reader"]
2pub type R = crate::R<CtrlbSpec>;
3#[doc = "Register `CTRLB` writer"]
4pub type W = crate::W<CtrlbSpec>;
5#[doc = "Serial Memory Mode\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7pub enum Modeselect {
8    #[doc = "0: SPI operating mode"]
9    Spi = 0,
10    #[doc = "1: Serial Memory operating mode"]
11    Memory = 1,
12}
13impl From<Modeselect> for bool {
14    #[inline(always)]
15    fn from(variant: Modeselect) -> Self {
16        variant as u8 != 0
17    }
18}
19#[doc = "Field `MODE` reader - Serial Memory Mode"]
20pub type ModeR = crate::BitReader<Modeselect>;
21impl ModeR {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> Modeselect {
25        match self.bits {
26            false => Modeselect::Spi,
27            true => Modeselect::Memory,
28        }
29    }
30    #[doc = "SPI operating mode"]
31    #[inline(always)]
32    pub fn is_spi(&self) -> bool {
33        *self == Modeselect::Spi
34    }
35    #[doc = "Serial Memory operating mode"]
36    #[inline(always)]
37    pub fn is_memory(&self) -> bool {
38        *self == Modeselect::Memory
39    }
40}
41#[doc = "Field `MODE` writer - Serial Memory Mode"]
42pub type ModeW<'a, REG> = crate::BitWriter<'a, REG, Modeselect>;
43impl<'a, REG> ModeW<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "SPI operating mode"]
48    #[inline(always)]
49    pub fn spi(self) -> &'a mut crate::W<REG> {
50        self.variant(Modeselect::Spi)
51    }
52    #[doc = "Serial Memory operating mode"]
53    #[inline(always)]
54    pub fn memory(self) -> &'a mut crate::W<REG> {
55        self.variant(Modeselect::Memory)
56    }
57}
58#[doc = "Local Loopback Enable\n\nValue on reset: 0"]
59#[derive(Clone, Copy, Debug, PartialEq, Eq)]
60pub enum Loopenselect {
61    #[doc = "0: Local Loopback is disabled"]
62    Disabled = 0,
63    #[doc = "1: Local Loopback is enabled"]
64    Enabled = 1,
65}
66impl From<Loopenselect> for bool {
67    #[inline(always)]
68    fn from(variant: Loopenselect) -> Self {
69        variant as u8 != 0
70    }
71}
72#[doc = "Field `LOOPEN` reader - Local Loopback Enable"]
73pub type LoopenR = crate::BitReader<Loopenselect>;
74impl LoopenR {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> Loopenselect {
78        match self.bits {
79            false => Loopenselect::Disabled,
80            true => Loopenselect::Enabled,
81        }
82    }
83    #[doc = "Local Loopback is disabled"]
84    #[inline(always)]
85    pub fn is_disabled(&self) -> bool {
86        *self == Loopenselect::Disabled
87    }
88    #[doc = "Local Loopback is enabled"]
89    #[inline(always)]
90    pub fn is_enabled(&self) -> bool {
91        *self == Loopenselect::Enabled
92    }
93}
94#[doc = "Field `LOOPEN` writer - Local Loopback Enable"]
95pub type LoopenW<'a, REG> = crate::BitWriter<'a, REG, Loopenselect>;
96impl<'a, REG> LoopenW<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "Local Loopback is disabled"]
101    #[inline(always)]
102    pub fn disabled(self) -> &'a mut crate::W<REG> {
103        self.variant(Loopenselect::Disabled)
104    }
105    #[doc = "Local Loopback is enabled"]
106    #[inline(always)]
107    pub fn enabled(self) -> &'a mut crate::W<REG> {
108        self.variant(Loopenselect::Enabled)
109    }
110}
111#[doc = "Field `WDRBT` reader - Wait Data Read Before Transfer"]
112pub type WdrbtR = crate::BitReader;
113#[doc = "Field `WDRBT` writer - Wait Data Read Before Transfer"]
114pub type WdrbtW<'a, REG> = crate::BitWriter<'a, REG>;
115#[doc = "Field `SMEMREG` reader - Serial Memory reg"]
116pub type SmemregR = crate::BitReader;
117#[doc = "Field `SMEMREG` writer - Serial Memory reg"]
118pub type SmemregW<'a, REG> = crate::BitWriter<'a, REG>;
119#[doc = "Chip Select Mode\n\nValue on reset: 0"]
120#[derive(Clone, Copy, Debug, PartialEq, Eq)]
121#[repr(u8)]
122pub enum Csmodeselect {
123    #[doc = "0: The chip select is deasserted if TD has not been reloaded before the end of the current transfer."]
124    Noreload = 0,
125    #[doc = "1: The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in TD has been transferred."]
126    Lastxfer = 1,
127    #[doc = "2: The chip select is deasserted systematically after each transfer."]
128    Systematically = 2,
129}
130impl From<Csmodeselect> for u8 {
131    #[inline(always)]
132    fn from(variant: Csmodeselect) -> Self {
133        variant as _
134    }
135}
136impl crate::FieldSpec for Csmodeselect {
137    type Ux = u8;
138}
139impl crate::IsEnum for Csmodeselect {}
140#[doc = "Field `CSMODE` reader - Chip Select Mode"]
141pub type CsmodeR = crate::FieldReader<Csmodeselect>;
142impl CsmodeR {
143    #[doc = "Get enumerated values variant"]
144    #[inline(always)]
145    pub const fn variant(&self) -> Option<Csmodeselect> {
146        match self.bits {
147            0 => Some(Csmodeselect::Noreload),
148            1 => Some(Csmodeselect::Lastxfer),
149            2 => Some(Csmodeselect::Systematically),
150            _ => None,
151        }
152    }
153    #[doc = "The chip select is deasserted if TD has not been reloaded before the end of the current transfer."]
154    #[inline(always)]
155    pub fn is_noreload(&self) -> bool {
156        *self == Csmodeselect::Noreload
157    }
158    #[doc = "The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in TD has been transferred."]
159    #[inline(always)]
160    pub fn is_lastxfer(&self) -> bool {
161        *self == Csmodeselect::Lastxfer
162    }
163    #[doc = "The chip select is deasserted systematically after each transfer."]
164    #[inline(always)]
165    pub fn is_systematically(&self) -> bool {
166        *self == Csmodeselect::Systematically
167    }
168}
169#[doc = "Field `CSMODE` writer - Chip Select Mode"]
170pub type CsmodeW<'a, REG> = crate::FieldWriter<'a, REG, 2, Csmodeselect>;
171impl<'a, REG> CsmodeW<'a, REG>
172where
173    REG: crate::Writable + crate::RegisterSpec,
174    REG::Ux: From<u8>,
175{
176    #[doc = "The chip select is deasserted if TD has not been reloaded before the end of the current transfer."]
177    #[inline(always)]
178    pub fn noreload(self) -> &'a mut crate::W<REG> {
179        self.variant(Csmodeselect::Noreload)
180    }
181    #[doc = "The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in TD has been transferred."]
182    #[inline(always)]
183    pub fn lastxfer(self) -> &'a mut crate::W<REG> {
184        self.variant(Csmodeselect::Lastxfer)
185    }
186    #[doc = "The chip select is deasserted systematically after each transfer."]
187    #[inline(always)]
188    pub fn systematically(self) -> &'a mut crate::W<REG> {
189        self.variant(Csmodeselect::Systematically)
190    }
191}
192#[doc = "Data Length\n\nValue on reset: 0"]
193#[derive(Clone, Copy, Debug, PartialEq, Eq)]
194#[repr(u8)]
195pub enum Datalenselect {
196    #[doc = "0: 8-bits transfer"]
197    _8bits = 0,
198    #[doc = "1: 9 bits transfer"]
199    _9bits = 1,
200    #[doc = "2: 10-bits transfer"]
201    _10bits = 2,
202    #[doc = "3: 11-bits transfer"]
203    _11bits = 3,
204    #[doc = "4: 12-bits transfer"]
205    _12bits = 4,
206    #[doc = "5: 13-bits transfer"]
207    _13bits = 5,
208    #[doc = "6: 14-bits transfer"]
209    _14bits = 6,
210    #[doc = "7: 15-bits transfer"]
211    _15bits = 7,
212    #[doc = "8: 16-bits transfer"]
213    _16bits = 8,
214}
215impl From<Datalenselect> for u8 {
216    #[inline(always)]
217    fn from(variant: Datalenselect) -> Self {
218        variant as _
219    }
220}
221impl crate::FieldSpec for Datalenselect {
222    type Ux = u8;
223}
224impl crate::IsEnum for Datalenselect {}
225#[doc = "Field `DATALEN` reader - Data Length"]
226pub type DatalenR = crate::FieldReader<Datalenselect>;
227impl DatalenR {
228    #[doc = "Get enumerated values variant"]
229    #[inline(always)]
230    pub const fn variant(&self) -> Option<Datalenselect> {
231        match self.bits {
232            0 => Some(Datalenselect::_8bits),
233            1 => Some(Datalenselect::_9bits),
234            2 => Some(Datalenselect::_10bits),
235            3 => Some(Datalenselect::_11bits),
236            4 => Some(Datalenselect::_12bits),
237            5 => Some(Datalenselect::_13bits),
238            6 => Some(Datalenselect::_14bits),
239            7 => Some(Datalenselect::_15bits),
240            8 => Some(Datalenselect::_16bits),
241            _ => None,
242        }
243    }
244    #[doc = "8-bits transfer"]
245    #[inline(always)]
246    pub fn is_8bits(&self) -> bool {
247        *self == Datalenselect::_8bits
248    }
249    #[doc = "9 bits transfer"]
250    #[inline(always)]
251    pub fn is_9bits(&self) -> bool {
252        *self == Datalenselect::_9bits
253    }
254    #[doc = "10-bits transfer"]
255    #[inline(always)]
256    pub fn is_10bits(&self) -> bool {
257        *self == Datalenselect::_10bits
258    }
259    #[doc = "11-bits transfer"]
260    #[inline(always)]
261    pub fn is_11bits(&self) -> bool {
262        *self == Datalenselect::_11bits
263    }
264    #[doc = "12-bits transfer"]
265    #[inline(always)]
266    pub fn is_12bits(&self) -> bool {
267        *self == Datalenselect::_12bits
268    }
269    #[doc = "13-bits transfer"]
270    #[inline(always)]
271    pub fn is_13bits(&self) -> bool {
272        *self == Datalenselect::_13bits
273    }
274    #[doc = "14-bits transfer"]
275    #[inline(always)]
276    pub fn is_14bits(&self) -> bool {
277        *self == Datalenselect::_14bits
278    }
279    #[doc = "15-bits transfer"]
280    #[inline(always)]
281    pub fn is_15bits(&self) -> bool {
282        *self == Datalenselect::_15bits
283    }
284    #[doc = "16-bits transfer"]
285    #[inline(always)]
286    pub fn is_16bits(&self) -> bool {
287        *self == Datalenselect::_16bits
288    }
289}
290#[doc = "Field `DATALEN` writer - Data Length"]
291pub type DatalenW<'a, REG> = crate::FieldWriter<'a, REG, 4, Datalenselect>;
292impl<'a, REG> DatalenW<'a, REG>
293where
294    REG: crate::Writable + crate::RegisterSpec,
295    REG::Ux: From<u8>,
296{
297    #[doc = "8-bits transfer"]
298    #[inline(always)]
299    pub fn _8bits(self) -> &'a mut crate::W<REG> {
300        self.variant(Datalenselect::_8bits)
301    }
302    #[doc = "9 bits transfer"]
303    #[inline(always)]
304    pub fn _9bits(self) -> &'a mut crate::W<REG> {
305        self.variant(Datalenselect::_9bits)
306    }
307    #[doc = "10-bits transfer"]
308    #[inline(always)]
309    pub fn _10bits(self) -> &'a mut crate::W<REG> {
310        self.variant(Datalenselect::_10bits)
311    }
312    #[doc = "11-bits transfer"]
313    #[inline(always)]
314    pub fn _11bits(self) -> &'a mut crate::W<REG> {
315        self.variant(Datalenselect::_11bits)
316    }
317    #[doc = "12-bits transfer"]
318    #[inline(always)]
319    pub fn _12bits(self) -> &'a mut crate::W<REG> {
320        self.variant(Datalenselect::_12bits)
321    }
322    #[doc = "13-bits transfer"]
323    #[inline(always)]
324    pub fn _13bits(self) -> &'a mut crate::W<REG> {
325        self.variant(Datalenselect::_13bits)
326    }
327    #[doc = "14-bits transfer"]
328    #[inline(always)]
329    pub fn _14bits(self) -> &'a mut crate::W<REG> {
330        self.variant(Datalenselect::_14bits)
331    }
332    #[doc = "15-bits transfer"]
333    #[inline(always)]
334    pub fn _15bits(self) -> &'a mut crate::W<REG> {
335        self.variant(Datalenselect::_15bits)
336    }
337    #[doc = "16-bits transfer"]
338    #[inline(always)]
339    pub fn _16bits(self) -> &'a mut crate::W<REG> {
340        self.variant(Datalenselect::_16bits)
341    }
342}
343#[doc = "Field `DLYBCT` reader - Delay Between Consecutive Transfers"]
344pub type DlybctR = crate::FieldReader;
345#[doc = "Field `DLYBCT` writer - Delay Between Consecutive Transfers"]
346pub type DlybctW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
347#[doc = "Field `DLYCS` reader - Minimum Inactive CS Delay"]
348pub type DlycsR = crate::FieldReader;
349#[doc = "Field `DLYCS` writer - Minimum Inactive CS Delay"]
350pub type DlycsW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
351impl R {
352    #[doc = "Bit 0 - Serial Memory Mode"]
353    #[inline(always)]
354    pub fn mode(&self) -> ModeR {
355        ModeR::new((self.bits & 1) != 0)
356    }
357    #[doc = "Bit 1 - Local Loopback Enable"]
358    #[inline(always)]
359    pub fn loopen(&self) -> LoopenR {
360        LoopenR::new(((self.bits >> 1) & 1) != 0)
361    }
362    #[doc = "Bit 2 - Wait Data Read Before Transfer"]
363    #[inline(always)]
364    pub fn wdrbt(&self) -> WdrbtR {
365        WdrbtR::new(((self.bits >> 2) & 1) != 0)
366    }
367    #[doc = "Bit 3 - Serial Memory reg"]
368    #[inline(always)]
369    pub fn smemreg(&self) -> SmemregR {
370        SmemregR::new(((self.bits >> 3) & 1) != 0)
371    }
372    #[doc = "Bits 4:5 - Chip Select Mode"]
373    #[inline(always)]
374    pub fn csmode(&self) -> CsmodeR {
375        CsmodeR::new(((self.bits >> 4) & 3) as u8)
376    }
377    #[doc = "Bits 8:11 - Data Length"]
378    #[inline(always)]
379    pub fn datalen(&self) -> DatalenR {
380        DatalenR::new(((self.bits >> 8) & 0x0f) as u8)
381    }
382    #[doc = "Bits 16:23 - Delay Between Consecutive Transfers"]
383    #[inline(always)]
384    pub fn dlybct(&self) -> DlybctR {
385        DlybctR::new(((self.bits >> 16) & 0xff) as u8)
386    }
387    #[doc = "Bits 24:31 - Minimum Inactive CS Delay"]
388    #[inline(always)]
389    pub fn dlycs(&self) -> DlycsR {
390        DlycsR::new(((self.bits >> 24) & 0xff) as u8)
391    }
392}
393impl W {
394    #[doc = "Bit 0 - Serial Memory Mode"]
395    #[inline(always)]
396    #[must_use]
397    pub fn mode(&mut self) -> ModeW<CtrlbSpec> {
398        ModeW::new(self, 0)
399    }
400    #[doc = "Bit 1 - Local Loopback Enable"]
401    #[inline(always)]
402    #[must_use]
403    pub fn loopen(&mut self) -> LoopenW<CtrlbSpec> {
404        LoopenW::new(self, 1)
405    }
406    #[doc = "Bit 2 - Wait Data Read Before Transfer"]
407    #[inline(always)]
408    #[must_use]
409    pub fn wdrbt(&mut self) -> WdrbtW<CtrlbSpec> {
410        WdrbtW::new(self, 2)
411    }
412    #[doc = "Bit 3 - Serial Memory reg"]
413    #[inline(always)]
414    #[must_use]
415    pub fn smemreg(&mut self) -> SmemregW<CtrlbSpec> {
416        SmemregW::new(self, 3)
417    }
418    #[doc = "Bits 4:5 - Chip Select Mode"]
419    #[inline(always)]
420    #[must_use]
421    pub fn csmode(&mut self) -> CsmodeW<CtrlbSpec> {
422        CsmodeW::new(self, 4)
423    }
424    #[doc = "Bits 8:11 - Data Length"]
425    #[inline(always)]
426    #[must_use]
427    pub fn datalen(&mut self) -> DatalenW<CtrlbSpec> {
428        DatalenW::new(self, 8)
429    }
430    #[doc = "Bits 16:23 - Delay Between Consecutive Transfers"]
431    #[inline(always)]
432    #[must_use]
433    pub fn dlybct(&mut self) -> DlybctW<CtrlbSpec> {
434        DlybctW::new(self, 16)
435    }
436    #[doc = "Bits 24:31 - Minimum Inactive CS Delay"]
437    #[inline(always)]
438    #[must_use]
439    pub fn dlycs(&mut self) -> DlycsW<CtrlbSpec> {
440        DlycsW::new(self, 24)
441    }
442}
443#[doc = "Control B\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrlb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrlb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
444pub struct CtrlbSpec;
445impl crate::RegisterSpec for CtrlbSpec {
446    type Ux = u32;
447}
448#[doc = "`read()` method returns [`ctrlb::R`](R) reader structure"]
449impl crate::Readable for CtrlbSpec {}
450#[doc = "`write(|w| ..)` method takes [`ctrlb::W`](W) writer structure"]
451impl crate::Writable for CtrlbSpec {
452    type Safety = crate::Unsafe;
453    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
454    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
455}
456#[doc = "`reset()` method sets CTRLB to value 0"]
457impl crate::Resettable for CtrlbSpec {
458    const RESET_VALUE: u32 = 0;
459}
atsamd51p/qspi/ctrlb.rs

atsamd51p/qspi/
ctrlb.rs
