atsamd51p/pcc/
mr.rs

Help
1#[doc = "Register `MR` reader"]
2pub type R = crate::R<MrSpec>;
3#[doc = "Register `MR` writer"]
4pub type W = crate::W<MrSpec>;
5#[doc = "Field `PCEN` reader - Parallel Capture Enable"]
6pub type PcenR = crate::BitReader;
7#[doc = "Field `PCEN` writer - Parallel Capture Enable"]
8pub type PcenW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Data size\n\nValue on reset: 0"]
10#[derive(Clone, Copy, Debug, PartialEq, Eq)]
11#[repr(u8)]
12pub enum Dsizeselect {
13    #[doc = "0: 1 data is read in the PCC_RHR"]
14    _1data = 0,
15    #[doc = "1: 2 data is read in the PCC_RHR"]
16    _2data = 1,
17    #[doc = "2: 4 data are read in the PCC_RHR (only for 8 bits data size, ISIZE = 0)"]
18    _4data = 2,
19}
20impl From<Dsizeselect> for u8 {
21    #[inline(always)]
22    fn from(variant: Dsizeselect) -> Self {
23        variant as _
24    }
25}
26impl crate::FieldSpec for Dsizeselect {
27    type Ux = u8;
28}
29impl crate::IsEnum for Dsizeselect {}
30#[doc = "Field `DSIZE` reader - Data size"]
31pub type DsizeR = crate::FieldReader<Dsizeselect>;
32impl DsizeR {
33    #[doc = "Get enumerated values variant"]
34    #[inline(always)]
35    pub const fn variant(&self) -> Option<Dsizeselect> {
36        match self.bits {
37            0 => Some(Dsizeselect::_1data),
38            1 => Some(Dsizeselect::_2data),
39            2 => Some(Dsizeselect::_4data),
40            _ => None,
41        }
42    }
43    #[doc = "1 data is read in the PCC_RHR"]
44    #[inline(always)]
45    pub fn is_1data(&self) -> bool {
46        *self == Dsizeselect::_1data
47    }
48    #[doc = "2 data is read in the PCC_RHR"]
49    #[inline(always)]
50    pub fn is_2data(&self) -> bool {
51        *self == Dsizeselect::_2data
52    }
53    #[doc = "4 data are read in the PCC_RHR (only for 8 bits data size, ISIZE = 0)"]
54    #[inline(always)]
55    pub fn is_4data(&self) -> bool {
56        *self == Dsizeselect::_4data
57    }
58}
59#[doc = "Field `DSIZE` writer - Data size"]
60pub type DsizeW<'a, REG> = crate::FieldWriter<'a, REG, 2, Dsizeselect>;
61impl<'a, REG> DsizeW<'a, REG>
62where
63    REG: crate::Writable + crate::RegisterSpec,
64    REG::Ux: From<u8>,
65{
66    #[doc = "1 data is read in the PCC_RHR"]
67    #[inline(always)]
68    pub fn _1data(self) -> &'a mut crate::W<REG> {
69        self.variant(Dsizeselect::_1data)
70    }
71    #[doc = "2 data is read in the PCC_RHR"]
72    #[inline(always)]
73    pub fn _2data(self) -> &'a mut crate::W<REG> {
74        self.variant(Dsizeselect::_2data)
75    }
76    #[doc = "4 data are read in the PCC_RHR (only for 8 bits data size, ISIZE = 0)"]
77    #[inline(always)]
78    pub fn _4data(self) -> &'a mut crate::W<REG> {
79        self.variant(Dsizeselect::_4data)
80    }
81}
82#[doc = "Field `SCALE` reader - Scale data"]
83pub type ScaleR = crate::BitReader;
84#[doc = "Field `SCALE` writer - Scale data"]
85pub type ScaleW<'a, REG> = crate::BitWriter<'a, REG>;
86#[doc = "Field `ALWYS` reader - Always Sampling"]
87pub type AlwysR = crate::BitReader;
88#[doc = "Field `ALWYS` writer - Always Sampling"]
89pub type AlwysW<'a, REG> = crate::BitWriter<'a, REG>;
90#[doc = "Field `HALFS` reader - Half Sampling"]
91pub type HalfsR = crate::BitReader;
92#[doc = "Field `HALFS` writer - Half Sampling"]
93pub type HalfsW<'a, REG> = crate::BitWriter<'a, REG>;
94#[doc = "Field `FRSTS` reader - First sample"]
95pub type FrstsR = crate::BitReader;
96#[doc = "Field `FRSTS` writer - First sample"]
97pub type FrstsW<'a, REG> = crate::BitWriter<'a, REG>;
98#[doc = "Input Data Size\n\nValue on reset: 0"]
99#[derive(Clone, Copy, Debug, PartialEq, Eq)]
100#[repr(u8)]
101pub enum Isizeselect {
102    #[doc = "0: Input data bus size is 8 bits"]
103    _8bits = 0,
104    #[doc = "1: Input data bus size is 10 bits"]
105    _10bits = 1,
106    #[doc = "2: Input data bus size is 12 bits"]
107    _12bits = 2,
108    #[doc = "3: Input data bus size is 14 bits"]
109    _14bits = 3,
110}
111impl From<Isizeselect> for u8 {
112    #[inline(always)]
113    fn from(variant: Isizeselect) -> Self {
114        variant as _
115    }
116}
117impl crate::FieldSpec for Isizeselect {
118    type Ux = u8;
119}
120impl crate::IsEnum for Isizeselect {}
121#[doc = "Field `ISIZE` reader - Input Data Size"]
122pub type IsizeR = crate::FieldReader<Isizeselect>;
123impl IsizeR {
124    #[doc = "Get enumerated values variant"]
125    #[inline(always)]
126    pub const fn variant(&self) -> Option<Isizeselect> {
127        match self.bits {
128            0 => Some(Isizeselect::_8bits),
129            1 => Some(Isizeselect::_10bits),
130            2 => Some(Isizeselect::_12bits),
131            3 => Some(Isizeselect::_14bits),
132            _ => None,
133        }
134    }
135    #[doc = "Input data bus size is 8 bits"]
136    #[inline(always)]
137    pub fn is_8bits(&self) -> bool {
138        *self == Isizeselect::_8bits
139    }
140    #[doc = "Input data bus size is 10 bits"]
141    #[inline(always)]
142    pub fn is_10bits(&self) -> bool {
143        *self == Isizeselect::_10bits
144    }
145    #[doc = "Input data bus size is 12 bits"]
146    #[inline(always)]
147    pub fn is_12bits(&self) -> bool {
148        *self == Isizeselect::_12bits
149    }
150    #[doc = "Input data bus size is 14 bits"]
151    #[inline(always)]
152    pub fn is_14bits(&self) -> bool {
153        *self == Isizeselect::_14bits
154    }
155}
156#[doc = "Field `ISIZE` writer - Input Data Size"]
157pub type IsizeW<'a, REG> = crate::FieldWriter<'a, REG, 3, Isizeselect>;
158impl<'a, REG> IsizeW<'a, REG>
159where
160    REG: crate::Writable + crate::RegisterSpec,
161    REG::Ux: From<u8>,
162{
163    #[doc = "Input data bus size is 8 bits"]
164    #[inline(always)]
165    pub fn _8bits(self) -> &'a mut crate::W<REG> {
166        self.variant(Isizeselect::_8bits)
167    }
168    #[doc = "Input data bus size is 10 bits"]
169    #[inline(always)]
170    pub fn _10bits(self) -> &'a mut crate::W<REG> {
171        self.variant(Isizeselect::_10bits)
172    }
173    #[doc = "Input data bus size is 12 bits"]
174    #[inline(always)]
175    pub fn _12bits(self) -> &'a mut crate::W<REG> {
176        self.variant(Isizeselect::_12bits)
177    }
178    #[doc = "Input data bus size is 14 bits"]
179    #[inline(always)]
180    pub fn _14bits(self) -> &'a mut crate::W<REG> {
181        self.variant(Isizeselect::_14bits)
182    }
183}
184#[doc = "Field `CID` reader - Clear If Disabled"]
185pub type CidR = crate::FieldReader;
186#[doc = "Field `CID` writer - Clear If Disabled"]
187pub type CidW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
188impl R {
189    #[doc = "Bit 0 - Parallel Capture Enable"]
190    #[inline(always)]
191    pub fn pcen(&self) -> PcenR {
192        PcenR::new((self.bits & 1) != 0)
193    }
194    #[doc = "Bits 4:5 - Data size"]
195    #[inline(always)]
196    pub fn dsize(&self) -> DsizeR {
197        DsizeR::new(((self.bits >> 4) & 3) as u8)
198    }
199    #[doc = "Bit 8 - Scale data"]
200    #[inline(always)]
201    pub fn scale(&self) -> ScaleR {
202        ScaleR::new(((self.bits >> 8) & 1) != 0)
203    }
204    #[doc = "Bit 9 - Always Sampling"]
205    #[inline(always)]
206    pub fn alwys(&self) -> AlwysR {
207        AlwysR::new(((self.bits >> 9) & 1) != 0)
208    }
209    #[doc = "Bit 10 - Half Sampling"]
210    #[inline(always)]
211    pub fn halfs(&self) -> HalfsR {
212        HalfsR::new(((self.bits >> 10) & 1) != 0)
213    }
214    #[doc = "Bit 11 - First sample"]
215    #[inline(always)]
216    pub fn frsts(&self) -> FrstsR {
217        FrstsR::new(((self.bits >> 11) & 1) != 0)
218    }
219    #[doc = "Bits 16:18 - Input Data Size"]
220    #[inline(always)]
221    pub fn isize(&self) -> IsizeR {
222        IsizeR::new(((self.bits >> 16) & 7) as u8)
223    }
224    #[doc = "Bits 30:31 - Clear If Disabled"]
225    #[inline(always)]
226    pub fn cid(&self) -> CidR {
227        CidR::new(((self.bits >> 30) & 3) as u8)
228    }
229}
230impl W {
231    #[doc = "Bit 0 - Parallel Capture Enable"]
232    #[inline(always)]
233    #[must_use]
234    pub fn pcen(&mut self) -> PcenW<MrSpec> {
235        PcenW::new(self, 0)
236    }
237    #[doc = "Bits 4:5 - Data size"]
238    #[inline(always)]
239    #[must_use]
240    pub fn dsize(&mut self) -> DsizeW<MrSpec> {
241        DsizeW::new(self, 4)
242    }
243    #[doc = "Bit 8 - Scale data"]
244    #[inline(always)]
245    #[must_use]
246    pub fn scale(&mut self) -> ScaleW<MrSpec> {
247        ScaleW::new(self, 8)
248    }
249    #[doc = "Bit 9 - Always Sampling"]
250    #[inline(always)]
251    #[must_use]
252    pub fn alwys(&mut self) -> AlwysW<MrSpec> {
253        AlwysW::new(self, 9)
254    }
255    #[doc = "Bit 10 - Half Sampling"]
256    #[inline(always)]
257    #[must_use]
258    pub fn halfs(&mut self) -> HalfsW<MrSpec> {
259        HalfsW::new(self, 10)
260    }
261    #[doc = "Bit 11 - First sample"]
262    #[inline(always)]
263    #[must_use]
264    pub fn frsts(&mut self) -> FrstsW<MrSpec> {
265        FrstsW::new(self, 11)
266    }
267    #[doc = "Bits 16:18 - Input Data Size"]
268    #[inline(always)]
269    #[must_use]
270    pub fn isize(&mut self) -> IsizeW<MrSpec> {
271        IsizeW::new(self, 16)
272    }
273    #[doc = "Bits 30:31 - Clear If Disabled"]
274    #[inline(always)]
275    #[must_use]
276    pub fn cid(&mut self) -> CidW<MrSpec> {
277        CidW::new(self, 30)
278    }
279}
280#[doc = "Mode Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
281pub struct MrSpec;
282impl crate::RegisterSpec for MrSpec {
283    type Ux = u32;
284}
285#[doc = "`read()` method returns [`mr::R`](R) reader structure"]
286impl crate::Readable for MrSpec {}
287#[doc = "`write(|w| ..)` method takes [`mr::W`](W) writer structure"]
288impl crate::Writable for MrSpec {
289    type Safety = crate::Unsafe;
290    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
291    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
292}
293#[doc = "`reset()` method sets MR to value 0"]
294impl crate::Resettable for MrSpec {
295    const RESET_VALUE: u32 = 0;
296}
atsamd51p/pcc/mr.rs

atsamd51p/pcc/
mr.rs
