atsamd11c/usb/device/
epintenset.rs

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1#[doc = "Register `EPINTENSET%s` reader"]
2pub type R = crate::R<EpintensetSpec>;
3#[doc = "Register `EPINTENSET%s` writer"]
4pub type W = crate::W<EpintensetSpec>;
5#[doc = "Field `TRCPT0` reader - Transfer Complete 0 Interrupt Enable"]
6pub type Trcpt0R = crate::BitReader;
7#[doc = "Field `TRCPT0` writer - Transfer Complete 0 Interrupt Enable"]
8pub type Trcpt0W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `TRCPT1` reader - Transfer Complete 1 Interrupt Enable"]
10pub type Trcpt1R = crate::BitReader;
11#[doc = "Field `TRCPT1` writer - Transfer Complete 1 Interrupt Enable"]
12pub type Trcpt1W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `TRFAIL0` reader - Error Flow 0 Interrupt Enable"]
14pub type Trfail0R = crate::BitReader;
15#[doc = "Field `TRFAIL0` writer - Error Flow 0 Interrupt Enable"]
16pub type Trfail0W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `TRFAIL1` reader - Error Flow 1 Interrupt Enable"]
18pub type Trfail1R = crate::BitReader;
19#[doc = "Field `TRFAIL1` writer - Error Flow 1 Interrupt Enable"]
20pub type Trfail1W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `RXSTP` reader - Received Setup Interrupt Enable"]
22pub type RxstpR = crate::BitReader;
23#[doc = "Field `RXSTP` writer - Received Setup Interrupt Enable"]
24pub type RxstpW<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `STALL0` reader - Stall 0 In/out Interrupt enable"]
26pub type Stall0R = crate::BitReader;
27#[doc = "Field `STALL0` writer - Stall 0 In/out Interrupt enable"]
28pub type Stall0W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `STALL1` reader - Stall 1 In/out Interrupt enable"]
30pub type Stall1R = crate::BitReader;
31#[doc = "Field `STALL1` writer - Stall 1 In/out Interrupt enable"]
32pub type Stall1W<'a, REG> = crate::BitWriter<'a, REG>;
33impl R {
34    #[doc = "Bit 0 - Transfer Complete 0 Interrupt Enable"]
35    #[inline(always)]
36    pub fn trcpt0(&self) -> Trcpt0R {
37        Trcpt0R::new((self.bits & 1) != 0)
38    }
39    #[doc = "Bit 1 - Transfer Complete 1 Interrupt Enable"]
40    #[inline(always)]
41    pub fn trcpt1(&self) -> Trcpt1R {
42        Trcpt1R::new(((self.bits >> 1) & 1) != 0)
43    }
44    #[doc = "Bit 2 - Error Flow 0 Interrupt Enable"]
45    #[inline(always)]
46    pub fn trfail0(&self) -> Trfail0R {
47        Trfail0R::new(((self.bits >> 2) & 1) != 0)
48    }
49    #[doc = "Bit 3 - Error Flow 1 Interrupt Enable"]
50    #[inline(always)]
51    pub fn trfail1(&self) -> Trfail1R {
52        Trfail1R::new(((self.bits >> 3) & 1) != 0)
53    }
54    #[doc = "Bit 4 - Received Setup Interrupt Enable"]
55    #[inline(always)]
56    pub fn rxstp(&self) -> RxstpR {
57        RxstpR::new(((self.bits >> 4) & 1) != 0)
58    }
59    #[doc = "Bit 5 - Stall 0 In/out Interrupt enable"]
60    #[inline(always)]
61    pub fn stall0(&self) -> Stall0R {
62        Stall0R::new(((self.bits >> 5) & 1) != 0)
63    }
64    #[doc = "Bit 6 - Stall 1 In/out Interrupt enable"]
65    #[inline(always)]
66    pub fn stall1(&self) -> Stall1R {
67        Stall1R::new(((self.bits >> 6) & 1) != 0)
68    }
69}
70impl W {
71    #[doc = "Bit 0 - Transfer Complete 0 Interrupt Enable"]
72    #[inline(always)]
73    #[must_use]
74    pub fn trcpt0(&mut self) -> Trcpt0W<EpintensetSpec> {
75        Trcpt0W::new(self, 0)
76    }
77    #[doc = "Bit 1 - Transfer Complete 1 Interrupt Enable"]
78    #[inline(always)]
79    #[must_use]
80    pub fn trcpt1(&mut self) -> Trcpt1W<EpintensetSpec> {
81        Trcpt1W::new(self, 1)
82    }
83    #[doc = "Bit 2 - Error Flow 0 Interrupt Enable"]
84    #[inline(always)]
85    #[must_use]
86    pub fn trfail0(&mut self) -> Trfail0W<EpintensetSpec> {
87        Trfail0W::new(self, 2)
88    }
89    #[doc = "Bit 3 - Error Flow 1 Interrupt Enable"]
90    #[inline(always)]
91    #[must_use]
92    pub fn trfail1(&mut self) -> Trfail1W<EpintensetSpec> {
93        Trfail1W::new(self, 3)
94    }
95    #[doc = "Bit 4 - Received Setup Interrupt Enable"]
96    #[inline(always)]
97    #[must_use]
98    pub fn rxstp(&mut self) -> RxstpW<EpintensetSpec> {
99        RxstpW::new(self, 4)
100    }
101    #[doc = "Bit 5 - Stall 0 In/out Interrupt enable"]
102    #[inline(always)]
103    #[must_use]
104    pub fn stall0(&mut self) -> Stall0W<EpintensetSpec> {
105        Stall0W::new(self, 5)
106    }
107    #[doc = "Bit 6 - Stall 1 In/out Interrupt enable"]
108    #[inline(always)]
109    #[must_use]
110    pub fn stall1(&mut self) -> Stall1W<EpintensetSpec> {
111        Stall1W::new(self, 6)
112    }
113}
114#[doc = "DEVICE End Point Interrupt Set Flag\n\nYou can [`read`](crate::Reg::read) this register and get [`epintenset::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`epintenset::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
115pub struct EpintensetSpec;
116impl crate::RegisterSpec for EpintensetSpec {
117    type Ux = u8;
118}
119#[doc = "`read()` method returns [`epintenset::R`](R) reader structure"]
120impl crate::Readable for EpintensetSpec {}
121#[doc = "`write(|w| ..)` method takes [`epintenset::W`](W) writer structure"]
122impl crate::Writable for EpintensetSpec {
123    type Safety = crate::Unsafe;
124    const ZERO_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
125    const ONE_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
126}
127#[doc = "`reset()` method sets EPINTENSET%s to value 0"]
128impl crate::Resettable for EpintensetSpec {
129    const RESET_VALUE: u8 = 0;
130}
atsamd11c/usb/device/epintenset.rs

atsamd11c/usb/device/
epintenset.rs
