atsamd11c/dmac/
intpend.rs

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1#[doc = "Register `INTPEND` reader"]
2pub type R = crate::R<IntpendSpec>;
3#[doc = "Register `INTPEND` writer"]
4pub type W = crate::W<IntpendSpec>;
5#[doc = "Field `ID` reader - Channel ID"]
6pub type IdR = crate::FieldReader;
7#[doc = "Field `ID` writer - Channel ID"]
8pub type IdW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
9#[doc = "Field `TERR` reader - Transfer Error"]
10pub type TerrR = crate::BitReader;
11#[doc = "Field `TERR` writer - Transfer Error"]
12pub type TerrW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `TCMPL` reader - Transfer Complete"]
14pub type TcmplR = crate::BitReader;
15#[doc = "Field `TCMPL` writer - Transfer Complete"]
16pub type TcmplW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `SUSP` reader - Channel Suspend"]
18pub type SuspR = crate::BitReader;
19#[doc = "Field `SUSP` writer - Channel Suspend"]
20pub type SuspW<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `FERR` reader - Fetch Error"]
22pub type FerrR = crate::BitReader;
23#[doc = "Field `BUSY` reader - Busy"]
24pub type BusyR = crate::BitReader;
25#[doc = "Field `PEND` reader - Pending"]
26pub type PendR = crate::BitReader;
27impl R {
28    #[doc = "Bits 0:2 - Channel ID"]
29    #[inline(always)]
30    pub fn id(&self) -> IdR {
31        IdR::new((self.bits & 7) as u8)
32    }
33    #[doc = "Bit 8 - Transfer Error"]
34    #[inline(always)]
35    pub fn terr(&self) -> TerrR {
36        TerrR::new(((self.bits >> 8) & 1) != 0)
37    }
38    #[doc = "Bit 9 - Transfer Complete"]
39    #[inline(always)]
40    pub fn tcmpl(&self) -> TcmplR {
41        TcmplR::new(((self.bits >> 9) & 1) != 0)
42    }
43    #[doc = "Bit 10 - Channel Suspend"]
44    #[inline(always)]
45    pub fn susp(&self) -> SuspR {
46        SuspR::new(((self.bits >> 10) & 1) != 0)
47    }
48    #[doc = "Bit 13 - Fetch Error"]
49    #[inline(always)]
50    pub fn ferr(&self) -> FerrR {
51        FerrR::new(((self.bits >> 13) & 1) != 0)
52    }
53    #[doc = "Bit 14 - Busy"]
54    #[inline(always)]
55    pub fn busy(&self) -> BusyR {
56        BusyR::new(((self.bits >> 14) & 1) != 0)
57    }
58    #[doc = "Bit 15 - Pending"]
59    #[inline(always)]
60    pub fn pend(&self) -> PendR {
61        PendR::new(((self.bits >> 15) & 1) != 0)
62    }
63}
64impl W {
65    #[doc = "Bits 0:2 - Channel ID"]
66    #[inline(always)]
67    #[must_use]
68    pub fn id(&mut self) -> IdW<IntpendSpec> {
69        IdW::new(self, 0)
70    }
71    #[doc = "Bit 8 - Transfer Error"]
72    #[inline(always)]
73    #[must_use]
74    pub fn terr(&mut self) -> TerrW<IntpendSpec> {
75        TerrW::new(self, 8)
76    }
77    #[doc = "Bit 9 - Transfer Complete"]
78    #[inline(always)]
79    #[must_use]
80    pub fn tcmpl(&mut self) -> TcmplW<IntpendSpec> {
81        TcmplW::new(self, 9)
82    }
83    #[doc = "Bit 10 - Channel Suspend"]
84    #[inline(always)]
85    #[must_use]
86    pub fn susp(&mut self) -> SuspW<IntpendSpec> {
87        SuspW::new(self, 10)
88    }
89}
90#[doc = "Interrupt Pending\n\nYou can [`read`](crate::Reg::read) this register and get [`intpend::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intpend::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
91pub struct IntpendSpec;
92impl crate::RegisterSpec for IntpendSpec {
93    type Ux = u16;
94}
95#[doc = "`read()` method returns [`intpend::R`](R) reader structure"]
96impl crate::Readable for IntpendSpec {}
97#[doc = "`write(|w| ..)` method takes [`intpend::W`](W) writer structure"]
98impl crate::Writable for IntpendSpec {
99    type Safety = crate::Unsafe;
100    const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
101    const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
102}
103#[doc = "`reset()` method sets INTPEND to value 0"]
104impl crate::Resettable for IntpendSpec {
105    const RESET_VALUE: u16 = 0;
106}
atsamd11c/dmac/intpend.rs

atsamd11c/dmac/
intpend.rs
