atsamd11c/gclk/
clkctrl.rs

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1#[doc = "Register `CLKCTRL` reader"]
2pub type R = crate::R<ClkctrlSpec>;
3#[doc = "Register `CLKCTRL` writer"]
4pub type W = crate::W<ClkctrlSpec>;
5#[doc = "Generic Clock Selection ID\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7#[repr(u8)]
8pub enum Idselect {
9    #[doc = "0: DFLL48"]
10    Dfll48 = 0,
11    #[doc = "1: FDPLL"]
12    Fdpll = 1,
13    #[doc = "2: FDPLL32K"]
14    Fdpll32k = 2,
15    #[doc = "3: WDT"]
16    Wdt = 3,
17    #[doc = "4: RTC"]
18    Rtc = 4,
19    #[doc = "5: EIC"]
20    Eic = 5,
21    #[doc = "6: USB"]
22    Usb = 6,
23    #[doc = "7: EVSYS_0"]
24    Evsys0 = 7,
25    #[doc = "8: EVSYS_1"]
26    Evsys1 = 8,
27    #[doc = "9: EVSYS_2"]
28    Evsys2 = 9,
29    #[doc = "10: EVSYS_3"]
30    Evsys3 = 10,
31    #[doc = "11: EVSYS_4"]
32    Evsys4 = 11,
33    #[doc = "12: EVSYS_5"]
34    Evsys5 = 12,
35    #[doc = "13: SERCOMX_SLOW"]
36    SercomxSlow = 13,
37    #[doc = "14: SERCOM0_CORE"]
38    Sercom0Core = 14,
39    #[doc = "15: SERCOM1_CORE"]
40    Sercom1Core = 15,
41    #[doc = "16: SERCOM2_CORE"]
42    Sercom2Core = 16,
43    #[doc = "17: TCC0"]
44    Tcc0 = 17,
45    #[doc = "18: TC1_TC2"]
46    Tc1Tc2 = 18,
47    #[doc = "19: ADC"]
48    Adc = 19,
49    #[doc = "20: AC_DIG"]
50    AcDig = 20,
51    #[doc = "21: AC_ANA"]
52    AcAna = 21,
53    #[doc = "22: DAC"]
54    Dac = 22,
55}
56impl From<Idselect> for u8 {
57    #[inline(always)]
58    fn from(variant: Idselect) -> Self {
59        variant as _
60    }
61}
62impl crate::FieldSpec for Idselect {
63    type Ux = u8;
64}
65impl crate::IsEnum for Idselect {}
66#[doc = "Field `ID` reader - Generic Clock Selection ID"]
67pub type IdR = crate::FieldReader<Idselect>;
68impl IdR {
69    #[doc = "Get enumerated values variant"]
70    #[inline(always)]
71    pub const fn variant(&self) -> Option<Idselect> {
72        match self.bits {
73            0 => Some(Idselect::Dfll48),
74            1 => Some(Idselect::Fdpll),
75            2 => Some(Idselect::Fdpll32k),
76            3 => Some(Idselect::Wdt),
77            4 => Some(Idselect::Rtc),
78            5 => Some(Idselect::Eic),
79            6 => Some(Idselect::Usb),
80            7 => Some(Idselect::Evsys0),
81            8 => Some(Idselect::Evsys1),
82            9 => Some(Idselect::Evsys2),
83            10 => Some(Idselect::Evsys3),
84            11 => Some(Idselect::Evsys4),
85            12 => Some(Idselect::Evsys5),
86            13 => Some(Idselect::SercomxSlow),
87            14 => Some(Idselect::Sercom0Core),
88            15 => Some(Idselect::Sercom1Core),
89            16 => Some(Idselect::Sercom2Core),
90            17 => Some(Idselect::Tcc0),
91            18 => Some(Idselect::Tc1Tc2),
92            19 => Some(Idselect::Adc),
93            20 => Some(Idselect::AcDig),
94            21 => Some(Idselect::AcAna),
95            22 => Some(Idselect::Dac),
96            _ => None,
97        }
98    }
99    #[doc = "DFLL48"]
100    #[inline(always)]
101    pub fn is_dfll48(&self) -> bool {
102        *self == Idselect::Dfll48
103    }
104    #[doc = "FDPLL"]
105    #[inline(always)]
106    pub fn is_fdpll(&self) -> bool {
107        *self == Idselect::Fdpll
108    }
109    #[doc = "FDPLL32K"]
110    #[inline(always)]
111    pub fn is_fdpll32k(&self) -> bool {
112        *self == Idselect::Fdpll32k
113    }
114    #[doc = "WDT"]
115    #[inline(always)]
116    pub fn is_wdt(&self) -> bool {
117        *self == Idselect::Wdt
118    }
119    #[doc = "RTC"]
120    #[inline(always)]
121    pub fn is_rtc(&self) -> bool {
122        *self == Idselect::Rtc
123    }
124    #[doc = "EIC"]
125    #[inline(always)]
126    pub fn is_eic(&self) -> bool {
127        *self == Idselect::Eic
128    }
129    #[doc = "USB"]
130    #[inline(always)]
131    pub fn is_usb(&self) -> bool {
132        *self == Idselect::Usb
133    }
134    #[doc = "EVSYS_0"]
135    #[inline(always)]
136    pub fn is_evsys_0(&self) -> bool {
137        *self == Idselect::Evsys0
138    }
139    #[doc = "EVSYS_1"]
140    #[inline(always)]
141    pub fn is_evsys_1(&self) -> bool {
142        *self == Idselect::Evsys1
143    }
144    #[doc = "EVSYS_2"]
145    #[inline(always)]
146    pub fn is_evsys_2(&self) -> bool {
147        *self == Idselect::Evsys2
148    }
149    #[doc = "EVSYS_3"]
150    #[inline(always)]
151    pub fn is_evsys_3(&self) -> bool {
152        *self == Idselect::Evsys3
153    }
154    #[doc = "EVSYS_4"]
155    #[inline(always)]
156    pub fn is_evsys_4(&self) -> bool {
157        *self == Idselect::Evsys4
158    }
159    #[doc = "EVSYS_5"]
160    #[inline(always)]
161    pub fn is_evsys_5(&self) -> bool {
162        *self == Idselect::Evsys5
163    }
164    #[doc = "SERCOMX_SLOW"]
165    #[inline(always)]
166    pub fn is_sercomx_slow(&self) -> bool {
167        *self == Idselect::SercomxSlow
168    }
169    #[doc = "SERCOM0_CORE"]
170    #[inline(always)]
171    pub fn is_sercom0_core(&self) -> bool {
172        *self == Idselect::Sercom0Core
173    }
174    #[doc = "SERCOM1_CORE"]
175    #[inline(always)]
176    pub fn is_sercom1_core(&self) -> bool {
177        *self == Idselect::Sercom1Core
178    }
179    #[doc = "SERCOM2_CORE"]
180    #[inline(always)]
181    pub fn is_sercom2_core(&self) -> bool {
182        *self == Idselect::Sercom2Core
183    }
184    #[doc = "TCC0"]
185    #[inline(always)]
186    pub fn is_tcc0(&self) -> bool {
187        *self == Idselect::Tcc0
188    }
189    #[doc = "TC1_TC2"]
190    #[inline(always)]
191    pub fn is_tc1_tc2(&self) -> bool {
192        *self == Idselect::Tc1Tc2
193    }
194    #[doc = "ADC"]
195    #[inline(always)]
196    pub fn is_adc(&self) -> bool {
197        *self == Idselect::Adc
198    }
199    #[doc = "AC_DIG"]
200    #[inline(always)]
201    pub fn is_ac_dig(&self) -> bool {
202        *self == Idselect::AcDig
203    }
204    #[doc = "AC_ANA"]
205    #[inline(always)]
206    pub fn is_ac_ana(&self) -> bool {
207        *self == Idselect::AcAna
208    }
209    #[doc = "DAC"]
210    #[inline(always)]
211    pub fn is_dac(&self) -> bool {
212        *self == Idselect::Dac
213    }
214}
215#[doc = "Field `ID` writer - Generic Clock Selection ID"]
216pub type IdW<'a, REG> = crate::FieldWriter<'a, REG, 6, Idselect>;
217impl<'a, REG> IdW<'a, REG>
218where
219    REG: crate::Writable + crate::RegisterSpec,
220    REG::Ux: From<u8>,
221{
222    #[doc = "DFLL48"]
223    #[inline(always)]
224    pub fn dfll48(self) -> &'a mut crate::W<REG> {
225        self.variant(Idselect::Dfll48)
226    }
227    #[doc = "FDPLL"]
228    #[inline(always)]
229    pub fn fdpll(self) -> &'a mut crate::W<REG> {
230        self.variant(Idselect::Fdpll)
231    }
232    #[doc = "FDPLL32K"]
233    #[inline(always)]
234    pub fn fdpll32k(self) -> &'a mut crate::W<REG> {
235        self.variant(Idselect::Fdpll32k)
236    }
237    #[doc = "WDT"]
238    #[inline(always)]
239    pub fn wdt(self) -> &'a mut crate::W<REG> {
240        self.variant(Idselect::Wdt)
241    }
242    #[doc = "RTC"]
243    #[inline(always)]
244    pub fn rtc(self) -> &'a mut crate::W<REG> {
245        self.variant(Idselect::Rtc)
246    }
247    #[doc = "EIC"]
248    #[inline(always)]
249    pub fn eic(self) -> &'a mut crate::W<REG> {
250        self.variant(Idselect::Eic)
251    }
252    #[doc = "USB"]
253    #[inline(always)]
254    pub fn usb(self) -> &'a mut crate::W<REG> {
255        self.variant(Idselect::Usb)
256    }
257    #[doc = "EVSYS_0"]
258    #[inline(always)]
259    pub fn evsys_0(self) -> &'a mut crate::W<REG> {
260        self.variant(Idselect::Evsys0)
261    }
262    #[doc = "EVSYS_1"]
263    #[inline(always)]
264    pub fn evsys_1(self) -> &'a mut crate::W<REG> {
265        self.variant(Idselect::Evsys1)
266    }
267    #[doc = "EVSYS_2"]
268    #[inline(always)]
269    pub fn evsys_2(self) -> &'a mut crate::W<REG> {
270        self.variant(Idselect::Evsys2)
271    }
272    #[doc = "EVSYS_3"]
273    #[inline(always)]
274    pub fn evsys_3(self) -> &'a mut crate::W<REG> {
275        self.variant(Idselect::Evsys3)
276    }
277    #[doc = "EVSYS_4"]
278    #[inline(always)]
279    pub fn evsys_4(self) -> &'a mut crate::W<REG> {
280        self.variant(Idselect::Evsys4)
281    }
282    #[doc = "EVSYS_5"]
283    #[inline(always)]
284    pub fn evsys_5(self) -> &'a mut crate::W<REG> {
285        self.variant(Idselect::Evsys5)
286    }
287    #[doc = "SERCOMX_SLOW"]
288    #[inline(always)]
289    pub fn sercomx_slow(self) -> &'a mut crate::W<REG> {
290        self.variant(Idselect::SercomxSlow)
291    }
292    #[doc = "SERCOM0_CORE"]
293    #[inline(always)]
294    pub fn sercom0_core(self) -> &'a mut crate::W<REG> {
295        self.variant(Idselect::Sercom0Core)
296    }
297    #[doc = "SERCOM1_CORE"]
298    #[inline(always)]
299    pub fn sercom1_core(self) -> &'a mut crate::W<REG> {
300        self.variant(Idselect::Sercom1Core)
301    }
302    #[doc = "SERCOM2_CORE"]
303    #[inline(always)]
304    pub fn sercom2_core(self) -> &'a mut crate::W<REG> {
305        self.variant(Idselect::Sercom2Core)
306    }
307    #[doc = "TCC0"]
308    #[inline(always)]
309    pub fn tcc0(self) -> &'a mut crate::W<REG> {
310        self.variant(Idselect::Tcc0)
311    }
312    #[doc = "TC1_TC2"]
313    #[inline(always)]
314    pub fn tc1_tc2(self) -> &'a mut crate::W<REG> {
315        self.variant(Idselect::Tc1Tc2)
316    }
317    #[doc = "ADC"]
318    #[inline(always)]
319    pub fn adc(self) -> &'a mut crate::W<REG> {
320        self.variant(Idselect::Adc)
321    }
322    #[doc = "AC_DIG"]
323    #[inline(always)]
324    pub fn ac_dig(self) -> &'a mut crate::W<REG> {
325        self.variant(Idselect::AcDig)
326    }
327    #[doc = "AC_ANA"]
328    #[inline(always)]
329    pub fn ac_ana(self) -> &'a mut crate::W<REG> {
330        self.variant(Idselect::AcAna)
331    }
332    #[doc = "DAC"]
333    #[inline(always)]
334    pub fn dac(self) -> &'a mut crate::W<REG> {
335        self.variant(Idselect::Dac)
336    }
337}
338#[doc = "Generic Clock Generator\n\nValue on reset: 0"]
339#[derive(Clone, Copy, Debug, PartialEq, Eq)]
340#[repr(u8)]
341pub enum Genselect {
342    #[doc = "0: Generic clock generator 0"]
343    Gclk0 = 0,
344    #[doc = "1: Generic clock generator 1"]
345    Gclk1 = 1,
346    #[doc = "2: Generic clock generator 2"]
347    Gclk2 = 2,
348    #[doc = "3: Generic clock generator 3"]
349    Gclk3 = 3,
350    #[doc = "4: Generic clock generator 4"]
351    Gclk4 = 4,
352    #[doc = "5: Generic clock generator 5"]
353    Gclk5 = 5,
354}
355impl From<Genselect> for u8 {
356    #[inline(always)]
357    fn from(variant: Genselect) -> Self {
358        variant as _
359    }
360}
361impl crate::FieldSpec for Genselect {
362    type Ux = u8;
363}
364impl crate::IsEnum for Genselect {}
365#[doc = "Field `GEN` reader - Generic Clock Generator"]
366pub type GenR = crate::FieldReader<Genselect>;
367impl GenR {
368    #[doc = "Get enumerated values variant"]
369    #[inline(always)]
370    pub const fn variant(&self) -> Option<Genselect> {
371        match self.bits {
372            0 => Some(Genselect::Gclk0),
373            1 => Some(Genselect::Gclk1),
374            2 => Some(Genselect::Gclk2),
375            3 => Some(Genselect::Gclk3),
376            4 => Some(Genselect::Gclk4),
377            5 => Some(Genselect::Gclk5),
378            _ => None,
379        }
380    }
381    #[doc = "Generic clock generator 0"]
382    #[inline(always)]
383    pub fn is_gclk0(&self) -> bool {
384        *self == Genselect::Gclk0
385    }
386    #[doc = "Generic clock generator 1"]
387    #[inline(always)]
388    pub fn is_gclk1(&self) -> bool {
389        *self == Genselect::Gclk1
390    }
391    #[doc = "Generic clock generator 2"]
392    #[inline(always)]
393    pub fn is_gclk2(&self) -> bool {
394        *self == Genselect::Gclk2
395    }
396    #[doc = "Generic clock generator 3"]
397    #[inline(always)]
398    pub fn is_gclk3(&self) -> bool {
399        *self == Genselect::Gclk3
400    }
401    #[doc = "Generic clock generator 4"]
402    #[inline(always)]
403    pub fn is_gclk4(&self) -> bool {
404        *self == Genselect::Gclk4
405    }
406    #[doc = "Generic clock generator 5"]
407    #[inline(always)]
408    pub fn is_gclk5(&self) -> bool {
409        *self == Genselect::Gclk5
410    }
411}
412#[doc = "Field `GEN` writer - Generic Clock Generator"]
413pub type GenW<'a, REG> = crate::FieldWriter<'a, REG, 4, Genselect>;
414impl<'a, REG> GenW<'a, REG>
415where
416    REG: crate::Writable + crate::RegisterSpec,
417    REG::Ux: From<u8>,
418{
419    #[doc = "Generic clock generator 0"]
420    #[inline(always)]
421    pub fn gclk0(self) -> &'a mut crate::W<REG> {
422        self.variant(Genselect::Gclk0)
423    }
424    #[doc = "Generic clock generator 1"]
425    #[inline(always)]
426    pub fn gclk1(self) -> &'a mut crate::W<REG> {
427        self.variant(Genselect::Gclk1)
428    }
429    #[doc = "Generic clock generator 2"]
430    #[inline(always)]
431    pub fn gclk2(self) -> &'a mut crate::W<REG> {
432        self.variant(Genselect::Gclk2)
433    }
434    #[doc = "Generic clock generator 3"]
435    #[inline(always)]
436    pub fn gclk3(self) -> &'a mut crate::W<REG> {
437        self.variant(Genselect::Gclk3)
438    }
439    #[doc = "Generic clock generator 4"]
440    #[inline(always)]
441    pub fn gclk4(self) -> &'a mut crate::W<REG> {
442        self.variant(Genselect::Gclk4)
443    }
444    #[doc = "Generic clock generator 5"]
445    #[inline(always)]
446    pub fn gclk5(self) -> &'a mut crate::W<REG> {
447        self.variant(Genselect::Gclk5)
448    }
449}
450#[doc = "Field `CLKEN` reader - Clock Enable"]
451pub type ClkenR = crate::BitReader;
452#[doc = "Field `CLKEN` writer - Clock Enable"]
453pub type ClkenW<'a, REG> = crate::BitWriter<'a, REG>;
454#[doc = "Field `WRTLOCK` reader - Write Lock"]
455pub type WrtlockR = crate::BitReader;
456#[doc = "Field `WRTLOCK` writer - Write Lock"]
457pub type WrtlockW<'a, REG> = crate::BitWriter<'a, REG>;
458impl R {
459    #[doc = "Bits 0:5 - Generic Clock Selection ID"]
460    #[inline(always)]
461    pub fn id(&self) -> IdR {
462        IdR::new((self.bits & 0x3f) as u8)
463    }
464    #[doc = "Bits 8:11 - Generic Clock Generator"]
465    #[inline(always)]
466    pub fn gen(&self) -> GenR {
467        GenR::new(((self.bits >> 8) & 0x0f) as u8)
468    }
469    #[doc = "Bit 14 - Clock Enable"]
470    #[inline(always)]
471    pub fn clken(&self) -> ClkenR {
472        ClkenR::new(((self.bits >> 14) & 1) != 0)
473    }
474    #[doc = "Bit 15 - Write Lock"]
475    #[inline(always)]
476    pub fn wrtlock(&self) -> WrtlockR {
477        WrtlockR::new(((self.bits >> 15) & 1) != 0)
478    }
479}
480impl W {
481    #[doc = "Bits 0:5 - Generic Clock Selection ID"]
482    #[inline(always)]
483    #[must_use]
484    pub fn id(&mut self) -> IdW<ClkctrlSpec> {
485        IdW::new(self, 0)
486    }
487    #[doc = "Bits 8:11 - Generic Clock Generator"]
488    #[inline(always)]
489    #[must_use]
490    pub fn gen(&mut self) -> GenW<ClkctrlSpec> {
491        GenW::new(self, 8)
492    }
493    #[doc = "Bit 14 - Clock Enable"]
494    #[inline(always)]
495    #[must_use]
496    pub fn clken(&mut self) -> ClkenW<ClkctrlSpec> {
497        ClkenW::new(self, 14)
498    }
499    #[doc = "Bit 15 - Write Lock"]
500    #[inline(always)]
501    #[must_use]
502    pub fn wrtlock(&mut self) -> WrtlockW<ClkctrlSpec> {
503        WrtlockW::new(self, 15)
504    }
505}
506#[doc = "Generic Clock Control\n\nYou can [`read`](crate::Reg::read) this register and get [`clkctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
507pub struct ClkctrlSpec;
508impl crate::RegisterSpec for ClkctrlSpec {
509    type Ux = u16;
510}
511#[doc = "`read()` method returns [`clkctrl::R`](R) reader structure"]
512impl crate::Readable for ClkctrlSpec {}
513#[doc = "`write(|w| ..)` method takes [`clkctrl::W`](W) writer structure"]
514impl crate::Writable for ClkctrlSpec {
515    type Safety = crate::Unsafe;
516    const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
517    const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
518}
519#[doc = "`reset()` method sets CLKCTRL to value 0"]
520impl crate::Resettable for ClkctrlSpec {
521    const RESET_VALUE: u16 = 0;
522}
atsamd11c/gclk/clkctrl.rs

atsamd11c/gclk/
clkctrl.rs
