atsamd11c/ac/
compctrl.rs

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1#[doc = "Register `COMPCTRL%s` reader"]
2pub type R = crate::R<CompctrlSpec>;
3#[doc = "Register `COMPCTRL%s` writer"]
4pub type W = crate::W<CompctrlSpec>;
5#[doc = "Field `ENABLE` reader - Enable"]
6pub type EnableR = crate::BitReader;
7#[doc = "Field `ENABLE` writer - Enable"]
8pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `SINGLE` reader - Single-Shot Mode"]
10pub type SingleR = crate::BitReader;
11#[doc = "Field `SINGLE` writer - Single-Shot Mode"]
12pub type SingleW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Speed Selection\n\nValue on reset: 0"]
14#[derive(Clone, Copy, Debug, PartialEq, Eq)]
15#[repr(u8)]
16pub enum Speedselect {
17    #[doc = "0: Low speed"]
18    Low = 0,
19    #[doc = "1: High speed"]
20    High = 1,
21}
22impl From<Speedselect> for u8 {
23    #[inline(always)]
24    fn from(variant: Speedselect) -> Self {
25        variant as _
26    }
27}
28impl crate::FieldSpec for Speedselect {
29    type Ux = u8;
30}
31impl crate::IsEnum for Speedselect {}
32#[doc = "Field `SPEED` reader - Speed Selection"]
33pub type SpeedR = crate::FieldReader<Speedselect>;
34impl SpeedR {
35    #[doc = "Get enumerated values variant"]
36    #[inline(always)]
37    pub const fn variant(&self) -> Option<Speedselect> {
38        match self.bits {
39            0 => Some(Speedselect::Low),
40            1 => Some(Speedselect::High),
41            _ => None,
42        }
43    }
44    #[doc = "Low speed"]
45    #[inline(always)]
46    pub fn is_low(&self) -> bool {
47        *self == Speedselect::Low
48    }
49    #[doc = "High speed"]
50    #[inline(always)]
51    pub fn is_high(&self) -> bool {
52        *self == Speedselect::High
53    }
54}
55#[doc = "Field `SPEED` writer - Speed Selection"]
56pub type SpeedW<'a, REG> = crate::FieldWriter<'a, REG, 2, Speedselect>;
57impl<'a, REG> SpeedW<'a, REG>
58where
59    REG: crate::Writable + crate::RegisterSpec,
60    REG::Ux: From<u8>,
61{
62    #[doc = "Low speed"]
63    #[inline(always)]
64    pub fn low(self) -> &'a mut crate::W<REG> {
65        self.variant(Speedselect::Low)
66    }
67    #[doc = "High speed"]
68    #[inline(always)]
69    pub fn high(self) -> &'a mut crate::W<REG> {
70        self.variant(Speedselect::High)
71    }
72}
73#[doc = "Interrupt Selection\n\nValue on reset: 0"]
74#[derive(Clone, Copy, Debug, PartialEq, Eq)]
75#[repr(u8)]
76pub enum Intselselect {
77    #[doc = "0: Interrupt on comparator output toggle"]
78    Toggle = 0,
79    #[doc = "1: Interrupt on comparator output rising"]
80    Rising = 1,
81    #[doc = "2: Interrupt on comparator output falling"]
82    Falling = 2,
83    #[doc = "3: Interrupt on end of comparison (single-shot mode only)"]
84    Eoc = 3,
85}
86impl From<Intselselect> for u8 {
87    #[inline(always)]
88    fn from(variant: Intselselect) -> Self {
89        variant as _
90    }
91}
92impl crate::FieldSpec for Intselselect {
93    type Ux = u8;
94}
95impl crate::IsEnum for Intselselect {}
96#[doc = "Field `INTSEL` reader - Interrupt Selection"]
97pub type IntselR = crate::FieldReader<Intselselect>;
98impl IntselR {
99    #[doc = "Get enumerated values variant"]
100    #[inline(always)]
101    pub const fn variant(&self) -> Intselselect {
102        match self.bits {
103            0 => Intselselect::Toggle,
104            1 => Intselselect::Rising,
105            2 => Intselselect::Falling,
106            3 => Intselselect::Eoc,
107            _ => unreachable!(),
108        }
109    }
110    #[doc = "Interrupt on comparator output toggle"]
111    #[inline(always)]
112    pub fn is_toggle(&self) -> bool {
113        *self == Intselselect::Toggle
114    }
115    #[doc = "Interrupt on comparator output rising"]
116    #[inline(always)]
117    pub fn is_rising(&self) -> bool {
118        *self == Intselselect::Rising
119    }
120    #[doc = "Interrupt on comparator output falling"]
121    #[inline(always)]
122    pub fn is_falling(&self) -> bool {
123        *self == Intselselect::Falling
124    }
125    #[doc = "Interrupt on end of comparison (single-shot mode only)"]
126    #[inline(always)]
127    pub fn is_eoc(&self) -> bool {
128        *self == Intselselect::Eoc
129    }
130}
131#[doc = "Field `INTSEL` writer - Interrupt Selection"]
132pub type IntselW<'a, REG> = crate::FieldWriter<'a, REG, 2, Intselselect, crate::Safe>;
133impl<'a, REG> IntselW<'a, REG>
134where
135    REG: crate::Writable + crate::RegisterSpec,
136    REG::Ux: From<u8>,
137{
138    #[doc = "Interrupt on comparator output toggle"]
139    #[inline(always)]
140    pub fn toggle(self) -> &'a mut crate::W<REG> {
141        self.variant(Intselselect::Toggle)
142    }
143    #[doc = "Interrupt on comparator output rising"]
144    #[inline(always)]
145    pub fn rising(self) -> &'a mut crate::W<REG> {
146        self.variant(Intselselect::Rising)
147    }
148    #[doc = "Interrupt on comparator output falling"]
149    #[inline(always)]
150    pub fn falling(self) -> &'a mut crate::W<REG> {
151        self.variant(Intselselect::Falling)
152    }
153    #[doc = "Interrupt on end of comparison (single-shot mode only)"]
154    #[inline(always)]
155    pub fn eoc(self) -> &'a mut crate::W<REG> {
156        self.variant(Intselselect::Eoc)
157    }
158}
159#[doc = "Negative Input Mux Selection\n\nValue on reset: 0"]
160#[derive(Clone, Copy, Debug, PartialEq, Eq)]
161#[repr(u8)]
162pub enum Muxnegselect {
163    #[doc = "0: I/O pin 0"]
164    Pin0 = 0,
165    #[doc = "1: I/O pin 1"]
166    Pin1 = 1,
167    #[doc = "2: I/O pin 2"]
168    Pin2 = 2,
169    #[doc = "3: I/O pin 3"]
170    Pin3 = 3,
171    #[doc = "4: Ground"]
172    Gnd = 4,
173    #[doc = "5: VDD scaler"]
174    Vscale = 5,
175    #[doc = "6: Internal bandgap voltage"]
176    Bandgap = 6,
177    #[doc = "7: DAC output"]
178    Dac = 7,
179}
180impl From<Muxnegselect> for u8 {
181    #[inline(always)]
182    fn from(variant: Muxnegselect) -> Self {
183        variant as _
184    }
185}
186impl crate::FieldSpec for Muxnegselect {
187    type Ux = u8;
188}
189impl crate::IsEnum for Muxnegselect {}
190#[doc = "Field `MUXNEG` reader - Negative Input Mux Selection"]
191pub type MuxnegR = crate::FieldReader<Muxnegselect>;
192impl MuxnegR {
193    #[doc = "Get enumerated values variant"]
194    #[inline(always)]
195    pub const fn variant(&self) -> Muxnegselect {
196        match self.bits {
197            0 => Muxnegselect::Pin0,
198            1 => Muxnegselect::Pin1,
199            2 => Muxnegselect::Pin2,
200            3 => Muxnegselect::Pin3,
201            4 => Muxnegselect::Gnd,
202            5 => Muxnegselect::Vscale,
203            6 => Muxnegselect::Bandgap,
204            7 => Muxnegselect::Dac,
205            _ => unreachable!(),
206        }
207    }
208    #[doc = "I/O pin 0"]
209    #[inline(always)]
210    pub fn is_pin0(&self) -> bool {
211        *self == Muxnegselect::Pin0
212    }
213    #[doc = "I/O pin 1"]
214    #[inline(always)]
215    pub fn is_pin1(&self) -> bool {
216        *self == Muxnegselect::Pin1
217    }
218    #[doc = "I/O pin 2"]
219    #[inline(always)]
220    pub fn is_pin2(&self) -> bool {
221        *self == Muxnegselect::Pin2
222    }
223    #[doc = "I/O pin 3"]
224    #[inline(always)]
225    pub fn is_pin3(&self) -> bool {
226        *self == Muxnegselect::Pin3
227    }
228    #[doc = "Ground"]
229    #[inline(always)]
230    pub fn is_gnd(&self) -> bool {
231        *self == Muxnegselect::Gnd
232    }
233    #[doc = "VDD scaler"]
234    #[inline(always)]
235    pub fn is_vscale(&self) -> bool {
236        *self == Muxnegselect::Vscale
237    }
238    #[doc = "Internal bandgap voltage"]
239    #[inline(always)]
240    pub fn is_bandgap(&self) -> bool {
241        *self == Muxnegselect::Bandgap
242    }
243    #[doc = "DAC output"]
244    #[inline(always)]
245    pub fn is_dac(&self) -> bool {
246        *self == Muxnegselect::Dac
247    }
248}
249#[doc = "Field `MUXNEG` writer - Negative Input Mux Selection"]
250pub type MuxnegW<'a, REG> = crate::FieldWriter<'a, REG, 3, Muxnegselect, crate::Safe>;
251impl<'a, REG> MuxnegW<'a, REG>
252where
253    REG: crate::Writable + crate::RegisterSpec,
254    REG::Ux: From<u8>,
255{
256    #[doc = "I/O pin 0"]
257    #[inline(always)]
258    pub fn pin0(self) -> &'a mut crate::W<REG> {
259        self.variant(Muxnegselect::Pin0)
260    }
261    #[doc = "I/O pin 1"]
262    #[inline(always)]
263    pub fn pin1(self) -> &'a mut crate::W<REG> {
264        self.variant(Muxnegselect::Pin1)
265    }
266    #[doc = "I/O pin 2"]
267    #[inline(always)]
268    pub fn pin2(self) -> &'a mut crate::W<REG> {
269        self.variant(Muxnegselect::Pin2)
270    }
271    #[doc = "I/O pin 3"]
272    #[inline(always)]
273    pub fn pin3(self) -> &'a mut crate::W<REG> {
274        self.variant(Muxnegselect::Pin3)
275    }
276    #[doc = "Ground"]
277    #[inline(always)]
278    pub fn gnd(self) -> &'a mut crate::W<REG> {
279        self.variant(Muxnegselect::Gnd)
280    }
281    #[doc = "VDD scaler"]
282    #[inline(always)]
283    pub fn vscale(self) -> &'a mut crate::W<REG> {
284        self.variant(Muxnegselect::Vscale)
285    }
286    #[doc = "Internal bandgap voltage"]
287    #[inline(always)]
288    pub fn bandgap(self) -> &'a mut crate::W<REG> {
289        self.variant(Muxnegselect::Bandgap)
290    }
291    #[doc = "DAC output"]
292    #[inline(always)]
293    pub fn dac(self) -> &'a mut crate::W<REG> {
294        self.variant(Muxnegselect::Dac)
295    }
296}
297#[doc = "Positive Input Mux Selection\n\nValue on reset: 0"]
298#[derive(Clone, Copy, Debug, PartialEq, Eq)]
299#[repr(u8)]
300pub enum Muxposselect {
301    #[doc = "0: I/O pin 0"]
302    Pin0 = 0,
303    #[doc = "1: I/O pin 1"]
304    Pin1 = 1,
305    #[doc = "2: I/O pin 2"]
306    Pin2 = 2,
307    #[doc = "3: I/O pin 3"]
308    Pin3 = 3,
309}
310impl From<Muxposselect> for u8 {
311    #[inline(always)]
312    fn from(variant: Muxposselect) -> Self {
313        variant as _
314    }
315}
316impl crate::FieldSpec for Muxposselect {
317    type Ux = u8;
318}
319impl crate::IsEnum for Muxposselect {}
320#[doc = "Field `MUXPOS` reader - Positive Input Mux Selection"]
321pub type MuxposR = crate::FieldReader<Muxposselect>;
322impl MuxposR {
323    #[doc = "Get enumerated values variant"]
324    #[inline(always)]
325    pub const fn variant(&self) -> Muxposselect {
326        match self.bits {
327            0 => Muxposselect::Pin0,
328            1 => Muxposselect::Pin1,
329            2 => Muxposselect::Pin2,
330            3 => Muxposselect::Pin3,
331            _ => unreachable!(),
332        }
333    }
334    #[doc = "I/O pin 0"]
335    #[inline(always)]
336    pub fn is_pin0(&self) -> bool {
337        *self == Muxposselect::Pin0
338    }
339    #[doc = "I/O pin 1"]
340    #[inline(always)]
341    pub fn is_pin1(&self) -> bool {
342        *self == Muxposselect::Pin1
343    }
344    #[doc = "I/O pin 2"]
345    #[inline(always)]
346    pub fn is_pin2(&self) -> bool {
347        *self == Muxposselect::Pin2
348    }
349    #[doc = "I/O pin 3"]
350    #[inline(always)]
351    pub fn is_pin3(&self) -> bool {
352        *self == Muxposselect::Pin3
353    }
354}
355#[doc = "Field `MUXPOS` writer - Positive Input Mux Selection"]
356pub type MuxposW<'a, REG> = crate::FieldWriter<'a, REG, 2, Muxposselect, crate::Safe>;
357impl<'a, REG> MuxposW<'a, REG>
358where
359    REG: crate::Writable + crate::RegisterSpec,
360    REG::Ux: From<u8>,
361{
362    #[doc = "I/O pin 0"]
363    #[inline(always)]
364    pub fn pin0(self) -> &'a mut crate::W<REG> {
365        self.variant(Muxposselect::Pin0)
366    }
367    #[doc = "I/O pin 1"]
368    #[inline(always)]
369    pub fn pin1(self) -> &'a mut crate::W<REG> {
370        self.variant(Muxposselect::Pin1)
371    }
372    #[doc = "I/O pin 2"]
373    #[inline(always)]
374    pub fn pin2(self) -> &'a mut crate::W<REG> {
375        self.variant(Muxposselect::Pin2)
376    }
377    #[doc = "I/O pin 3"]
378    #[inline(always)]
379    pub fn pin3(self) -> &'a mut crate::W<REG> {
380        self.variant(Muxposselect::Pin3)
381    }
382}
383#[doc = "Field `SWAP` reader - Swap Inputs and Invert"]
384pub type SwapR = crate::BitReader;
385#[doc = "Field `SWAP` writer - Swap Inputs and Invert"]
386pub type SwapW<'a, REG> = crate::BitWriter<'a, REG>;
387#[doc = "Output\n\nValue on reset: 0"]
388#[derive(Clone, Copy, Debug, PartialEq, Eq)]
389#[repr(u8)]
390pub enum Outselect {
391    #[doc = "0: The output of COMPn is not routed to the COMPn I/O port"]
392    Off = 0,
393    #[doc = "1: The asynchronous output of COMPn is routed to the COMPn I/O port"]
394    Async = 1,
395    #[doc = "2: The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port"]
396    Sync = 2,
397}
398impl From<Outselect> for u8 {
399    #[inline(always)]
400    fn from(variant: Outselect) -> Self {
401        variant as _
402    }
403}
404impl crate::FieldSpec for Outselect {
405    type Ux = u8;
406}
407impl crate::IsEnum for Outselect {}
408#[doc = "Field `OUT` reader - Output"]
409pub type OutR = crate::FieldReader<Outselect>;
410impl OutR {
411    #[doc = "Get enumerated values variant"]
412    #[inline(always)]
413    pub const fn variant(&self) -> Option<Outselect> {
414        match self.bits {
415            0 => Some(Outselect::Off),
416            1 => Some(Outselect::Async),
417            2 => Some(Outselect::Sync),
418            _ => None,
419        }
420    }
421    #[doc = "The output of COMPn is not routed to the COMPn I/O port"]
422    #[inline(always)]
423    pub fn is_off(&self) -> bool {
424        *self == Outselect::Off
425    }
426    #[doc = "The asynchronous output of COMPn is routed to the COMPn I/O port"]
427    #[inline(always)]
428    pub fn is_async(&self) -> bool {
429        *self == Outselect::Async
430    }
431    #[doc = "The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port"]
432    #[inline(always)]
433    pub fn is_sync(&self) -> bool {
434        *self == Outselect::Sync
435    }
436}
437#[doc = "Field `OUT` writer - Output"]
438pub type OutW<'a, REG> = crate::FieldWriter<'a, REG, 2, Outselect>;
439impl<'a, REG> OutW<'a, REG>
440where
441    REG: crate::Writable + crate::RegisterSpec,
442    REG::Ux: From<u8>,
443{
444    #[doc = "The output of COMPn is not routed to the COMPn I/O port"]
445    #[inline(always)]
446    pub fn off(self) -> &'a mut crate::W<REG> {
447        self.variant(Outselect::Off)
448    }
449    #[doc = "The asynchronous output of COMPn is routed to the COMPn I/O port"]
450    #[inline(always)]
451    pub fn async_(self) -> &'a mut crate::W<REG> {
452        self.variant(Outselect::Async)
453    }
454    #[doc = "The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port"]
455    #[inline(always)]
456    pub fn sync(self) -> &'a mut crate::W<REG> {
457        self.variant(Outselect::Sync)
458    }
459}
460#[doc = "Field `HYST` reader - Hysteresis Enable"]
461pub type HystR = crate::BitReader;
462#[doc = "Field `HYST` writer - Hysteresis Enable"]
463pub type HystW<'a, REG> = crate::BitWriter<'a, REG>;
464#[doc = "Filter Length\n\nValue on reset: 0"]
465#[derive(Clone, Copy, Debug, PartialEq, Eq)]
466#[repr(u8)]
467pub enum Flenselect {
468    #[doc = "0: No filtering"]
469    Off = 0,
470    #[doc = "1: 3-bit majority function (2 of 3)"]
471    Maj3 = 1,
472    #[doc = "2: 5-bit majority function (3 of 5)"]
473    Maj5 = 2,
474}
475impl From<Flenselect> for u8 {
476    #[inline(always)]
477    fn from(variant: Flenselect) -> Self {
478        variant as _
479    }
480}
481impl crate::FieldSpec for Flenselect {
482    type Ux = u8;
483}
484impl crate::IsEnum for Flenselect {}
485#[doc = "Field `FLEN` reader - Filter Length"]
486pub type FlenR = crate::FieldReader<Flenselect>;
487impl FlenR {
488    #[doc = "Get enumerated values variant"]
489    #[inline(always)]
490    pub const fn variant(&self) -> Option<Flenselect> {
491        match self.bits {
492            0 => Some(Flenselect::Off),
493            1 => Some(Flenselect::Maj3),
494            2 => Some(Flenselect::Maj5),
495            _ => None,
496        }
497    }
498    #[doc = "No filtering"]
499    #[inline(always)]
500    pub fn is_off(&self) -> bool {
501        *self == Flenselect::Off
502    }
503    #[doc = "3-bit majority function (2 of 3)"]
504    #[inline(always)]
505    pub fn is_maj3(&self) -> bool {
506        *self == Flenselect::Maj3
507    }
508    #[doc = "5-bit majority function (3 of 5)"]
509    #[inline(always)]
510    pub fn is_maj5(&self) -> bool {
511        *self == Flenselect::Maj5
512    }
513}
514#[doc = "Field `FLEN` writer - Filter Length"]
515pub type FlenW<'a, REG> = crate::FieldWriter<'a, REG, 3, Flenselect>;
516impl<'a, REG> FlenW<'a, REG>
517where
518    REG: crate::Writable + crate::RegisterSpec,
519    REG::Ux: From<u8>,
520{
521    #[doc = "No filtering"]
522    #[inline(always)]
523    pub fn off(self) -> &'a mut crate::W<REG> {
524        self.variant(Flenselect::Off)
525    }
526    #[doc = "3-bit majority function (2 of 3)"]
527    #[inline(always)]
528    pub fn maj3(self) -> &'a mut crate::W<REG> {
529        self.variant(Flenselect::Maj3)
530    }
531    #[doc = "5-bit majority function (3 of 5)"]
532    #[inline(always)]
533    pub fn maj5(self) -> &'a mut crate::W<REG> {
534        self.variant(Flenselect::Maj5)
535    }
536}
537impl R {
538    #[doc = "Bit 0 - Enable"]
539    #[inline(always)]
540    pub fn enable(&self) -> EnableR {
541        EnableR::new((self.bits & 1) != 0)
542    }
543    #[doc = "Bit 1 - Single-Shot Mode"]
544    #[inline(always)]
545    pub fn single(&self) -> SingleR {
546        SingleR::new(((self.bits >> 1) & 1) != 0)
547    }
548    #[doc = "Bits 2:3 - Speed Selection"]
549    #[inline(always)]
550    pub fn speed(&self) -> SpeedR {
551        SpeedR::new(((self.bits >> 2) & 3) as u8)
552    }
553    #[doc = "Bits 5:6 - Interrupt Selection"]
554    #[inline(always)]
555    pub fn intsel(&self) -> IntselR {
556        IntselR::new(((self.bits >> 5) & 3) as u8)
557    }
558    #[doc = "Bits 8:10 - Negative Input Mux Selection"]
559    #[inline(always)]
560    pub fn muxneg(&self) -> MuxnegR {
561        MuxnegR::new(((self.bits >> 8) & 7) as u8)
562    }
563    #[doc = "Bits 12:13 - Positive Input Mux Selection"]
564    #[inline(always)]
565    pub fn muxpos(&self) -> MuxposR {
566        MuxposR::new(((self.bits >> 12) & 3) as u8)
567    }
568    #[doc = "Bit 15 - Swap Inputs and Invert"]
569    #[inline(always)]
570    pub fn swap(&self) -> SwapR {
571        SwapR::new(((self.bits >> 15) & 1) != 0)
572    }
573    #[doc = "Bits 16:17 - Output"]
574    #[inline(always)]
575    pub fn out(&self) -> OutR {
576        OutR::new(((self.bits >> 16) & 3) as u8)
577    }
578    #[doc = "Bit 19 - Hysteresis Enable"]
579    #[inline(always)]
580    pub fn hyst(&self) -> HystR {
581        HystR::new(((self.bits >> 19) & 1) != 0)
582    }
583    #[doc = "Bits 24:26 - Filter Length"]
584    #[inline(always)]
585    pub fn flen(&self) -> FlenR {
586        FlenR::new(((self.bits >> 24) & 7) as u8)
587    }
588}
589impl W {
590    #[doc = "Bit 0 - Enable"]
591    #[inline(always)]
592    #[must_use]
593    pub fn enable(&mut self) -> EnableW<CompctrlSpec> {
594        EnableW::new(self, 0)
595    }
596    #[doc = "Bit 1 - Single-Shot Mode"]
597    #[inline(always)]
598    #[must_use]
599    pub fn single(&mut self) -> SingleW<CompctrlSpec> {
600        SingleW::new(self, 1)
601    }
602    #[doc = "Bits 2:3 - Speed Selection"]
603    #[inline(always)]
604    #[must_use]
605    pub fn speed(&mut self) -> SpeedW<CompctrlSpec> {
606        SpeedW::new(self, 2)
607    }
608    #[doc = "Bits 5:6 - Interrupt Selection"]
609    #[inline(always)]
610    #[must_use]
611    pub fn intsel(&mut self) -> IntselW<CompctrlSpec> {
612        IntselW::new(self, 5)
613    }
614    #[doc = "Bits 8:10 - Negative Input Mux Selection"]
615    #[inline(always)]
616    #[must_use]
617    pub fn muxneg(&mut self) -> MuxnegW<CompctrlSpec> {
618        MuxnegW::new(self, 8)
619    }
620    #[doc = "Bits 12:13 - Positive Input Mux Selection"]
621    #[inline(always)]
622    #[must_use]
623    pub fn muxpos(&mut self) -> MuxposW<CompctrlSpec> {
624        MuxposW::new(self, 12)
625    }
626    #[doc = "Bit 15 - Swap Inputs and Invert"]
627    #[inline(always)]
628    #[must_use]
629    pub fn swap(&mut self) -> SwapW<CompctrlSpec> {
630        SwapW::new(self, 15)
631    }
632    #[doc = "Bits 16:17 - Output"]
633    #[inline(always)]
634    #[must_use]
635    pub fn out(&mut self) -> OutW<CompctrlSpec> {
636        OutW::new(self, 16)
637    }
638    #[doc = "Bit 19 - Hysteresis Enable"]
639    #[inline(always)]
640    #[must_use]
641    pub fn hyst(&mut self) -> HystW<CompctrlSpec> {
642        HystW::new(self, 19)
643    }
644    #[doc = "Bits 24:26 - Filter Length"]
645    #[inline(always)]
646    #[must_use]
647    pub fn flen(&mut self) -> FlenW<CompctrlSpec> {
648        FlenW::new(self, 24)
649    }
650}
651#[doc = "Comparator Control n\n\nYou can [`read`](crate::Reg::read) this register and get [`compctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`compctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
652pub struct CompctrlSpec;
653impl crate::RegisterSpec for CompctrlSpec {
654    type Ux = u32;
655}
656#[doc = "`read()` method returns [`compctrl::R`](R) reader structure"]
657impl crate::Readable for CompctrlSpec {}
658#[doc = "`write(|w| ..)` method takes [`compctrl::W`](W) writer structure"]
659impl crate::Writable for CompctrlSpec {
660    type Safety = crate::Unsafe;
661    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
662    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
663}
664#[doc = "`reset()` method sets COMPCTRL%s to value 0"]
665impl crate::Resettable for CompctrlSpec {
666    const RESET_VALUE: u32 = 0;
667}
atsamd11c/ac/compctrl.rs

atsamd11c/ac/
compctrl.rs
