atsamd11c/mtb/
master.rs

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1#[doc = "Register `MASTER` reader"]
2pub type R = crate::R<MasterSpec>;
3#[doc = "Register `MASTER` writer"]
4pub type W = crate::W<MasterSpec>;
5#[doc = "Field `MASK` reader - Maximum Value of the Trace Buffer in SRAM"]
6pub type MaskR = crate::FieldReader;
7#[doc = "Field `MASK` writer - Maximum Value of the Trace Buffer in SRAM"]
8pub type MaskW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
9#[doc = "Field `TSTARTEN` reader - Trace Start Input Enable"]
10pub type TstartenR = crate::BitReader;
11#[doc = "Field `TSTARTEN` writer - Trace Start Input Enable"]
12pub type TstartenW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `TSTOPEN` reader - Trace Stop Input Enable"]
14pub type TstopenR = crate::BitReader;
15#[doc = "Field `TSTOPEN` writer - Trace Stop Input Enable"]
16pub type TstopenW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `SFRWPRIV` reader - Special Function Register Write Privilege"]
18pub type SfrwprivR = crate::BitReader;
19#[doc = "Field `SFRWPRIV` writer - Special Function Register Write Privilege"]
20pub type SfrwprivW<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `RAMPRIV` reader - SRAM Privilege"]
22pub type RamprivR = crate::BitReader;
23#[doc = "Field `RAMPRIV` writer - SRAM Privilege"]
24pub type RamprivW<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `HALTREQ` reader - Halt Request"]
26pub type HaltreqR = crate::BitReader;
27#[doc = "Field `HALTREQ` writer - Halt Request"]
28pub type HaltreqW<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `EN` reader - Main Trace Enable"]
30pub type EnR = crate::BitReader;
31#[doc = "Field `EN` writer - Main Trace Enable"]
32pub type EnW<'a, REG> = crate::BitWriter<'a, REG>;
33impl R {
34    #[doc = "Bits 0:4 - Maximum Value of the Trace Buffer in SRAM"]
35    #[inline(always)]
36    pub fn mask(&self) -> MaskR {
37        MaskR::new((self.bits & 0x1f) as u8)
38    }
39    #[doc = "Bit 5 - Trace Start Input Enable"]
40    #[inline(always)]
41    pub fn tstarten(&self) -> TstartenR {
42        TstartenR::new(((self.bits >> 5) & 1) != 0)
43    }
44    #[doc = "Bit 6 - Trace Stop Input Enable"]
45    #[inline(always)]
46    pub fn tstopen(&self) -> TstopenR {
47        TstopenR::new(((self.bits >> 6) & 1) != 0)
48    }
49    #[doc = "Bit 7 - Special Function Register Write Privilege"]
50    #[inline(always)]
51    pub fn sfrwpriv(&self) -> SfrwprivR {
52        SfrwprivR::new(((self.bits >> 7) & 1) != 0)
53    }
54    #[doc = "Bit 8 - SRAM Privilege"]
55    #[inline(always)]
56    pub fn rampriv(&self) -> RamprivR {
57        RamprivR::new(((self.bits >> 8) & 1) != 0)
58    }
59    #[doc = "Bit 9 - Halt Request"]
60    #[inline(always)]
61    pub fn haltreq(&self) -> HaltreqR {
62        HaltreqR::new(((self.bits >> 9) & 1) != 0)
63    }
64    #[doc = "Bit 31 - Main Trace Enable"]
65    #[inline(always)]
66    pub fn en(&self) -> EnR {
67        EnR::new(((self.bits >> 31) & 1) != 0)
68    }
69}
70impl W {
71    #[doc = "Bits 0:4 - Maximum Value of the Trace Buffer in SRAM"]
72    #[inline(always)]
73    #[must_use]
74    pub fn mask(&mut self) -> MaskW<MasterSpec> {
75        MaskW::new(self, 0)
76    }
77    #[doc = "Bit 5 - Trace Start Input Enable"]
78    #[inline(always)]
79    #[must_use]
80    pub fn tstarten(&mut self) -> TstartenW<MasterSpec> {
81        TstartenW::new(self, 5)
82    }
83    #[doc = "Bit 6 - Trace Stop Input Enable"]
84    #[inline(always)]
85    #[must_use]
86    pub fn tstopen(&mut self) -> TstopenW<MasterSpec> {
87        TstopenW::new(self, 6)
88    }
89    #[doc = "Bit 7 - Special Function Register Write Privilege"]
90    #[inline(always)]
91    #[must_use]
92    pub fn sfrwpriv(&mut self) -> SfrwprivW<MasterSpec> {
93        SfrwprivW::new(self, 7)
94    }
95    #[doc = "Bit 8 - SRAM Privilege"]
96    #[inline(always)]
97    #[must_use]
98    pub fn rampriv(&mut self) -> RamprivW<MasterSpec> {
99        RamprivW::new(self, 8)
100    }
101    #[doc = "Bit 9 - Halt Request"]
102    #[inline(always)]
103    #[must_use]
104    pub fn haltreq(&mut self) -> HaltreqW<MasterSpec> {
105        HaltreqW::new(self, 9)
106    }
107    #[doc = "Bit 31 - Main Trace Enable"]
108    #[inline(always)]
109    #[must_use]
110    pub fn en(&mut self) -> EnW<MasterSpec> {
111        EnW::new(self, 31)
112    }
113}
114#[doc = "MTB Master\n\nYou can [`read`](crate::Reg::read) this register and get [`master::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`master::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
115pub struct MasterSpec;
116impl crate::RegisterSpec for MasterSpec {
117    type Ux = u32;
118}
119#[doc = "`read()` method returns [`master::R`](R) reader structure"]
120impl crate::Readable for MasterSpec {}
121#[doc = "`write(|w| ..)` method takes [`master::W`](W) writer structure"]
122impl crate::Writable for MasterSpec {
123    type Safety = crate::Unsafe;
124    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
125    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
126}
127#[doc = "`reset()` method sets MASTER to value 0"]
128impl crate::Resettable for MasterSpec {
129    const RESET_VALUE: u32 = 0;
130}
atsamd11c/mtb/master.rs

atsamd11c/mtb/
master.rs
