atsamd11c/dac/
ctrlb.rs
1#[doc = "Register `CTRLB` reader"]
2pub type R = crate::R<CtrlbSpec>;
3#[doc = "Register `CTRLB` writer"]
4pub type W = crate::W<CtrlbSpec>;
5#[doc = "Field `EOEN` reader - External Output Enable"]
6pub type EoenR = crate::BitReader;
7#[doc = "Field `EOEN` writer - External Output Enable"]
8pub type EoenW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `IOEN` reader - Internal Output Enable"]
10pub type IoenR = crate::BitReader;
11#[doc = "Field `IOEN` writer - Internal Output Enable"]
12pub type IoenW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `LEFTADJ` reader - Left Adjusted Data"]
14pub type LeftadjR = crate::BitReader;
15#[doc = "Field `LEFTADJ` writer - Left Adjusted Data"]
16pub type LeftadjW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `VPD` reader - Voltage Pump Disable"]
18pub type VpdR = crate::BitReader;
19#[doc = "Field `VPD` writer - Voltage Pump Disable"]
20pub type VpdW<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `BDWP` reader - Bypass DATABUF Write Protection"]
22pub type BdwpR = crate::BitReader;
23#[doc = "Field `BDWP` writer - Bypass DATABUF Write Protection"]
24pub type BdwpW<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Reference Selection\n\nValue on reset: 0"]
26#[derive(Clone, Copy, Debug, PartialEq, Eq)]
27#[repr(u8)]
28pub enum Refselselect {
29 #[doc = "0: Internal 1.0V reference"]
30 Int1v = 0,
31 #[doc = "1: AVCC"]
32 Avcc = 1,
33 #[doc = "2: External reference"]
34 Vrefp = 2,
35}
36impl From<Refselselect> for u8 {
37 #[inline(always)]
38 fn from(variant: Refselselect) -> Self {
39 variant as _
40 }
41}
42impl crate::FieldSpec for Refselselect {
43 type Ux = u8;
44}
45impl crate::IsEnum for Refselselect {}
46#[doc = "Field `REFSEL` reader - Reference Selection"]
47pub type RefselR = crate::FieldReader<Refselselect>;
48impl RefselR {
49 #[doc = "Get enumerated values variant"]
50 #[inline(always)]
51 pub const fn variant(&self) -> Option<Refselselect> {
52 match self.bits {
53 0 => Some(Refselselect::Int1v),
54 1 => Some(Refselselect::Avcc),
55 2 => Some(Refselselect::Vrefp),
56 _ => None,
57 }
58 }
59 #[doc = "Internal 1.0V reference"]
60 #[inline(always)]
61 pub fn is_int1v(&self) -> bool {
62 *self == Refselselect::Int1v
63 }
64 #[doc = "AVCC"]
65 #[inline(always)]
66 pub fn is_avcc(&self) -> bool {
67 *self == Refselselect::Avcc
68 }
69 #[doc = "External reference"]
70 #[inline(always)]
71 pub fn is_vrefp(&self) -> bool {
72 *self == Refselselect::Vrefp
73 }
74}
75#[doc = "Field `REFSEL` writer - Reference Selection"]
76pub type RefselW<'a, REG> = crate::FieldWriter<'a, REG, 2, Refselselect>;
77impl<'a, REG> RefselW<'a, REG>
78where
79 REG: crate::Writable + crate::RegisterSpec,
80 REG::Ux: From<u8>,
81{
82 #[doc = "Internal 1.0V reference"]
83 #[inline(always)]
84 pub fn int1v(self) -> &'a mut crate::W<REG> {
85 self.variant(Refselselect::Int1v)
86 }
87 #[doc = "AVCC"]
88 #[inline(always)]
89 pub fn avcc(self) -> &'a mut crate::W<REG> {
90 self.variant(Refselselect::Avcc)
91 }
92 #[doc = "External reference"]
93 #[inline(always)]
94 pub fn vrefp(self) -> &'a mut crate::W<REG> {
95 self.variant(Refselselect::Vrefp)
96 }
97}
98impl R {
99 #[doc = "Bit 0 - External Output Enable"]
100 #[inline(always)]
101 pub fn eoen(&self) -> EoenR {
102 EoenR::new((self.bits & 1) != 0)
103 }
104 #[doc = "Bit 1 - Internal Output Enable"]
105 #[inline(always)]
106 pub fn ioen(&self) -> IoenR {
107 IoenR::new(((self.bits >> 1) & 1) != 0)
108 }
109 #[doc = "Bit 2 - Left Adjusted Data"]
110 #[inline(always)]
111 pub fn leftadj(&self) -> LeftadjR {
112 LeftadjR::new(((self.bits >> 2) & 1) != 0)
113 }
114 #[doc = "Bit 3 - Voltage Pump Disable"]
115 #[inline(always)]
116 pub fn vpd(&self) -> VpdR {
117 VpdR::new(((self.bits >> 3) & 1) != 0)
118 }
119 #[doc = "Bit 4 - Bypass DATABUF Write Protection"]
120 #[inline(always)]
121 pub fn bdwp(&self) -> BdwpR {
122 BdwpR::new(((self.bits >> 4) & 1) != 0)
123 }
124 #[doc = "Bits 6:7 - Reference Selection"]
125 #[inline(always)]
126 pub fn refsel(&self) -> RefselR {
127 RefselR::new((self.bits >> 6) & 3)
128 }
129}
130impl W {
131 #[doc = "Bit 0 - External Output Enable"]
132 #[inline(always)]
133 #[must_use]
134 pub fn eoen(&mut self) -> EoenW<CtrlbSpec> {
135 EoenW::new(self, 0)
136 }
137 #[doc = "Bit 1 - Internal Output Enable"]
138 #[inline(always)]
139 #[must_use]
140 pub fn ioen(&mut self) -> IoenW<CtrlbSpec> {
141 IoenW::new(self, 1)
142 }
143 #[doc = "Bit 2 - Left Adjusted Data"]
144 #[inline(always)]
145 #[must_use]
146 pub fn leftadj(&mut self) -> LeftadjW<CtrlbSpec> {
147 LeftadjW::new(self, 2)
148 }
149 #[doc = "Bit 3 - Voltage Pump Disable"]
150 #[inline(always)]
151 #[must_use]
152 pub fn vpd(&mut self) -> VpdW<CtrlbSpec> {
153 VpdW::new(self, 3)
154 }
155 #[doc = "Bit 4 - Bypass DATABUF Write Protection"]
156 #[inline(always)]
157 #[must_use]
158 pub fn bdwp(&mut self) -> BdwpW<CtrlbSpec> {
159 BdwpW::new(self, 4)
160 }
161 #[doc = "Bits 6:7 - Reference Selection"]
162 #[inline(always)]
163 #[must_use]
164 pub fn refsel(&mut self) -> RefselW<CtrlbSpec> {
165 RefselW::new(self, 6)
166 }
167}
168#[doc = "Control B\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrlb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrlb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
169pub struct CtrlbSpec;
170impl crate::RegisterSpec for CtrlbSpec {
171 type Ux = u8;
172}
173#[doc = "`read()` method returns [`ctrlb::R`](R) reader structure"]
174impl crate::Readable for CtrlbSpec {}
175#[doc = "`write(|w| ..)` method takes [`ctrlb::W`](W) writer structure"]
176impl crate::Writable for CtrlbSpec {
177 type Safety = crate::Unsafe;
178 const ZERO_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
179 const ONE_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
180}
181#[doc = "`reset()` method sets CTRLB to value 0"]
182impl crate::Resettable for CtrlbSpec {
183 const RESET_VALUE: u8 = 0;
184}